JP2003007702A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of steps on a surface to be polished due to the difference in the polishing rate by CMP in holes or regions of groove pattern with high and low densities on the semiconductor surface. SOLUTION: In the manufacturing method of semiconductor devices, the hole or an entire formation surface of a groove pattern 12 is covered for forming a conductive layer 13 on an insulating layer 11, impurities (P, B, and As) having a higher polishing rate than the conductive layer are implanted to the hole or the conductive layer 13 that is formed in a region where a groove pattern density is low, and the conductive layer is polished and removed by a CMP to obtain a uniform polishing surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, which is characterized by a method of polishing a conductor material.

[0002]

2. Description of the Related Art Doped polysilicon is widely used for filling contact plugs, capacitors, etc. in DRAM (Dynamic Random Access Memory), and the conventional etchback method is generally used as a flattening method. Met. However, the demand for flattening of the interlayer insulating film and particles has become stricter year by year due to the multi-layering and miniaturization accompanying the high integration of LSI in recent years. A polishing method (hereinafter, CMP polishing) has come to be used.

As shown schematically in FIG. 2, this CMP polishing apparatus comprises a rotatable surface plate 1, a polishing head 3 and a conditioner 7 which are arranged on the rotatable surface plate 1 so as to be vertically movable and rotatable. There is. On the surface plate 1, a polishing pad 5
While the slurry 2 is dropped through the slurry supply nozzle 6 and the object to be polished, such as the wafer 4, attached to the head 3 is pressed against the surface of the pad 5, the surface plate 1 and the head 3 are attached. Polishing is performed with the slurry by using a rotating force.

FIGS. 3A to 3D show, in order, a conventional polysilicon polishing process using this CMP apparatus, taking contact plug formation as an example. Figure 3
A is a cross-sectional view showing the patterned interphase insulating film 11, which is formed on a Si substrate which has been subjected to normal LSI processing. This structure is formed by, for example, masking a resist patterned by a normal photolithography process and performing dry etching to obtain a contact hole diameter of 0.
It can be obtained by forming a connection hole having a thickness of 25 μm and a depth of 650 nm (step 1).

Next, a film thickness of 250 n is formed on the interlayer insulating film 11 having the pattern shown in FIG. 3A by the LPCVD method.
m poly-silicon is deposited over the entire area to fill the connection holes and make the entire surface flat (step 2). FIG. 3B is a sectional view showing this state. Subsequently, the deposited polysilicon is polished and removed by a CMP apparatus. That is, a semiconductor substrate having a polysilicon film formed thereon is mounted on a polishing head, pressed against a polishing pad while supplying a slurry, and polished and removed by rotation of the polishing head and the polishing pad (step 3).

If the polishing by the CMP method is performed uniformly here, a contact plug having a flat surface as shown in FIG. 3C should be obtained. However, in reality, a flat processed surface as shown in FIG. 3C cannot be obtained, and particularly in a region having a high pattern density such as a memory cell portion, both the pattern and the interlayer insulating film become thinner than other regions, so-called erosion. (Draining of the film thickness due to over-processing) occurs, and as shown in FIG. 3D, the variation in the film reduction amount becomes large between a region having a low pattern density and a region having a high pattern density, and a step is generally generated.

As a result, a level difference is generated in a region having a high pattern density and a region having a low pattern density, so that the flatness is deteriorated and the characteristics of the element, the yield, and the reliability such as a short circuit are lowered.

[0008]

This phenomenon is caused by partially removing the conductive material (polysilicon) remaining in the recesses (pattern) on the surface of the insulating film after the polysilicon 3 is removed by polishing the upper portion of the pattern. It occurs when removing by polishing, and the reason is due to the difference in polishing selection ratio between the filling material (polysilicon) and the base insulating film, that is, the polishing rate. Therefore,
An object of the present invention is to prevent a step corresponding to a difference in polishing rate from occurring in a region having a high pattern density and a region having a low pattern density.
P is to create a polished surface with high flatness.

[0009]

The object of the present invention is achieved by substantially eliminating the polishing selection ratio between the filling material (polysilicon) and the underlying insulating film. In particular,
The invention of claim 1 comprises the step of forming a hole or groove pattern in an insulating layer formed on a substrate, the step of forming a conductive layer on the insulating layer so as to cover the entire surface of the hole or groove pattern formation surface, the hole or A method for manufacturing a semiconductor device, comprising a step of ion-implanting an impurity having a polishing rate higher than that of a conductive layer into a conductive layer formed in a region having a low groove pattern density, and then polishing and removing the conductive layer. is there.

According to a second aspect of the present invention, a step of forming a hole or a groove in the interlayer insulating layer formed on the substrate, and a step of forming a conductive layer on the interlayer insulating layer covering the entire surface of the hole or groove of the substrate. Forming step, forming a resist layer on the conductive layer in which the holes or grooves are formed, and implanting an impurity having a polishing rate higher than that of the conductive layer into the conductive layer other than the resist layer forming portion To form an impurity injection layer, and a CMP polishing step of removing the resist layer and then CMP polishing the conductive layer to fill only holes or grooves. It is a method of manufacturing a device.

A third aspect of the present invention is the method of manufacturing a semiconductor device according to the first or second aspect, wherein the conductive material is polysilicon.

According to a fourth aspect of the present invention, in the polishing method according to the first or second aspect, the impurity is at least one of P, B, and As, and the ion implantation probe has a film thickness of the conductive layer. It is a method of manufacturing a semiconductor device, characterized in that

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The polishing method of the present invention will be described with reference to the embodiments shown in FIGS. 1A to 1E. Figure 1A
FIG. 3B is a diagram showing a cross-sectional structure of the interlayer insulating film 11 on which the pattern 12 is formed and is similar to FIG. 3A. The interlayer insulating film is
It is formed on a Si substrate that has been subjected to normal LSI processing. This structure is similar to the structure described above, for example, by dry-etching the resist patterned in the photolithography process, and the contact hole diameter: 0.
It can be obtained by forming a connection hole having a thickness of 25 μm and a depth of 650 nm (step 1).

Next, as shown in FIG. 1A, a film thickness of 250 is formed by LPCVD on the interlayer insulating film 11 having a pattern of holes (contact holes) or grooves (trench) formed therein.
A polysilicon film having a thickness of nm is formed on the entire surface to fill the connection hole and to form a flat surface as a whole (step 2). FIG. 1B is a sectional view showing this state.

Subsequently, a resist film 14 is applied, and patterning is performed so that the resist film in the region having a low pattern density is removed (step 3). FIG. 1C is a sectional view showing this state. Further, in the state shown in FIG. 3, P ion implantation is performed in an area where the polysilicon 13 is exposed, that is, a region having a low pattern density to form an impurity implantation layer 15 (step 4). FIG. 1D shows this state. At this time, the P implantation probe does not exceed the polysilicon film thickness, which is 250 nm in this embodiment. The ion species to be implanted may be at least one of P (adjacent), B (boron), and As (arsenic), and it is of course possible to perform ion implantation by combining these. By implanting these impurities, the polishing rate of the polysilicon layer, which is a region having a low pattern density, is increased and becomes approximately the same as that of the region having a high pattern density. If necessary, the polysilicon layer may be doped with impurities P, B, and As in step 3.

After the polysilicon layer is doped with impurities in step 4, the resist film 14 is ashed.
Are removed (step 5), and then the polysilicon is removed by polishing with a CMP apparatus (step 6). By performing the above steps, the polysilicon is polished in the region having a high pattern density and the region having a low pattern density at the same polishing rate, and as a result, a flat surface having no step can be obtained. FIG. 1D is a sectional view showing this state.

Polishing of the CMP apparatus in the examples was carried out under the following conditions. The operating temperature of the CMP apparatus is 25 to 30 ° C., and the friction pad 5 is composed of a laminate of a non-woven fabric and a suede pad formed of vertically foamed polyurethane (Supreme RN-H manufactured by Rodel Co.) as a friction pad. The rotation speed of the platen and polishing head is
Both polishing heads at 50 rpm, polishing pressure 150 g / c
At m ² , the slurry was an alkaline slurry containing colloidal silica, and polishing was performed while supplying the slurry on the pad 5 of the surface plate 1 at a flow rate of 200 mI / min. By this polishing, the deposited polysilicon other than that filled in the connection holes was completely removed. As a result, the difference in the film reduction amount between the peripheral circuit region having a low pattern density and the memory cell region having a high pattern density was eliminated, and a flat polished surface was obtained as a whole.

By the way, it has been found that the occurrence of erosion increases exponentially as the pattern density increases, and in particular, the pattern density becomes remarkable from around 60 to 70%. The area having a high pattern density can be 60 to 70% or more and at least 70% or more, and the area having a low pattern density can be a region having a pattern density of 30 to 40% or less and at least 30% or less. Therefore, in the present invention, a region having a high pattern density or a region having a low pattern density means a pattern density of 60% or more or 40% or less, respectively.

[0019]

According to the present invention, in polishing a wafer having a pattern, impurities are ion-implanted into a region having a low pattern density to eliminate a difference in polishing rate between a region having a high pattern density and a region having a low pattern density. Therefore, it is possible to suppress the occurrence of a step on the surface of the wafer when polishing with the CMP apparatus, and improve the flatness after polishing. Further, this improves the characteristics, yield and reliability of the device.

[Brief description of drawings]

FIG. 1 is a diagram for explaining each step in a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a perspective view schematically showing a CMP apparatus.

FIG. 3 is a diagram for explaining each step in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 ... Surface plate, 2 ... Slurry, 3 ... Head, 4 ... Wafer, 5 ... Polishing pad, 6 ... Slurry supply nozzle, 11
... Interlayer insulating film, 12 ... Pattern, 13 ... Polysilicon, 14 ... Resist film, 15 ... Impurity injection layer,

Claims (4)

[Claims] 1. A step of forming a hole or groove pattern in an insulating layer formed on a substrate, a step of forming a conductive layer on the insulating layer so as to cover the entire surface of the hole or groove pattern formation surface, the hole or groove pattern A method of manufacturing a semiconductor device, comprising: a step of ion-implanting an impurity having a polishing rate higher than that of a conductive layer into a conductive layer formed in a region having a low density, and thereafter polishing and removing the conductive layer. 2. A step of forming a hole or a groove in an interlayer insulating layer formed on a substrate, a step of forming a conductive layer on the interlayer insulating layer so as to cover the entire surface of the hole or groove of the substrate. A step of forming a resist layer on the conductive layer in which the holes or grooves are formed, and an impurity injection layer by injecting an impurity having a polishing rate higher than that of the conductive layer into the conductive layer other than the resist layer forming portion And a CMP polishing step of performing CMP polishing until the conductive layer is filled only in the holes or trenches after the resist layer is removed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductor material is polysilicon. 4. The polishing processing method according to claim 1, wherein the impurity is composed of at least one of P, B, and As, and the ion implantation probe does not exceed the thickness of the conductive layer. A method for manufacturing a characteristic semiconductor device.