JP2003007005A - Data synchronization detecting method, data recorder using this method, information recording medium used for this method, data synchronization signal detector, signal processor using this and information recording and reproducing device provided with these - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information recording and reproducing device in which the performance deterioration of information reproduction is reduced by reducing the erroneous detection of a data synchronization signal in the detection of the data synchronization signal and varying a retry method depending on whether the main cause of an error in occurrence of a retry error when information reproduction is the erroneous detection of the data synchronization signal, so as to perform optimal retry. SOLUTION: A guard signal 33 for preventing the erroneous detection of the data synchronization signal 32 is added to a data signal 34 being recorded information continuously after the signal 32 for synchronizing data to prevent the occurrence of the erroneous detection of the signal 32 even when the signal 32 is not detected at its normal position. A data signal resulting from delaying the detection output of the signal 32 by the length of the guard signal and reproducing it is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording / reproducing apparatus, and more particularly to data sync signal detection for preventing erroneous detection of the data sync signal when the data sync signal cannot be detected at the position of the regular data sync signal. Regarding the device.

[0002]

2. Description of the Related Art An example of a conventional data synchronization signal detecting device will be described below with reference to the drawings.

A conventional method will be described by taking a magnetic disk device as an example. FIG. 13 shows an example of the recording format 10 of the magnetic disk device and the detection timing of the data synchronization signal. Data is recorded or reproduced on a recording medium for each sector that is a unit storage area. Each sector has a PLL (Phase Lo) that performs clock synchronization.
PLO_SYNC3 for pulling in cked Loop)
1. A data synchronization signal 32 for detecting the start position of DATA to obtain a demodulation timing signal of a modulated code, a DATA section 34 for actually recording and reproducing data, and a CRC section ECC for error detection and correction. There is a section 35.
A GAP unit 36, which is a pattern for absorbing various delay times, is provided between each sector.

Further, FIG. 14 shows the structure of a reproducing system for detecting a data synchronization signal. Format 10 of FIG.
Play back the information configured as
Is input to the equalizer 81. The equalizer 81 equalizes the signal and outputs it as an equalizer output 92. The data discriminating means 82 inputs the equalizer output 92, performs data discrimination, and outputs it as a data discrimination output 93. The data discrimination output 93 is input to the serial / parallel conversion means or the code demodulation means 83 and the data synchronization signal detection means 84. The data sync signal detecting means 84 detects the data sync signal and outputs a data sync signal detection output 94. The serial / parallel conversion means or the code demodulation means 83 performs serial / parallel conversion or code demodulation on the data bit string of the data discrimination output 93 at the timing of the data synchronization signal detection output 94, and outputs it as a reproduction data output 95.

It is well known that the accurate detection of the data synchronization signal 32 is very important for the subsequent code demodulation of the DATA section 34. In other words, even if the data demodulated by the DATA unit 34 has a very good error rate, if the data synchronization signal 32, which is normally about several bytes, is erroneously detected, the D of several tens to several hundreds of bytes after that is detected.
This is because the code demodulation of the ATA unit 34 is not performed correctly.

The data sync signal detection error rate is an index for knowing the detection performance of the data sync signal 32. This is the number of erroneous data sync signal detections divided by the total number of data sync signal detections. Here, the data sync signal is erroneously detected when the data sync signal is detected before the regular data sync signal detection position or when the data sync signal cannot be detected at the regular data sync signal detection position. Is. In order to detect the updated data synchronization signal 32 more accurately, a period during which the data synchronization signal 32 can be detected is provided, for example, the enable signal 12. This period is set so as to cover the relative fluctuations of the reproduction signal and the enable signal.

If the data sync signal detection output 94 is output as the data sync signal detection output signal 16 of FIG. 13 while the enable signal 12 is "H", it means that the data sync signal is detected. In some cases, the data sync signal is detected before the normal data sync signal detection position.
It is a portion indicated by 23 of 3. Therefore, in order to improve the data synchronization signal detection error rate, it is necessary to prevent the portion indicated by 23 from being erroneously detected and to perform the data synchronization signal detection more reliably at the regular data synchronization signal detection position. Is.

When the data sync signal is detected before the normal data sync signal detection position, the reproduction process is performed assuming that the data sync signal is normally detected by the incorrect data sync signal detection output 94. Since the serial-parallel conversion means or the code demodulation means 83 will erroneously demodulate the data code, data error detection and correction by the reproduction signal of the CRC section ECC section 35 will be performed. However, since the data code demodulation is incorrect, there are many errors and correct data cannot be obtained. Therefore, the retry is executed.

If the data sync signal cannot be detected up to the normal data sync signal detection position, the data sync signal detection output 94 is not detected and a retry is performed. However, in reality, when the data sync signal detection output 94 cannot be generated at the regular data sync signal detection position, the data sync signal detection output 94 is erroneously detected by the data signal part which reproduced the DATA part 34 thereafter. There is a possibility that
For example, the data sync signal detection output 94 is output as the data sync signal erroneous detection pulse 20 at an erroneous position like the data sync signal detection output signal 19 of FIG. This is the part indicated by 24 in FIG. In the portion of 24, even if the data synchronization signal detection output is generated or not, it is already erroneous as the data synchronization detection and does not affect the data synchronization signal detection error rate.

However, if the data sync signal detection output is erroneously generated in this 24 part, the erroneous data sync signal is detected as in the case where the data sync signal is detected before the previous normal data sync signal detection position. Playback processing is performed assuming that the data sync signal is detected normally by the detection output.
CRC section EC due to erroneous data code demodulation
Data error detection and correction based on the reproduction signal of the C unit 35 will be performed.

However, since the data code demodulation is erroneous, many errors exist, correct data cannot be obtained, and retry is executed. In this case, since the data sync signal detection output cannot be obtained at the regular data sync signal detection position, it is necessary to select a retry method that is effective in improving the data sync signal detection. Therefore, a retry method that is effective in reducing errors in the data section is selected, and it takes time to arrive at a retry method that is effective in detecting the data synchronization signal.

Alternatively, even if a retry method that has an improving effect on the detection of the data synchronization signal is first carried out because there are many errors in the data, the error in the data is actually caused due to the poor signal quality of the data part. In many cases, it may take time to reach a retry method that has an improving effect.

For this reason, it is necessary to combine a retry method having an improvement effect on the detection of the data synchronization signal even when the data synchronization signal detection output is possible, resulting in an increase in the number of retry processes, resulting in a performance error. Will be deteriorated.

As a technique for dealing with erroneous detection at the portion indicated by 23, for example, Japanese Patent Laid-Open No. 11-96
Some methods try to obtain a correct data sync signal detection output by removing a wrong data sync signal detection output by the method disclosed in Japanese Patent No. 681. However, this is also 24
I can not deal with the part of.

[0015]

As described above, if the data sync signal detection output cannot be obtained up to the normal data sync signal detection position, the data sync signal is erroneously detected in the subsequent data section. , Data error detection and correction, delay of retry determination as a result, and further it takes time to obtain appropriate retry parameter settings in retry, therefore data reproduction in retry There is a technical problem in that Therefore, in the present invention, it is necessary to prevent the data synchronization signal from being detected after the regular data synchronization signal detection position. Further, it is necessary to reliably detect a detection error in the data synchronization signal, set an optimum retry parameter, and retry to prevent the data reproduction performance from being deteriorated during the retry. Furthermore, it is also necessary that the structure of the data synchronization signal detection means be easy and that it be realized with a small circuit scale.

The present invention solves the above problems,
It is an object of the present invention to provide a data synchronization signal detection device that can appropriately perform a retry process even if a detection error occurs.

[0017]

In order to solve the above problems, the first object of the present invention is to provide a guard signal section for preventing erroneous detection of the data synchronization signal subsequent to the data synchronization signal. By doing so, it becomes possible to prevent the detection of the data synchronization signal from occurring after the regular data synchronization signal detection position. A guard pattern writing unit for writing the guard signal portion on the recording medium is also provided. Further, during reproduction, since the data immediately after the data sync signal detection output is output is the guard signal section, a delay means for delaying the data sync signal detection output by the length of the guard signal section is provided.

Secondly, the method of changing the parameter at the time of retry is changed depending on the presence / absence of the data sync signal detection output. Specifically, if there is a data sync signal detection output, a parameter that reduces errors in the data section is set and retried, and if there is no data sync signal detection output, it is effective in detecting the data sync signal. It is to set a certain parameter and retry. By doing this,
Appropriate parameters can be set, and data can be reproduced more quickly and surely.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

A data synchronization signal detecting apparatus according to the first embodiment of the present invention will be described below with reference to FIGS.

First, the format of the embodiment of the present invention will be described with reference to part of FIG. 11 in FIG. 1 is
This indicates the format on the recording medium when recording information. Here, one sector, which is a recording unit of information, is shown. For each sector, P is used to perform clock synchronization.
PLO for pulling in LL (Phase Locked Loop)
_SYNC31, a data synchronization signal 32 for detecting the start position of DATA and obtaining a demodulation timing signal of the modulated code (= taking data synchronization), a guard for preventing the data synchronization signal from being erroneously detected Signal 33, DATA section (data signal) 3 for actually recording and reproducing data
4. Furthermore, CRC part ECC for error detection and correction
There is a section 35. A GAP unit 36, which is a pattern for absorbing various delay times, is provided between each sector.

Next, the configuration of the first embodiment will be described with reference to FIG. FIG. 3 is a diagram for explaining the configuration of a reproducing system including the data synchronization signal detecting means. The information configured as the format 11 in FIG. 1 is reproduced and input to the equalizer 41 as a reproduction data input 51. The equalizer 41 equalizes the signal and outputs it as an equalizer output 52. The data discriminating means 42 inputs the equalizer output 52, performs data discrimination, and outputs a discrimination bit string as the data discrimination output 53. The data discrimination output 53 is input to the serial / parallel conversion means or the code demodulation means 43 and the data synchronization signal detection means 44. The data sync signal detecting means 44 detects the data sync signal and outputs a data sync signal detection output 54. As the method of detecting the data synchronization signal by the data synchronization signal detecting means 44, the conventional method can be applied as it is.

The data sync signal detection output 54 is output to the serial / parallel conversion means or the code demodulation means 43 as the data discrimination output 53.
To a parallel bit or a timing to be the basis of demodulation for code demodulating the data discrimination output 53. The delay unit 45, which is a delay means, delays the data synchronization signal detection output 54 by a predetermined time and outputs the data synchronization signal detection delay output 55. The purpose of delaying the data sync signal detection output 54 by the delay device 45 is that the data sync signal detection output 54 is output because a signal corresponding to the data sync signal 32 of FIG. Then, the data discriminating means 42 outputs the guard signal 33 which is not data.
That is, the delay time until the true data is output from the data discriminating means 42 is absorbed. Therefore,
The delay amount of the delay device 45 corresponds to the length of the guard signal 33.

In the serial / parallel conversion means or code demodulation means 43 which has a role as data output means, the data bit string of the data discrimination output 53 is subjected to serial / parallel conversion or code demodulation at the timing of the data sync signal detection delay output 55 and reproduced. It is output as the data output 56.

Returning to FIG. 1 again, the timing for detecting the data synchronization signal will be described. In order to detect the data synchronization signal 32 more accurately, a period during which the data synchronization signal 32 can be detected is given, for example, as the enable signal 12. Normally, the control signal for reproduction and the reproduction signal reproduced from the recording medium are caused by fluctuations in the rotation of the motor that rotates the recording medium, fluctuations in the clock that operates the control circuit, etc.
Since the relative position fluctuates, it is generated in a period that can absorb those fluctuations. The portion 21 that reflects the data sync signal detection error rate can be made by carefully selecting the bit pattern sequence of the data sync signal 32.

Since this portion is the PLO_SYNC 31 and the data synchronization signal 32, it can be taken into consideration. In addition, as in the present invention, the guard signal 33 is changed to the data synchronization signal 3
In order to prevent an error occurring in the data synchronization signal detection error from occurring in the data synchronization signal 32 and the guard signal 33 even in the portion 22 which is not reflected in the data synchronization signal detection error rate, by arranging after 2 It is possible to carefully select the bit pattern sequence of the data synchronization signal 32, similarly to the front side of the data synchronization signal 32.

As a result, the data sync signal detection output 54 in the portion 22 which is not reflected in the data sync signal detection error rate.
Error detection can be reduced. Therefore, the data sync signal detection output 54 is the data sync signal detection output signal 1
It becomes extremely rare to generate the data synchronization signal erroneous detection pulse 18 as in the case of No. 7. In addition, the data synchronization signal 32
The guard signal 33 may have the same bit pattern sequence as that of the PLO_SYNC 31 in order to prevent the data synchronization signal detection error from occurring with respect to the error occurring between the guard signal 33 and the guard signal 33.

Next, the required length of the guard signal 33 will be described with reference to FIG. The format 11 is the same as that in FIG. The data sync signal detection output signal 16 represents the timing when the data sync signal detection output 54 is correctly detected. In the enable signal 13, the relative position of the control signal for reproduction (including the enable signal 13) and the reproduction signal reproduced from the recording medium fluctuates, and the control signal can be generated relatively earliest. It represents the state. Most of the period of the enable signal 13 overlaps the portion 21 that reflects the data sync signal detection error rate, and is not erroneously detected after the normal data sync signal detection position.

On the contrary, in the enable signal 14, the relative position of the control signal for reproduction (including the enable signal 14) and the reproduction signal reproduced from the recording medium fluctuates, and the control signal is relatively the most. It represents a state that can occur late. Most of the period of the enable signal 14 overlaps the portion 22 which is not reflected in the data synchronization signal detection error rate,
It is necessary to consider the case where the data is erroneously detected after the normal data sync signal detection position.

Therefore, even in this state, the guard signal 33 is required to have a length so that it cannot be erroneously detected after the normal data sync signal detection position, and it corresponds to the time when the enable signal is "H". I understand. However, the guard signal 33 can be made slightly shorter than the time during which the enable signal is "H". This can be done by considering the pattern length of the data synchronization signal 32, the detection condition of the data synchronization signal 32, the probability that the control signal will occur relatively late, and the like.

Next, with reference to FIG. 4, signals of respective parts in the configuration of FIG. 1 will be described. RG50 for playback operation
Becomes "H", the reproducing operation is started, and the data discriminating means 42 outputs the data discriminating output 53. Portions corresponding to the PLO_SYNC 31, the data synchronization signal 32, the guard signal 33, and the DATA unit 34 are output with time. If the data discrimination output 53 outputs a portion corresponding to the data synchronization signal 32 and the data synchronization signal detecting means 44 detects the data synchronization signal 32 while the enable signal 58 is "H", the data synchronization signal detection output 54 is obtained. Is output. The delay unit 45 outputs the data synchronization signal detection delay output 55 after a delay 57 corresponding to the time corresponding to the guard signal 33. By the data synchronization signal detection delay output 55, the serial / parallel conversion means or the code demodulation means 43 to the DATA unit 34
A signal corresponding to is output.

The structure of the recording system for recording information according to the second embodiment of the present invention will be described below with reference to FIG.

First, a signal corresponding to the DATA section 34 is input to the code modulator 61 as a recording data input 71,
The information to be recorded is code-modulated and output as modulated record data 72. Modulation record data 72, PLO_SYNC
The pattern 73, the SYNC_BYTE pattern 74, and the guard pattern 75 are input to the signal selection unit 62, and the control signal 76 from the control circuit 63 selects each signal as in the format 11 of FIG. The output 77 is output. In the P / S converter 64,
The data of the selective output 77 is converted into the data of the serial bit string, and the serial data 78 is output. The serial data 78 is recorded and corrected by the recording correction circuit 65, is output as a recording data output 79, and is written on the information recording medium.

Here, the modulated recording data 72, PLO_
SYNC pattern 73, SYNC_BYTE pattern 7
4, the guard pattern 75 is input to one signal selection unit 62, but any one of the signals may be selected as the recording data while being output as the recording data output 79. There are many configurations. For example, P
The LO_SYNC pattern 73 and the SYNC_BYTE pattern 74 can be input before the code modulator 61, and the PLO_SYNC pattern 73 can be input as a serial data string after the P / S converter 64. Further, the PLO_SYNC pattern 73 and the guard pattern 75 may be the same pattern.

FIG. 6 shows the third embodiment of the present invention.
The flow chart of data reading is shown.

The normal data read process in the case of no error starts from 110, and prepares for data read at 111. Here, for example, setting of parameters for reading data, seeking to the data sector, and the like are performed. When the preparation is completed, the data is read out at 112. At this time, the data synchronization signal is also detected. At 113, it is determined whether or not the data synchronization signal can be detected. When the data synchronization signal can be detected in 113, it is determined in 114 whether the data can be read correctly. When the data including the correctable error is read correctly, the data read in 115 is transferred to the host device, and 1
It ends at 24.

When the data synchronization signal cannot be detected as a result of the determination in 113, the retry sequence for reading data again is started. If the number of retries is counted at 116, the number of retries count is determined at 117, and if it is within the limit number, 118
Change the parameter of the data synchronization signal detection method according to the number of retries. Specifically, it is to select a pattern matching threshold value or a pattern to be matched. In this way, the parameters are changed, the data is read again at 112, and when the data synchronization signal can be detected at 113, 114 determines whether the data has been read correctly.

At 114, if there is an error in the data and the data cannot be read correctly, the retry sequence for reading the data again starts. At 120, the number of retries is counted, at 121, the retry count value is judged, and if it is within the limit number, 122 is used to change the parameter for data reproduction according to the retry count. Specifically, it is a coefficient of a filter, or off-track reproduction is performed. In this way, the parameters are changed and the data is read again at 112. In this way, when the correct data can be read, the process proceeds from 114 to 115, 115 transfers the data to the host device, and 124 ends.

If the data synchronization cannot be detected even if the retries are repeated at 117 and the number of retries exceeds the limit number, it is reported at 119 that the data cannot be read out to the host device, and the process ends at 124. Similarly, if correct data is not obtained even if the retry is repeated at 121 and the limit number of times of retry is exceeded, at 123, the fact that the data cannot be read is reported to the host device, and the process ends at 124.

It is also possible to combine the reports that the data of 119 and 121 cannot be read into one. The number of retries may be counted separately for 116 and 120, or may be counted by the same counter. Furthermore, the limit number of retries may be different between 117 and 121, or may be the same value.

As a fourth embodiment of the present invention, USP
It is also possible to support a data format format having a plurality of data synchronization patterns disclosed in 5,844,920. FIG. 7 shows an example in which the present invention is applied to a format format for recording / reproducing on / from those recording media.

FIG. 7A shows a case where the data synchronization signal is arranged at two places. PLO_SYNC 31, data synchronization signal 32, guard signal 33, first DATA unit 10
1, second PLO_SYNC 103, second data synchronization signal 104, second guard signal 105, second DATA
There are a unit 102, a CRC unit ECC unit 35, and a GAP 36.
A guard signal follows each of the two data synchronization signals.

FIG. 7B shows an example of FIG. 7A.
This is the case where the second PLO_SYNC 103 is not included.
The third guard signal 106 and the second guard signal 105 are arranged before and after the PLO_SYNC 31, the data synchronization signal 32, the guard signal 33, the first DATA unit 101, and the second data synchronization signal 104, and the second DATA unit is arranged. 102, CR
There are a C section ECC section 35 and a GAP 36. The second data synchronization signal 104 requires the third guard signal 106 before the second data synchronization signal 104 to prevent erroneous detection of the data synchronization signal in the first DATA unit 101. .

FIG. 7C is a schematic diagram of the example of FIG. 7A.
This is the case where the first DATA unit 101 is not included. PLO
_SYNC 31, data synchronization signal 32, second PLO_
There are a SYNC 103, a second data synchronization signal 104, a second guard signal 105, a DATA section 34, a CRC section ECC section 35, and a GAP 36. Second data synchronization signal 104
After that, the guard signal 105 is required.

FIG. 7D shows the case where the data synchronization signal is arranged at two locations, one of which is the CRC section and the ECC section 35.
It is an example that is placed after. PLO_SYNC 31, data synchronization signal 32, guard signal 33, DATA section 34,
There are a CRC section ECC section 35, a second data synchronization signal 107, a second guard signal 108, and a GAP 36. Where G
It is assumed that the same pattern data as PLO_SYNC is written in AP36. By doing so, the second data synchronization signal 107 can prevent erroneous detection of the data synchronization signal even when the data is discriminated from the GAP 36 side.

Other than the above, a combination of the examples illustrated here and a configuration in which the number of places for arranging the data synchronization signal is further increased is possible. Further, it is possible to adopt a configuration in which they are applied to a split sector format in which data sectors are separated by servo areas.

A fifth embodiment of the present invention will be described with reference to FIGS.
The operation will be described with reference to FIG. This embodiment is an example in which data synchronization signals are provided at two places, and among the formats listed in the fourth embodiment, FIG.
The format corresponding to (B) is used.

FIG. 8 is a diagram for explaining the structure of the reproducing system including the data synchronization signal detecting means in the structure of the fifth embodiment. Information of the format configured as shown in FIG. 7B is reproduced, and the equalizer 1 is used as a reproduction data input 151.
Enter in 41. The equalizer 141 equalizes the signal and outputs it as an equalizer output 152. Data discrimination means 142
Receives the equalizer output 152, performs data discrimination, and outputs it as a data discrimination output 153. Data discrimination output 1
53 is input to the data synchronizing signal detecting means 143, the data delay device 144 and the data selector 145.

The data synchronizing signal detecting means 143 detects the data synchronizing signals of the first data synchronizing signal 32 and the second data synchronizing signal 104 during the period when the enable signal 154 is "H", and the first data synchronizing signal is detected. Signal detection output 1
55, and outputs the second data synchronization signal detection output 159. As the method of detecting the data synchronization signal by the data synchronization signal detecting means 143, the conventional method can be applied as it is. If they cannot be detected, the first data synchronization signal non-detection output 157 and the second data synchronization signal non-detection output 161 are output. The first data sync signal detection output 155 is input to the delay device 146, delayed by a predetermined time, and output as the first data sync signal detection delay output 156.

First data sync signal undetected output 157
Are input to the delay device 147, delayed by a predetermined time, and output as the first data synchronization signal undetected delay output 158. The second data sync signal detection output 159 is input to the delay device 148, delayed by a predetermined time, and output as the second data sync signal detection delay output 160. First data synchronization signal detection delay output 156, first data synchronization signal non-detection delay output 158, second data synchronization signal detection delay output 160, second data synchronization signal non-detection output 161
Is input to the control circuit 149.

The control circuit 149 serves as a data selector, a timing at which the serial / parallel conversion means or the code demodulation means 150 converts data into parallel bits, or a base for demodulation for code demodulation, based on the input signal. A control signal 163 that gives timing is output. Data delay device 14
4 delays the input data discrimination output 153 for a predetermined time and outputs a data discrimination delay output 165. The data selector 145 inputs the data discrimination output 153, the data discrimination delay output 165, and the supplementary data 164, and selects the data selected by the control signal 162 as the data selection output 1
66 is output.

Serial / parallel conversion means or code demodulation means 15
0 inputs the data selection output 166, and the control signal 163
According to the above, serial-parallel conversion of data, data demodulation, etc. are carried out and output as a reproduction data output 167.

FIG. 9 is a diagram for explaining an example of the case where the first data synchronization signal 32 is detected in the fifth embodiment. First, the RG 170 for the playback operation is "H"
Then, the reproduction operation is started, and the data discrimination output 153 is output from the data discrimination means. Data discrimination output 153
Over time, PLO_SYNC 31, first data synchronization signal 32, first guard signal 33, first DAT
Portions corresponding to the A section 101, the second guard signal 106, the second data synchronization signal 104, the third guard signal 105, and the second DATA section 102 are output.

In the data discrimination output 153, a portion corresponding to the data synchronization signal 32 is output, and if the data synchronization signal detecting means 143 detects the first data synchronization signal 32 while the enable signal 154 is "H", The first data sync signal detection output 155 is output. Delay it 1
At 46, a predetermined time is delayed. The delay amount 171 corresponds to the lengths of the first guard signal 33, the second guard signal 106, the third guard signal 105, and the second data synchronization signal 104. Thus, the delay device 146 outputs the first data synchronization signal detection delay output 156. The control circuit 149 generates the control signal 162 of the data selector 154 based on the first data synchronization signal detection delay output 156, selects the data discrimination delay output 165, and selects the data selection output 166.
Is output.

The data discrimination delay output 165 delays the data discrimination output 153 by the data delay unit 144 for a predetermined time. The delay amount 174 corresponds to the lengths of the portions of the second guard signal 106, the third guard signal 105, and the second data synchronization signal 104. The control circuit 149 also generates a control signal 163 for the serial / parallel conversion means or the code demodulation means 150 based on the first data synchronization signal detection delay output 156.

Serial / parallel conversion means or code demodulation means 15
0 performs serial-parallel conversion or code demodulation of the data selection output 166 according to the control signal 163, and as the reproduction data output 167, the data corresponding to the data synchronization signal 32 and the data corresponding to the first DATA unit 101 are output. Output. When the control circuit 149 processes the data for the length corresponding to the first DATA unit 101, the data selector 154 is switched by the control signal 162 and the data discrimination output 153 is output from the data selection output 166.

This is a portion corresponding to the second DATA portion 102. In this way, the first DATA unit 10
The data corresponding to 1 and the second DATA unit 102 are continuously output as the reproduction data output 167. The purpose of delaying by the data delay unit 144 and the delay unit 146 is to output the first DATA unit 101 and the second DATA unit 102 successively.

FIG. 10 shows the first embodiment in the fifth embodiment.
6 is a diagram illustrating an example in which the second data synchronization signal 104 is detected without detecting the data synchronization signal 32 of FIG. Similar to FIG. 9, the RG 170 for the reproducing operation is “H”.
Then, the reproduction operation is started, and the data discrimination output 153 is output from the data discrimination means. Data discrimination output 153
Over time, PLO_SYNC 31, first data synchronization signal 32, first guard signal 33, first DAT
Portions corresponding to the A section 101, the second guard signal 106, the second data synchronization signal 104, the third guard signal 105, and the second DATA section 102 are output.

The data discrimination output 153 outputs a portion corresponding to the data synchronization signal 32, but the data synchronization signal detecting means 143 detects the first data synchronization signal 32 while the enable signal 154 is "H". However, the enable signal 154 becomes “L”, the first data synchronization signal detection output 155 is not output, and the first data synchronization signal non-detection output 157 is output. The first data sync signal undetected output 157 is delayed by the delay device 147 for a predetermined time. The delay amount 172 is equal to the second guard signal 10
6, third guard signal 105, second data synchronization signal 1
It corresponds to the length of the part 04.

In this way, the delay device 147 outputs the first data sync signal undetected delay output 158. Based on the first data synchronization signal undetected delay output 158, the control circuit 14
At 9, the control signal 162 of the data selector 154 is generated,
The supplementary data 164 is selected and the data selection output 166 is output. Here, since the first data synchronization signal 32 cannot be detected, the data corresponding to the first DATA unit 101 cannot be reproduced, so that data is selected as supplementary data 164 of an arbitrary value. To do.

The control circuit 149 also generates a control signal 163 for the serial / parallel conversion means or the code demodulation means 150 based on the first data synchronization signal undetected delay output 158. The serial / parallel conversion means or code demodulation means 150 performs serial / parallel conversion or code demodulation on the data selection output 166 according to the control signal 163, and reproduces data output 167.
As a result, the data synchronization signal 109 is inserted at the head and the data corresponding to the supplementary data 164 is output. Control circuit 14
In FIG. 9, when the supplementary data 164 corresponding to the length of the first DATA unit 101 is processed, the control signal 162 turns off the data selector 154.

While processing the supplementary data 164, the portion corresponding to the second data synchronization signal 104 is output at the data discrimination output 153, and while the enable signal 154 is "H" in the data synchronization signal detection means 143. When the second data synchronization signal 104 is detected, the second data synchronization signal detection output 159 is output. The delay device 148 delays it for a predetermined time. The delay amount 173 corresponds to the lengths of the third guard signal 105 and the second data synchronization signal 104. In this way, the delay device 148 outputs the second data synchronization signal detection delay output 160.

Second data sync signal detection delay output 160
Based on the above, the control circuit 149 generates the control signal 162 of the data selector 154, the data selector 154 selects the data discrimination output 153, and outputs the data selection output 166. At this time, the processing for the supplementary data 164 has already been completed. The control circuit 149 also generates a control signal 163 for the serial / parallel conversion means or the code demodulation means 150 based on the second data synchronization signal detection delay output 160.

Serial / parallel conversion means or code demodulation means 15
0 performs serial-parallel conversion or code demodulation of the data selection output 166 according to the control signal 163, and outputs the data corresponding to the second DATA unit 102 as the reproduction data output 167.

FIG. 11 shows the first embodiment in the fifth embodiment.
FIG. 6 is a diagram illustrating an example in which the data synchronization signal 32 of No. 2 cannot be detected and the second data synchronization signal 104 cannot be detected. The supplemental data 164 corresponding to the length of the first DATA unit 101 in the first half is processed, and the process up to the point where the data selector 154 is turned off by the control signal 162 is the same, so the description thereof will be omitted. To do.

While processing the supplementary data 164, the portion corresponding to the second data synchronization signal 104 was output at the data discrimination output 153, but the enable signal 154 of the data synchronization signal detection means 143 is "H". In the meantime, the second data synchronization signal 104 cannot be detected, the enable signal 154 becomes “L”, the second data synchronization signal detection output 159 is not output, and the second data synchronization signal undetected. The output 161 is output. The second data sync signal undetected output 161 does not need to be delayed. In the control circuit 149, the control signal 162 of the data selector 154 and the serial / parallel conversion means or the code demodulation means 1
Do not generate 50 control signals 163. The RG 170 is set to "L" by the second data sync signal non-detection output 161, and the reproducing operation is ended. At this time, the supplementary data 164 may still be processed.

In the fifth embodiment, serial data may be converted into parallel data at the input side of the data selector. Further, the supplementary data may be selected after the serial / parallel conversion means or the code demodulation means 150.

Further, also in the case of FIG. 7A, the second guard signal 106 before the second data synchronization signal 104 is PL.
The difference is only O_SYNC 103, which is essentially the same as this embodiment.

In the case of FIG. 7C, PLO_S is between the first data synchronization signal 32 and the second data synchronization signal 104.
YNC103, which corresponds to PLO_SYNC103 in the delay amount of the first data synchronization signal detection output with respect to the first data synchronization signal 32 and the delay amount of the second data synchronization signal detection output with respect to the second data synchronization signal 104. This can be easily realized by providing a difference of.

In the case of FIG. 7D, the second data synchronization signal 107 is in front of the GAP unit 36, but when the second data synchronization signal 107 is used, it is reproduced from the GAP unit 36 side. Except for the number of data synchronization signals, the data synchronization signal detection can be processed in the same manner as in the case of one data synchronization signal.

The enable signal 154 in the description is
Although it is fixedly "H" for a certain period, it may be "L" depending on the detection of the data synchronization signal.

FIG. 12 shows a magnetic disk device according to a sixth embodiment of the present invention. The first to fifth embodiments are used. The magnetic disk device 201 includes a magnetic disk 211, a magnetic head 212, and R / W_AMP2.
13, HDC microcomputer 214, data buffer 215,
Servo processing circuit 216, mechanical system driver 217, VCM
It has 218, a motor 219, a signal processing means 220, and the like. The signal processing means 220 may be the data synchronization signal detecting means, the guard pattern selecting means, or the data reading flow chart according to the embodiment of the present invention, which has the above-described embodiment of FIG. 1 and FIG. 5 or another configuration according to the present invention. Includes controlled signal processing means. The magnetic disk device 201 having this configuration can realize a magnetic disk device that rarely detects a data synchronization signal at an incorrect position.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above description, the data synchronizing signal detecting device according to the present invention has been described by taking the magnetic disk device as an example. However, other than this, a signal processing circuit for information processing, a signal processing device, an integrated circuit, an optical circuit. It can also be used in an information recording / reproducing device such as a magnetic disk device, an optical disk device, and a floppy (registered trademark) disk device, and a data recording device for recording data and signals by the above-mentioned method and data and signals are recorded. It is applicable to a recording medium.

[0075]

As in the present invention, by providing a guard signal for preventing erroneous detection of the data synchronization signal after the data synchronization signal, erroneous detection of the data synchronization signal after the normal data synchronization signal detection position. Therefore, the accuracy of the detected data synchronization signal detection output can be improved. Further, it is possible to carry out an appropriate retry, and it is possible to improve the data reproduction performance at the time of retry.

Further, it becomes possible to improve the data reproducing performance at the time of retry of the signal processing circuit, the information recording / reproducing apparatus, the information transmitting apparatus, etc. using the same.

As a result, when there is a pattern similar to the data synchronization signal at the data head portion, it is possible to eliminate what is erroneously detected at the data head portion due to an error in the data synchronization signal.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the format of the present invention and the timing of data sync signal detection and the like.

FIG. 2 is another diagram for explaining the format format of the present invention and the timing of data sync signal detection and the like.

FIG. 3 is a diagram illustrating a configuration of a reproducing system including a data synchronization signal detecting means according to the present invention.

FIG. 4 is a diagram illustrating a signal and a sequence of each unit illustrated in FIG.

FIG. 5 is a diagram illustrating a configuration of a recording system of the present invention.

FIG. 6 is a diagram illustrating a flowchart at the time of reproducing information including the retry method according to the present invention.

FIG. 7 is a diagram illustrating an example in which the present invention is applied to another format format.

FIG. 8 is a diagram illustrating a configuration of a reproducing system including a data synchronization signal detecting means of an embodiment when there are two data synchronization signals according to the present invention.

FIG. 9 is a diagram illustrating an example in which the present invention is applied to the case where there are two data synchronization signal detection signals and the first data synchronization signal is detected.

FIG. 10 is a diagram illustrating an example in which the present invention is applied to the case where there are two data synchronization signal detection signals and a second data synchronization signal is detected.

FIG. 11 is a diagram illustrating an example in which the present invention is applied to the case where there are two data synchronization signal detection signals and the data synchronization signal cannot be detected.

FIG. 12 is a diagram illustrating a magnetic disk device according to the present invention.

FIG. 13 is a diagram illustrating a configuration of a reproducing system including a conventional data synchronization signal detecting means.

FIG. 14 is a diagram for explaining a conventional format format and timing of data sync signal detection and the like.

[Explanation of symbols]

10, 11, ... Format, 12, 13, 14, 154
... enable signal, 16,17,19 ... data sync signal detection output signal, 18,20 ... data sync signal erroneous detection pulse, 21,23 ... portion reflected in SYNC detection rate, 22,2
4 ... Portion not reflected in SYNC detection rate, 31, 103 ... PL
O_SYNC, 32, 104, 107 ... Data synchronization signal, 33, 105, 106, 108 ... Guard signal, 3
4, 101, 102 ... DATA section, 35 ... CRC section / E
CC section, 36 ... GAP section, 41, 81, 141 ... Equalizer, 42, 82, 142 ... Data discrimination means, 43, 8
3,150 ... Serial / parallel conversion means or code demodulation means, 4
4, 84, 143 ... Data sync signal detecting means, 45, 1
46, 147, 148 ... Delay device, 51, 91, 151 ...
Playback data input, 52, 92, 152 ... Equalizer output, 5
3, 93, 153 ... Data discrimination output, 54, 94 ... Data synchronization signal detection output, 55 ... Data synchronization signal detection delay output, 56, 95 ... Reproduction data output, 61 ... Code modulator,
62 ... Signal selecting means, 63 ... Control circuit, 64 ... P / S converter, 65 ... Recording correction circuit, 71 ... Recording data input, 7
2 ... Modulated recording data, 73 ... PLO_SYNC pattern, 74 ... SYNC_BYTE pattern, 75 ... Guard pattern, 76 ... Control signal, 77 ... Select output, 78 ... Serial data, 79 ... Recording data output, 144 ... Data delay device, 145 ... Data selector, 149 ... Control circuit,
155 ... First data sync signal detection output, 156 ... First
Data synchronization signal detection delay output, 157 ... First data synchronization signal non-detection output, 158 ... First data synchronization signal non-detection delay output, 159 ... Second data synchronization signal detection output, 160 ... Second data Sync signal detection delay output, 16
1 ... Second data sync signal non-detection output, 162,163
... control signal, 164 ... supplementary data, 165 ... data discrimination delay output, 166 ... data selection output, 167 ... reproduction data output, 201 ... magnetic disk device, 202 ... host device, 211 ... magnetic disk, 212 ... magnetic head, 21
3 ... R / W_AMP, 214 ... HDC microcomputer, 215
... Data buffer, 216 ... Servo processing circuit, 217 ...
Mechanical system driver, 218 ... VCM, 219 ... motor,
220 ... Signal processing means

   ─────────────────────────────────────────────────── ─── Continued front page    (54) [Title of Invention] Data synchronization detection method, data recording device using this method, information recording medium used in this method,                     A data synchronization signal detecting device, a signal processing device using the same, and an information recording / reproducing device including them                     apparatus

Claims (7)

[Claims] 1. Discrimination means for inputting input data including a data synchronization signal for data synchronization, a guard signal for preventing erroneous detection of the data synchronization signal following the data synchronization signal, and a data signal subsequent thereto for discriminating the data of the input data. A data synchronization signal detecting means for detecting data synchronization by the discrimination bit string outputted from the discrimination means, and a data synchronization signal detection output outputted from the data synchronization signal detecting means, and a time delay corresponding to the guard signal length. A data synchronization signal detecting device comprising: delaying means for causing the delaying means; and data outputting means for outputting a data signal of a discrimination bit string outputted from the discriminating means at the timing of a signal outputted from the delaying means. 2. A PLO_SYNC signal for clock synchronization, a data synchronization signal for data synchronization, a guard signal for preventing erroneous detection of the data synchronization signal, and a selection means for selecting a data signal as information to be recorded. Data recorder. 3. The data recording device according to claim 2, wherein the guard signal for preventing erroneous detection of the data synchronization signal is the same bit pattern sequence as the PLO_SYNC signal. 4. Discrimination means for inputting input data including a data synchronization signal for data synchronization, a guard signal for preventing erroneous detection of the data synchronization signal following the data synchronization signal, and a data signal subsequent thereto for discriminating the data of the input data. A data synchronization signal detecting means for detecting data synchronization by the discrimination bit string outputted from the discrimination means, and a data synchronization signal detection output outputted from the data synchronization signal detecting means, and a time delay corresponding to the guard signal length. And a data synchronization signal detecting device having a data output means for outputting a data signal of a discrimination bit string output from the discrimination means at the timing of a signal output from the delay means, and a PLO_SYNC for synchronizing clocks. Data synchronization signal and data synchronization signal Guard signal that prevents false detection of data synchronization signal Signal processing apparatus and a data recording apparatus and selecting means for selecting the data signal is information to be recorded and. 5. An information recording medium for recording information, a recording / reproducing means for recording or reproducing information on this information recording medium, and a signal processing means for performing signal processing of information to be recorded or information to be reproduced. A means for adding a data synchronization signal for data synchronization when recording information on the information recording medium and a guard signal for preventing erroneous detection of the data synchronization signal to the information to be recorded. Information recording / reproducing apparatus. 6. Input data including a data synchronization signal for data synchronization, a guard signal for preventing erroneous detection of the data synchronization signal subsequent thereto, and a data signal subsequent thereto are input to a discrimination means for performing data discrimination, and this discrimination is performed. By inputting the discrimination bit string output from the means to the data synchronization signal detection means for detecting data synchronization and outputting the data synchronization signal detection output, the delay means delays the data synchronization signal detection output for the guard signal length. A data synchronization detection method for outputting a discrimination bit string output from the discrimination means as a data signal by a delayed signal. 7. An information recording medium in which a data synchronization signal for synchronizing data and a guard signal for preventing erroneous detection of the data synchronization signal are added to a data signal which is recording information and recorded.