JP4340380B2 - Data playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data recording / reproducing apparatus, and more particularly to a data recording / reproducing apparatus capable of improving the data recording efficiency of a recording medium.
[0002]
[Prior art]
The prior art will be described taking a general magnetic disk device as an example of a data recording / reproducing device.
[0003]
The magnetic disk device includes a magnetic disk, a recording circuit that performs data recording operation on the magnetic disk, a reproducing circuit that performs data reproducing operation from the magnetic disk, and a control circuit that controls the recording / reproducing operation. The
[0004]
FIG. 13 shows the configuration of the magnetic disk.
[0005]
Concentric tracks t are formed on the magnetic disk 2. On the track t, a sector c delimited by a gap g for absorbing rotational fluctuation of the magnetic disk is provided. In addition, servo areas s are intermittently arranged on the circumference. When one sector c is divided by the servo area s, the sector c is called a split sector. A sector c that is not divided in the servo area s is called a non-split sector.
[0006]
FIG. 14 is an explanatory diagram of an index pulse signal IDX, a servo gate signal SG, and a sector pulse signal SP for controlling information arrangement on a track, recording timing, and reproduction timing.
[0007]
The index pulse signal IDX is a signal indicating the starting point of the track, and is generated once per rotation of the magnetic disk 2.
[0008]
The servo gate signal SG is a signal indicating a servo area, and is generated at regular intervals from the index pulse signal IDX.
[0009]
The sector pulse signal SP is a signal indicating the starting point of the sector and is generated based on the index pulse signal IDX.
[0010]
{When recording data}
During data recording, the operation is as follows.
[0011]
The control circuit activates the write gate signal WG for the sector to be recorded on the basis of the sector pulse signal SP. At the same time, a series of sector information on the data bus NRZ, that is, bit synchronization information PLO, symbol synchronization information SYNC, data DATA, error check code ECC for error detection and correction, and pad information for absorbing reproduction delay PAD is output. When a series of sector information is output, the write gate signal WG is made inactive.
[0012]
The recording circuit records a series of sector information output to the data bus NRZ on a track t of the magnetic disk 2 after a delay called a recording delay. The time corresponding to the recording delay is included in the series of sector information in advance, and the data length actually recorded on the track t is shorter than the series of sector information lengths.
[0013]
{During data playback}
When data is played back, it operates as follows.
[0014]
The control circuit activates the read gate signal RG for the sector to be reproduced with reference to the sector pulse signal SP.
[0015]
When the read gate signal RG becomes active, the reproduction circuit outputs the bit synchronization information PLO, and reproduces the symbol synchronization information SYNC, data DATA, error check code ECC, and pad information PAD following the bit synchronization information PLO on the magnetic disk. Output on the data bus NRZ.
[0016]
Here, the symbol synchronization information SYNC, data DATA, error check code ECC and pad information PAD output on the data bus NRZ are derived from the symbol synchronization information SYNC, data DATA, error check code ECC and pad area PAD on the magnetic disk. The timing is delayed by the time required for the reproduction process. This delay time is called reproduction delay time.
[0017]
The control circuit detects the symbol synchronization information SYNC on the data bus NRZ, thereby detecting the start of the data DATA, and processes the data DATA and the error check code ECC. Further, after detecting the symbol synchronization information SYNC, the read gate signal RG is made inactive after a time corresponding to the number of data transfer bytes.
[0018]
When the read gate signal RG becomes inactive, the reproduction circuit stops outputting data reproduced from the magnetic disk.
[0019]
[Problems to be solved by the invention]
In the above conventional magnetic disk apparatus, the reproduction delay is ensured to ensure that the information of the sector is read from the magnetic disk during the period from the activation of the read gate signal RG to the deactivation at the start of a certain sector. It was necessary to provide a pad area PAD longer than the time on the magnetic disk.
[0020]
The reproduction circuit generally employs a PRML (Partial Response Maximum Likelihood) signal processing system that can reproduce a low S / N signal. However, the PRML signal processing system tends to increase the reproduction delay time. For this reason, the pad area PAD also tends to increase.
[0021]
However, when the pad area PAD increases, there is a problem that the data storage area that can be effectively used decreases and the data recording efficiency decreases.
[0022]
Accordingly, an object of the present invention is to provide a data reproducing apparatus that can suppress an increase in pad area PAD and improve the data recording efficiency of a recording medium.
[0023]
Further, at the time of recording, it is necessary to provide a PAD corresponding to the recording delay time between the time when the write gate signal WG is activated and the time when it is deactivated at the recording start position of a certain sector.
[0024]
Accordingly, another object of the present invention is to provide a data recording / reproducing apparatus that can suppress an increase in pad area PAD and improve the data recording efficiency of a recording medium.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides synchronization information detection means for detecting synchronization information of a block to be reproduced from a medium in which a series of data strings to which synchronization information is added is recorded as a block, and outputting a synchronization information detection signal, Block end position calculating means for calculating the end position of the block on the recording medium with reference to the synchronization information detection signal, and reading data from the recording medium to the block end position calculated from the detected synchronization information and reproducing the data A data reproducing apparatus including a data reproducing circuit is provided.
[0026]
Alternatively, a bit synchronization information for performing bit synchronization, symbol synchronization information for performing symbol synchronization, data, correction information for correcting this data, and a data string having an additional area as a block unit, The read command signal for instructing to read the block to be reproduced on the recording medium on which the block is recorded is activated, the end position of the block on the recording medium is calculated based on the synchronization information detection signal, and the read command signal is input. A format control circuit to be activated, a synchronization information detection circuit that reads a block on the recording medium to detect symbol synchronization information and outputs a synchronization information detection signal while the read command signal is active, and a period in which the read command signal is active The block data read from the recording medium and the correction information are based on the synchronization information detection signal. A data reproduction circuit to be reproduced and outputted Te, and the data reproducing apparatus comprising a data processing circuit for processing the data and correction information output from the data reproduction circuit after the elapse of the reproduction delay time based on the synchronization information detection signal.
[0027]
Alternatively, a synchronization information detection circuit that detects synchronization information of a block to be reproduced and outputs a synchronization information detection signal from a recording medium in which a series of data strings to which synchronization information is added is recorded as a block, and a synchronization information detection signal as a reference. A code reproduction circuit for reproducing and outputting the code string, and a decoding circuit for decoding the code string output from the code reproduction circuit with reference to the synchronization information detection signal, and after the synchronization information detection signal is output, A data reproducing apparatus that processes a sequence by a decoding circuit.
[0028]
Alternatively, a data generation circuit for sending data, an encoding circuit for encoding the data, a data string generation circuit for generating a data string by adding synchronization information to the encoded data, and recording the data string A recording circuit for recording as a data string and a format control circuit for controlling the data string generating circuit and the recording circuit independently. The control circuit controls the recording circuit after the data string of the data string generating circuit is output. The data reproducing apparatus outputs a recording data string.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited thereby.
[0030]
-First embodiment-
FIG. 1 is a configuration diagram of a magnetic disk device according to a first embodiment of the present invention.
[0031]
The magnetic disk device 1 includes a magnetic disk 2, a recording / reproducing head 3 that converts magnetic information recorded on the magnetic disk 2 into an electrical signal, a servo control circuit 4 that controls the positioning of the recording / reproducing head 3, It includes an R / W amplifier 5 that interfaces recording / reproducing signals, a recording / reproducing processing circuit 6 that processes digital data, and a data control circuit 7 that controls recording / reproducing of data.
[0032]
The recording / reproducing processing circuit 6 includes an encoding circuit 10 and a data recording circuit 11 that are data recording paths, a waveform processing circuit 12 that is a data reproducing path, a data determination circuit 14, a data correction circuit 15, and a decoding circuit 16, and a servo control path. And a SYNC detection circuit 17 that outputs a synchronization information detection signal SBD to the data control circuit 7.
[0033]
The data control circuit 7 includes a microcomputer 20, a format control circuit 21 that generates various control signals based on the servo pulse signal SS and the synchronization information detection signal SBD, and a data bus NRZ under the control of the format control circuit 21. A data flow control circuit 22 that controls data, a buffer control circuit 23, a buffer 24, an ECC correction circuit 25, and an interface control circuit 26 that is a connection unit with an external processing device are provided.
[0034]
{Non-recording playback operation}
During the non-recording / reproducing operation, the servo control circuit 4 performs control using servo information in the servo area, and the recording / reproducing head 3 is positioned on an arbitrary track.
[0035]
The timing of the servo information is indicated by the servo gate signal SG among the format control signals of the format control circuit 21.
[0036]
When the servo gate signal SG becomes active, the servo demodulating circuit 13 uses the servo information obtained via the recording / reproducing head 3, the R / W amplifier 5 and the waveform processing circuit 12 to use the servo pulse signal SS indicating the servo area. Is output to the format control circuit 21. Further, the servo demodulation circuit 13 outputs the track position deviation amount of the recording / reproducing head 3 to the servo control circuit 4.
[0037]
The servo control circuit 4 feeds back the amount of positional deviation and causes the recording / reproducing head 3 to follow the track.
[0038]
{Recording action}
The recording operation is started by sending a write command that is a recording command of the external processing device.
[0039]
The external processing device sends data to be recorded to the interface control circuit 26 following the write command.
[0040]
The interface control circuit 26 receives a write command from the external processing device, and sends the write command and a logical address included in the write command to the microcomputer 20.
[0041]
The microcomputer 20 converts the logical address into a physical address and gives a seek command for the recording / reproducing head 3 to the servo control circuit 4.
[0042]
The servo control circuit 4 moves the recording / reproducing head 3 to a track corresponding to the physical address. In parallel with this, the data to be recorded is temporarily stored in the buffer 24 via the interface control circuit 26 and the buffer control circuit 23.
[0043]
The format control circuit 21 generates a servo gate signal SG, an index pulse signal IDX, and a sector pulse signal SP based on the servo pulse signal SS.
[0044]
When the sector number corresponding to the sector pulse signal SP matches the recording sector number given by the physical address, the format control circuit 21 activates the write gate signal WG and controls the data flow control circuit 22 to control a series of sectors. Information, that is, bit synchronization information PLO, symbol synchronization information SYNC, data DATA temporarily stored in the buffer 24, error check code ECC generated by the ECC correction circuit 25, and pad information PAD are sequentially output to the data bus NRZ. To do.
[0045]
Although several bytes of POST information are provided between the error check code ECC and the pad information PAD to ensure data processing of the error check code ECC, they are ignored for the sake of explanation because they are not directly related to the present invention. To do.
[0046]
The output sector information is encoded into a specific code by the encoding circuit 10 and passed to the data recording circuit 11.
[0047]
The data recording circuit 11 adds a data correction code to the encoded parallel data string, and outputs it to the R / W amplifier 5 as a serial data string.
[0048]
The R / W amplifier 5 records a serial data string as sector information on the corresponding track from the recording / reproducing head 3.
[0049]
{Playback operation}
The reproduction operation is started by sending a read command that is a reproduction instruction of the external processing device. The timing of the control signal will be described later.
[0050]
The interface control circuit 26 receives the read command and outputs a logical address included in the read command to the microcomputer 20.
[0051]
The microcomputer 20 converts a logical address into a physical address and gives a seek command to the servo control circuit 4 so as to move the recording / reproducing head 3 onto a track to be reproduced.
[0052]
The format control circuit 21 generates a sector pulse signal SP based on the servo pulse signal SS processed by the recording / reproducing head 3, the R / W amplifier 5, the waveform processing circuit 12, and the servo demodulation circuit 13. Here, the sector pulse signal SP is advanced in phase with respect to the sector pulse signal SP at the time of recording.
[0053]
When the sector number corresponding to the sector pulse signal SP matches the reproduction sector number given by the physical address, the format control circuit 21 activates the read gate signal RG.
[0054]
The sector information is reproduced as serial digital data by the R / W amplifier 5, the waveform processing circuit 12, and the data determination circuit 14.
[0055]
The SYNC detection circuit 17 detects the symbol synchronization information SYNC in the sector information and activates the synchronization information detection signal SBD.
[0056]
The data correction circuit 15 corrects data using a data correction code (CRC, ECC, etc.) after the synchronization information detection signal SBD becomes active.
[0057]
The decoding circuit 16 outputs the serial data string on the data bus NRZ as parallel data.
[0058]
The format control circuit 21 counts the number of data transfer bytes based on the synchronization information detection signal SBD, and inactivates the read gate signal RG when reaching the end position of the sector. That is, the timing at which the read gate signal RG becomes inactive is the timing at which the reproduction delay time does not enter. Therefore, the minimum pad area PAD is sufficient regardless of the reproduction delay time.
[0059]
The arrival of data at the data flow control circuit 22 is delayed from the synchronization information detection signal SBD by the processing time in the data correction circuit 15 and the decoding circuit 16, that is, the reproduction delay time. Therefore, the data flow control circuit 22 counts the number of bytes corresponding to the reproduction delay time after the synchronization information detection signal SBD becomes active, and then stores the data in the buffer 24 via the buffer control circuit 23.
[0060]
The ECC correction circuit 25 performs error verification of the data stored in the buffer 24 based on the error check code ECC, and corrects if there is an error.
[0061]
The data stored in the buffer 24 is sent to the external processing device through the buffer control circuit 23 and the interface control circuit 26 under the control of the microcomputer 20 when the data correction is completed or when there is no error in the data. The
[0062]
FIG. 2 is an explanatory diagram of the internal configuration of the format control circuit 21 and the data flow control circuit 22.
[0063]
The format control circuit 21 includes a servo control signal generation circuit 30, an index pulse generation circuit 31, a sector pulse generation circuit 32, and a sequencer 33.
[0064]
The servo control signal generation circuit 30 generates a servo gate signal SG with reference to the servo pulse signal SS.
[0065]
The index pulse generation circuit 31 determines the servo pulse signal SS during the period when the servo gate signal SG is active, and generates the index pulse signal IDX.
[0066]
The sector pulse generation circuit 32 generates a sector pulse signal SP having different phases depending on the reproducing operation and the recording operation with reference to the index pulse signal IDX.
[0067]
The sequencer 33 controls the sector format, and includes a write gate signal WG indicating the sector recording period, a read gate signal RG indicating the sector reproduction period, a selection signal SEL for controlling the data flow control circuit 22, and A load signal LD is generated.
[0068]
The data flow control circuit 22 includes a fixed data generation circuit 34, a FIFO 38, a selection circuit 35, a reproduction delay counter 36, and a data transfer counter 37.
[0069]
The fixed data generation circuit 34 is a circuit that outputs a code sequence of bit synchronization information PLO, symbol synchronization information SYNC, and pad information PAD, and is connected to the first end of the selection circuit 35.
[0070]
The FIFO 38 is a circuit that outputs the data DATA and the error check code ECC code string from the buffer control circuit 23, and is connected to the second end of the selection circuit 35.
[0071]
The selection circuit 35 selects the fixed data generation circuit 34 when the selection signal SEL from the sequencer 33 is “1”, selects the FIFO 38 when the selection signal SEL is “0”, and outputs it to the data bus NRZ. .
[0072]
FIG. 3 shows the timing of the servo gate signal SG, the index pulse signal IDX, the sector pulse signal SP, and the data arrangement on the magnetic disk 2.
[0073]
FIG. 3 shows an example in which three servo areas and eight sectors are arranged during one rotation of the magnetic disk 2.
[0074]
The servo gate signal SG becomes active in each servo area.
[0075]
The index pulse signal IDX becomes active once every three servo periods.
[0076]
The sector pulse signal SP becomes active at the start position of the sector.
[0077]
A slight gap region GAP is formed between the sectors.
[0078]
One sector includes bit synchronization information PLO, symbol synchronization information SYNC, data DATA, error check code ECC, and pad area PAD.
[0079]
{During recording}
In the recording operation, as shown in FIG. 3A, the sector pulse signal SP becomes active at the sector start position, and the write gate signal WG records the data of the sector. It becomes active in sync with.
[0080]
A series of sector information of the bit synchronization information PLO, symbol synchronization information SYNC, data DATA, error check code ECC and pad information PAD to be recorded is based on the selection signal SEL output from the sequencer 33, the fixed data generation circuit 34, the FIFO 38 and the selection. Generated by circuit 35. That is, the sequencer 33 first sets the selection signal SEL to “1”, selects the output of the fixed data generation circuit 34, and outputs the bit synchronization information PLO and the symbol synchronization information SYNC to the data bus NRZ. Subsequently, the sequencer 33 sets the selection signal SEL to “0”, selects the output of the FIFO 38, and outputs the data DATA and the error check code ECC to the data bus NRZ. Next, the sequencer 33 sets the selection signal SEL to “1”, selects the output of the fixed data generation circuit 34, and outputs the pad information PAD to the data bus NRZ. Finally, the sequencer 33 inactivates the write gate signal WG and ends the recording operation.
[0081]
{During playback operation}
At the time of the reproducing operation, as shown in FIG. 3B, the sector pulse signal SP is a signal whose phase is advanced with respect to the data recording operation. This is because control is performed to ensure that the read gate signal RG is activated at the head position of the sector against fluctuations in the sector start position due to rotational fluctuations. In other words, the sector pulse generation circuit 32 advances the phase of the sector pulse signal SP when the read / write signal indicates a reproduction operation as compared with when the read / write signal indicates a recording operation.
[0082]
The sequencer 33 activates the read gate signal RG at the sector start position with reference to the sector pulse signal SP. Then, after a predetermined number of bytes have elapsed since the detection of the symbol synchronization information SYNC, it is inactive.
[0083]
When the sequencer 33 detects the synchronization information detection signal SBD from the SYNC detection circuit 17, the sequencer 33 starts the count operation of the reproduction delay counter 36 by the load signal LD. The reproduction delay counter 36 outputs the ST signal when counting the number of bytes corresponding to the reproduction delay time of the data correction circuit 15 and the decoding circuit 16. After being triggered by the ST signal, the data transfer counter 37 counts a predetermined number of bytes of data. During this count, data DATA and error check code ECC on the data bus NRZ are sent to the buffer control circuit 23 via the FIFO 38.
[0084]
The prescribed number of bytes is basically the number of bytes corresponding to the data DATA and error check code ECC, but in the case of a non-split sector that is not divided in the servo area and in the case of a split sector that is divided in the servo area. It is different.
[0085]
FIG. 4 shows the output timing of the control signal in the reproduction operation of a single data sector.
[0086]
(1) in FIG. 4 is the output timing of the control signal for the non-split sector (sector # 2).
[0087]
The read gate signal RG is active from the sector start position on the magnetic disk to the middle of the pad area PAD.
[0088]
The synchronization information detection signal SBD becomes active when the symbol synchronization information SYNC is detected by the SYNC detection circuit 17, and becomes inactive when the read gate signal RG becomes inactive.
[0089]
The data bus NRZ of the decoding circuit 16 is in a high impedance state (Hi-Z) at the start of the reproduction operation, and after the reproduction delay time has elapsed since the synchronization information detection signal SBD was output, the data DATA, the error check code ECC, and the pad Data in the area PAD is output.
[0090]
The synchronization information detection signal SBD and the data bus NRZ data having the above timing relationship are controlled by the format control circuit 21 and the data flow control circuit 22 as described above.
[0091]
(2) in FIG. 4 is the output timing of the control signal for the split sector (sector # 3).
[0092]
The read gate signal RG for the first half sector (referred to as sector # 3 (a)) preceding the servo area becomes active from the start position of the bit synchronization information PLO of sector # 3 (a) to the middle of the pad area PAD. The read gate signal RG for the latter half sector (referred to as sector # 3 (b)) after the servo area is active from the start position of the bit synchronization information PLO of sector # 3 (b) to the middle of the pad area PAD. .
[0093]
The synchronization information detection signal SBD becomes active when the symbol synchronization information SYNC of the sector # 3 (a) is detected by the SYNC detection circuit 17, and becomes inactive when the read gate signal RG becomes inactive. Also, it becomes active when the symbol synchronization information SYNC of sector # 3 (b) is detected by the SYNC detection circuit 17, and becomes inactive when the read gate signal RG becomes inactive.
[0094]
The data bus NRZ outputs data DATA (1) and pad information PAD after the reproduction delay time has elapsed from the synchronization information detection signal SBD detected in the sector # 3 (a), and then enters a high impedance state. Further, after the reproduction delay time has elapsed from the synchronization information detection signal SBD detected in the sector # 3 (b), the data DATA (2), the error check code ECC, and the pad information PAD are output, and then the high impedance state is entered. . Here, the reproduction delay time is the same time in sector # 3 (a) and sector # 3 (b), and since the servo period is not zero, sector # 3 (a) and sector # 3 (b ) Data bus NRZ does not collide.
[0095]
The synchronization information detection signal SBD and the data bus NRZ data having the above timing relationship are controlled by the format control circuit 21 and the data flow control circuit 22 as described above.
[0096]
FIG. 5 shows the output timing of the control signal in the reproduction operation of continuous data sectors.
[0097]
(1) in FIG. 5 is the output timing of the control signal for continuous reproduction of the non-split sectors (sectors # 4 and # 5).
[0098]
The read gate signal RG, the synchronization information detection signal SBD, and the data bus NRZ are generated at the same timing as in the reproduction operation of a single sector.
[0099]
The synchronization information detection signal SBD becomes inactive at the same time as the read gate signal RG for the sector # 4 becomes inactive. Therefore, it becomes possible for the format control circuit 21 to detect the start position of the symbol synchronization information SYNC of the next sector # 5 by using the synchronization information detection signal SBD.
[0100]
In addition, the data bus NRZ during the period of sector # 4 and sector # 5 does not overlap because the bit synchronization information PLO and symbol synchronization information SYNC of gap area GAP and sector # 5 are not zero.
[0101]
Therefore, the data of each sector can be stored in the corresponding buffer 24 by the format control circuit 21 and the data flow control circuit 22.
[0102]
(2) in FIG. 5 is an output timing of the control signal for continuous reproduction of the split sector (sector # 3) and the non-split sector (sector # 4).
[0103]
The read gate signal RG, the synchronization information detection signal SBD, and the data bus NRZ are generated at a timing that combines the timing at the time of reproducing operation of a single split sector and the timing at the time of reproducing operation of a single non-split sector.
[0104]
The synchronization information detection signal SBD is the same as (1) in FIG. Therefore, the format control circuit 21 can detect the start position of the corresponding symbol synchronization information SYNC by the synchronization information detection signal SBD.
[0105]
Similarly, the data bus NRZ during each sector period does not overlap.
[0106]
Therefore, the data of each sector can be stored in the corresponding buffer 24.
[0107]
Next, a case where the symbol synchronization information SYNC cannot be correctly detected due to a determination error of the data determination circuit 14 or the like will be described with reference to FIG.
[0108]
FIG. 6 (1) shows a case where the symbol synchronization information SYNC of sector # 5 cannot be correctly detected during the continuous reproduction operation of non-split sectors (sectors # 4 and # 5).
[0109]
The reproduction operation for sector # 4 is the same as (1) in FIG.
[0110]
The read gate signal RG of sector # 5 becomes active at the start position of the bit synchronization information PLO. However, since the synchronization information detection signal SBD does not become active within a predetermined period, the sequencer 33 reads the read gate signal RG. Inactive. The predetermined period is a period slightly longer than the period from the sector start position to the symbol synchronization information SYNC. The data correction circuit 15 and the decoding circuit 16 do not output the data DATA (DATA # 5) of the sector # 5 to the data bus NRZ because the synchronization information detection signal SBD is not active. Accordingly, the data DATA (DATA # 4) of the sector # 4 is normally stored in the buffer 24, but the data DATA (DATA # 5) of the sector # 5 is not stored in the buffer 24. For this reason, the reproduction operation is performed again on sector # 5 by processing such as retry.
[0111]
(2) in FIG. 6 shows the sector (sector # 3 (2)) after the servo area of the split sector # 3 during the continuous reproduction operation of the split sector (sector # 3) and the non-split sector (sector # 4). This shows a case where the symbol synchronization information SYNC could not be detected correctly.
[0112]
The reproduction operation for the sector (sector # 3 (1)) before the servo area of split sector # 3 is the same as (2) in FIG.
[0113]
The read gate signal RG of the sector (sector # 3 (2)) after the servo area of the split sector # 3 becomes active at the start position of the bit synchronization information PLO, but the synchronization information is detected within a predetermined period. Since the signal SBD does not become active, the sequencer 33 makes the read gate signal RG inactive. The data correction circuit 15 and the decoding circuit 16 do not output the data DATA (DATA # 3 (2)) of the sector # 3 (2) to the data bus NRZ because the synchronization information detection signal SBD is not active.
[0114]
The reproduction operation for the non-split sector # 4 is the same as (2) in FIG.
[0115]
Therefore, the reproduction operation is performed again for the data in split sector # 3 by a process such as retry.
[0116]
FIG. 7 shows a control procedure of the sequencer 33 and the data flow control circuit 22.
[0117]
This control procedure includes a normal process (1) for processing a non-split sector and a split sector, and an exception process (2) when the symbol synchronization information SYNC is not detected within a specified time.
[0118]
The normal process shown in (1) of FIG. 7 is processed in steps 1 to 9.
[0119]
The sequencer 33 activates the read gate signal RG at step 1. In step 2, it is confirmed whether or not the synchronization information detection signal SBD is detected within a certain period. If it is detected, the control is shifted to step 3. If the synchronization information detection signal SBD does not become active within a certain period, the process proceeds to exception processing. In step 3, in order to ensure the active state of the read gate signal RG between the data DATA, the error check code ECC, and the pad area PAD, the process waits until the specified number of bytes are counted. Here, the prescribed number of bytes is the total number of bytes of data DATA, error check code ECC and pad area PAD in the case of a non-split sector, and data DATA and pad area PAD up to the servo area in the case of a split sector. This is the total number of bytes (in the example of (2) in FIG. 4, the total number of bytes of DATA (1) and the subsequent pad area PAD).
[0120]
In step 4, the read gate signal RG is made inactive.
[0121]
For the non-split sector, since the prescribed number of bytes of data has been processed, the operation ends in step 4.
[0122]
For the split sector, the passage of the servo period is awaited in step 5, and the split sector after the servo area is processed. In step 6, the read gate signal RG is made active again, and in step 7, the synchronization information detection signal SBD is detected. If the synchronization information detection signal SBD is not detected within a certain period, the process proceeds to exception processing. In step 8, after waiting for a prescribed number of bytes (the total number of bytes of DATA (2), ECC, and pad area PAD in the example of (2) in FIG. 4), the read gate signal RG is made inactive in step 9.
[0123]
Basically, except for step 3 and step 8, the data flow control circuit 22 continues the data transfer if data transfer is in progress. In step 3 and step 8, the load signal LD given from the sequencer 33 waits for the number of reproduction delay bytes and performs data transfer of the prescribed number of bytes.
[0124]
The exception process shown in (2) of FIG. 7 is processed by step1 and step2.
[0125]
The sequencer 33 inactivates the read gate signal RG at step 1, notifies the microcomputer 20 of the occurrence of a data error at step 2, and performs a retry process or the like.
[0126]
The data flow control circuit 22 performs a data transfer continuation process if data transfer is in progress.
[0127]
According to the magnetic disk device 1 of the first embodiment, the synchronization information detection signal is not output from the data correction circuit 15 and the decoding circuit 16 whose outputs are delayed by the reproduction delay time, but the SYNC having substantially no delay. A synchronization information detection signal SBD is output from the detection circuit 17. Therefore, the format control circuit 21 can accurately inactivate the read gate signal RG at the end position of the sector on the magnetic disk with reference to the synchronization information detection signal BSD, regardless of the reproduction delay time. Therefore, in order to guarantee that the recording / reproducing processing circuit 6 reads the information of the sector from the magnetic disk, it is not necessary to provide a pad area PAD longer than the reproduction delay time at the end of the sector. Therefore, the pad area PAD is minimized, the data storage area that can be used effectively can be increased, and the data recording efficiency can be improved. Since data is delayed by the reproduction delay time and output to the data bus NRZ, the data flow control circuit 22 processes the data delayed by the reproduction delay time.
[0128]
In other words, in the present invention, the format control and the data control are separated and controlled. As a result, the pad area PAD can be minimized, the effective data recording area can be expanded, and the data recording efficiency can be improved.
[0129]
Specifically, what conventionally required a pad area PAD of about 8 bytes can be suppressed to about 2 bytes. Further, when the reproduction delay extends to one sector (about 512 bytes), the pad area PAD of 512 bytes or more has been conventionally required, but even in this case, it can be suppressed to about 2 bytes (the data recording efficiency is 512 bytes). In the above pad area PAD, it is reduced to about 40%, but in the pad area PAD of about 2 bytes, about 75% can be secured).
[0130]
-Second Embodiment-
In the second embodiment, among the signals connecting the recording / reproducing processing circuit 6 and the data control circuit 7 shown in FIG. 1, the synchronization information detection signal SBD is reduced.
[0131]
FIG. 8 is a main part configuration diagram of a magnetic disk apparatus according to the second embodiment of the present invention. In order to distinguish from the recording / reproduction processing circuit 6 and the data control circuit 7 shown in FIG. 1, in FIG. 8, a recording / reproduction processing circuit 6 ′ and a data control circuit 7 ′ are used.
[0132]
The recording / reproducing processing circuit 6 ′ includes a coding circuit 10 and a data recording circuit 11 that are data recording paths, a waveform processing circuit 12, a data determination circuit 14, a data correction circuit 15, and a decoding circuit 16 that are data reproducing paths, and servo control. The servo demodulation circuit 13 serving as a path, the SYNC detection circuit 17 that transmits SYNC information to the data control circuit 7 ′ via the data bus NRZ, and the SYNC code generation circuit 40 are configured.
[0133]
The data control circuit 7 ′ is a format control that performs format control and data processing from information on the interface control circuit 26, microcomputer 20, buffer 24, buffer control circuit 23, ECC correction circuit 25, and data bus NRZ (not shown). A circuit 41 and a data flow control circuit 42 are provided.
[0134]
FIG. 9 is an explanatory diagram of data exchange on the data bus NRZ between the recording / reproduction processing circuit 6 ′ and the data control circuit 7 ′ during the reproduction operation. For convenience of explanation, it is assumed that the sector reproduction operation before the read gate signal RG becomes active is completed.
[0135]
FIG. 9 (1) shows the continuous reproduction operation of the non-split sector.
[0136]
When the read gate signal RG becomes active at the start position of the sector # 4, the waveform processing circuit 12 and the data determination circuit 14 start the data determination operation for the sector.
[0137]
When detecting the symbol synchronization information SYNC, the SYNC detection circuit 17 activates the synchronization information detection signal SBD. Since there is no data transfer on the data bus NRZ, the SYNC code generation circuit 40 outputs special symbol synchronization information SYNC onto the data bus NRZ when the synchronization information detection signal SBD becomes active.
[0138]
When the synchronization information detection signal SBD becomes active, the data correction circuit 15 and the decoding circuit 16 start data correction and decoding, and output data (DATA # 4) on the data bus NRZ after the reproduction delay time has elapsed. .
[0139]
The data bus NRZ is high impedance (Hi-Z) from the special symbol synchronization information SYNC to the start of data (DATA # 4).
[0140]
When the format control circuit 41 detects the special symbol synchronization information SYNC, it activates the load signal LD.
[0141]
When the load signal LD becomes active, the data flow control circuit 42 transfers the data (DATA # 4) on the data bus NRZ after the reproduction delay time has elapsed to the buffer control circuit 23.
[0142]
The read gate signal RG corresponding to the sector # 4 becomes inactive at the final position of the sector # 4, but the data (DATA # 4), the error check code ECC and the data of the pad information PAD are already in the data correction circuit. 15 and the internal storage circuit of the decoding circuit 16, and subsequently output from the data correction circuit 15 and the decoding circuit 16 to the data bus NRZ.
[0143]
When the read gate signal RG corresponding to the sector # 5 becomes active, the data correction circuit 15 and the decoding circuit 16 suspend the output to the data bus NRZ.
[0144]
For this reason, the data bus NRZ becomes high impedance (Hi-Z).
[0145]
When the SYNC detection circuit 17 detects the symbol synchronization information SYNC of sector # 5, the synchronization information detection signal SBD becomes active, and the SYNC code generation circuit 40 outputs special symbol synchronization information SYNC to the data bus NRZ.
[0146]
Following this, the data correction circuit 15 and the decoding circuit 16 resume the output of the data (DATA # 4) stored in the internal storage circuit, the subsequent error check code ECC, and pad information PAD to the data bus NRZ. .
[0147]
At the same time, the data correction circuit 15 and the decoding circuit 16 perform the correction and decoding processing of the data of sector # 5 using the internal storage circuit. However, since the reproduction delay time is not reached, the data correction circuit 15 and the decoding circuit 16 are not output to the data bus NRZ. When the output of the pad information PAD of sector # 4 is completed, the data bus NRZ becomes high impedance (Hi-Z).
[0148]
Thereafter, when the reproduction delay time elapses, the data correction circuit 15 and the decoding circuit 16 output the data of sector # 5 (DATA # 5), the error check code ECC and the pad information PAD data that follow the data bus NRZ.
[0149]
FIG. 9 (2) shows the continuous reproduction operation of the split sector and the non-split sector.
[0150]
As in (1) of FIG. 9, when the read gate signal RG becomes active at the start position of the sector # 3 and the symbol synchronization information SYNC is detected, special symbol synchronization information SYNC is output on the data bus NRZ. The After the reproduction delay time elapses, data (DATA # 3 (1)) before the servo area is output to the data bus NRZ.
[0151]
When the read gate signal RG becomes active again after the servo area has passed and the data after the servo area (DATA # 3 (2)) starts, the output of the data before the servo area (DATA # 3 (1)) Temporarily interrupted, the data bus NRZ becomes high impedance (Hi-Z).
[0152]
When the symbol synchronization information SYNC of data (DATA # 3 (2)) after the servo area is detected, special symbol synchronization information SYNC is output to the data bus NRZ.
[0153]
Following this, the output of data (DATA # 3 (1)) before the servo area is resumed.
[0154]
Thereafter, when the reproduction delay time elapses, data (DATA # 3 (2)) after the servo area is output from the data correction circuit 15 and the decoding circuit 16 onto the data bus NRZ. Since the corresponding read gate signal RG becomes active first, the output is temporarily suspended, and the data bus NRZ becomes high impedance (Hi-Z).
[0155]
When the symbol synchronization information SYNC of sector # 4 is detected, special symbol synchronization information SYNC is output to the data bus NRZ.
[0156]
Following this, the output of data (DATA # 3 (2)) after the servo area is resumed.
[0157]
Thereafter, when the reproduction delay time elapses, the data (DATA # 4) of the sector # 4 is output from the data correction circuit 15 and the decoding circuit 16 onto the data bus NRZ.
[0158]
Next, a control method when the symbol synchronization information SYNC is not detected will be described.
[0159]
FIG. 10 (1) shows a case where the symbol synchronization information SYNC of sector # 5 is not detected in the continuous reproduction operation of the non-split sector.
[0160]
The special symbol synchronization information SYNC of sector # 4 is output to the data bus NRZ, and a part of the data (DATA # 4) is output after the reproduction delay time has elapsed. When the read gate signal RG of sector # 5 becomes active, the output of data (DATA # 4) is suspended. Thereafter, since the symbol synchronization information SYNC of the sector # 5 is not detected, the special symbol synchronization information SYNC of the sector # 5 is not output. Therefore, the output of data (DATA # 4) is not resumed. However, since the synchronization information detection signal SBD does not become active within a predetermined period, the read gate signal RG of sector # 5 becomes inactive. Then, the output of data (DATA # 4) is resumed. Thereby, the output of the data of sector # 4 is completed.
[0161]
(2) of FIG. 10 shows a case where the symbol synchronization information SYNC after the servo area of the split sector # 3 is not detected in the continuous reproduction operation of the split sector and the non-split sector.
[0162]
When data (DATA # 3 (1)) before the servo area of split sector # 3 is output to the data bus NRZ, data DATA # 3 (2) after the servo area of split sector # 3 Since the read gate signal RG becomes active, the output is temporarily interrupted. Since the symbol synchronization information SYNC of the data DATA # 3 (2) after the servo area of the split sector # 3 has not been detected, if the read gate signal RG becomes inactive, the data before the servo area of the split sector # 3 ( The output of DATA # 3 (1)) is resumed. However, since the symbol synchronization information SYNC is not detected, the data DATA # 3 (2) after the servo area of the split sector # 3 is not corrected and decoded, and no data is output on the data bus NRZ. In this case, since data in sector # 3 is partially lost, data recovery processing such as retry is performed.
[0163]
FIG. 11 is an explanatory diagram of the internal configuration of the format control circuit 41 and the data flow control circuit 42.
[0164]
Compared to FIG. 2, the sequencer 50 is provided instead of the sequencer 33 of FIG. 2, and the data bus NRZ is input to the sequencer 50 instead of the synchronization information detection signal SBD being input to the sequencer 33 in FIG. The difference is that the hold signal HD is output from the sequencer 50 to the data transfer counter 51.
[0165]
The sequencer 50 during the recording operation performs exactly the same operation as the sequencer 33 in FIG.
[0166]
During the reproduction operation, the sequencer 50 activates the read gate signal RG and activates the hold signal HD that temporarily holds the count operation of the data transfer counter 51. Further, when the sequencer 50 detects special symbol synchronization information SYNC on the data bus NRZ, the sequencer 50 activates the load signal LD and deactivates the hold signal HD.
[0167]
The reproduction delay counter 36 activates the ST signal with a delay of the number of bytes corresponding to the reproduction delay with reference to the load signal LD.
[0168]
The data transfer counter 51 counts the number of data transferred to the buffer control circuit 23. If the hold signal HD is active, the data transfer is temporarily interrupted when the read gate signal RG is active. Then, when the hold signal HD becomes inactive, the data transfer is resumed.
[0169]
FIG. 12 shows a control procedure of the sequencer 50 and the data flow control circuit 42.
[0170]
This control procedure includes a normal process (1) for processing a non-split sector and a split sector, and an exception process (2) when the symbol synchronization information SYNC is not detected within a specified time.
[0171]
The normal process shown in (1) of FIG. 12 is processed in steps 1 to 9.
[0172]
The sequencer 50 activates the read gate signal RG at step 1, shifts control to step 3 if special symbol synchronization information SYNC is detected on the data bus NRZ within a predetermined period in step 2, and shifts to exception processing if not detected. To do. In step 3, wait until the specified number of bytes is counted. In step 4, the read gate signal RG is made inactive. For the non-split sector, the data processing for the specified number of bytes has been completed, so the processing ends at step 4. For the split sector, the passage of the servo area is awaited at step 5, and the read gate signal RG is made active again at step 6. In step 7, if special symbol synchronization information SYNC is detected within a certain period, control is transferred to step 8, and if not detected, exception processing is performed. In step 8, the specified number of bytes is waited. In step 9, the read gate signal RG is made inactive.
[0173]
In step 1 where the read gate signal RG becomes active, the data flow control circuit 42 temporarily stops data transfer if data transfer is in progress. In step 2, the data transfer continues to be suspended. When the special symbol synchronization information SYNC is detected and the process proceeds to step 3, the data transfer is resumed if it is paused, and is given from the sequencer 50 if the data transfer is not paused. Waiting for the number of reproduction delay bytes by the load signal LD, data transfer of a prescribed number of bytes is performed. Steps 4 and 5 continue if data is being transferred. Steps 6-9 are the same as steps 1-5.
[0174]
The exception process shown in (2) of FIG. 12 is processed by step1 and step2.
[0175]
The sequencer 50 inactivates the read gate signal RG at step 1, notifies the microcomputer 20 of the occurrence of a data error at step 2, and performs a retry process or the like.
[0176]
The data flow control circuit 42 resumes if the data transfer is temporarily stopped in step 1. In step 2, the data transfer is stopped.
[0177]
According to the second embodiment, the SYNC information is notified from the recording / reproduction processing circuit 6 ′ to the data control circuit 7 using the special symbol synchronization information SYNC on the data bus NRZ instead of the synchronization information detection signal SBD. Is possible. Therefore, it is possible to reduce the number of pins and the wiring area when the LSI is realized.
[0178]
-Third embodiment-
In the third embodiment, a control signal indicating a data output period is newly provided to simplify the control. FIG. 15 is a block diagram of the magnetic recording / reproducing apparatus of the third embodiment for simplifying the control. Compared with FIG. 1, the LD signal for the format control circuit 21 to control the data flow control circuit 22 is changed to a newly provided VALID signal. Here, the VALID signal is a bidirectional signal indicating that data on the NRZ has been determined, and is connected to the decoding circuit 16, the encoding circuit 10, and the data flow control circuit 22. The VALID signal indicates the output period of NRZ data, although it differs depending on the recording operation and the reproducing operation. The bidirectional switching operation of the VALID signal is performed by the data flow control circuit 22 during the recording operation and by the decoding circuit 16 during the reproduction operation.
[0179]
<Recording action>
At the time of the recording operation, the data flow control circuit 22 is newly provided with a write valid generation circuit 60 for generating a valid signal at the time of the recording operation as shown in one configuration example of FIG. The fixed data generation circuit 34 and the selection circuit 35 are included in the encoding circuit 10. After the data string transmitted from the buffer control circuit is temporarily stored in the FIFO 38, when the VALID signal output from the write valid generation circuit 60 becomes active, the output data from the FIFO 38 is output to the encoding circuit 10 as NRZ data. The encoding circuit 10 has the same function as the fixed data generation circuit 34, and records data such as PLO and SYNC together with the converted NRZ data.
[0180]
These operation timings are shown in FIG. The VALID signal is active only when the servo area does not divide the sector area and when the servo area divides the sector area and the data on the NRZ data is fixed. It becomes. When the WG signal generated after the recording delay rises, the PLO signal is outputted from the data recording circuit 11 when the SBD signal rises. When the NRZ data during the period when the VALID signal is active is processed, the SBD signal falls and the POST signal is recorded. Thereafter, the WG signal falls, completing a series of recording operations.
[0181]
<Playback operation>
During the reproduction operation, the decoding circuit 16 activates the VALID signal simultaneously with the transmission of the NRZ data. The VALID signal and NRZ data are connected to the FIFO 38 of the data flow control circuit 22 as shown in FIG. When the VALID signal is active, the FIFO 38 takes in the NRZ data, and then sends the data to the buffer control circuit.
[0182]
As shown in FIG. 18, the detailed timing of the VALID signal is generated in accordance with the timing of data output to the NRZ data. At this time, the rising edge of the SBD signal is output after detecting the SYNC area on the recording medium, but since the NRZ data and the VALID signal are output after the reproduction delay time after SYNC detection, the SBD signal is output from the NRZ data. , Asserted early with respect to the VALID signal. The format control circuit 21 generates a falling edge of the RG signal in the POST area on the recording medium from the asserted position of the SBD signal. The SBD signal is negated corresponding to the falling edge of the RG signal. The recording / reproducing processing circuit 6 detects the period from the SBD assert position to the falling edge of the RG signal and recognizes it as the number of data to be transferred. Based on the recognized number of data transfers, the recording / reproducing circuit 6 outputs the NRZ data to the data flow control circuit 22 after a reproduction delay.
[0183]
According to the above embodiment, by configuring the magnetic recording / reproducing apparatus based on the control signal (VALID signal) indicating the data output period, the control signal increases, but the control circuit can be simplified.
[0184]
In the recording operation example of this embodiment, since the case where the recording delay is large is shown, the output timing of the NRZ data is earlier than the assertion timing of the WG signal by the recording delay. However, the recording delay is a conversion delay of the encoding circuit 10 or the data recording circuit 11, and varies greatly depending on the configuration of the encoding circuit. Therefore, the recording delay may be small as shown in the conventional example. In this case, the output timing of the WG signal and the NRZ data as shown in the conventional example may be the same, that is, the VALID signal and the WG signal can be shared.
[0185]
Although not shown in the present embodiment, in order to delay the NRZ data, a memory for temporarily storing recording data may be required in the encoding circuit 10 or the recording / reproducing processing circuit 6 in some cases.
[0186]
-Other embodiments-
The structural example of the magnetic recording / reproducing apparatus of 4th Embodiment is shown. As shown in FIG. 19, the encoding circuit 10 and the decoding circuit 16 are arranged between the data flow control circuit 22 and the buffer control circuit 23, and the data flow control circuit 22 records and reproduces the encoded data. It is one block diagram of the magnetic recording / reproducing apparatus which enabled it to process.
[0187]
<Recording action>
During the recording operation, the encoding circuit 10 encodes the data string transmitted from the buffer control circuit 23, and transmits the encoded data string to the data flow control circuit 22 unlike the above configuration example. As shown in FIG. 20, the flow control circuit 22 includes a fixed data generation circuit 34, a selection circuit 35, a write valid generation circuit 60, and a FIFO 38. The FIFO 38 stores the data output from the fixed data generation circuit 34 and the data transmitted from the encoding circuit 10 within the range indicated by the sequencer 33, and NRZ based on the valid signal generated by the write valid generation circuit 60. The data is output to the data recording circuit 11.
[0188]
The timing of the VALID signal and NRZ data is shown in FIG. The NRZ data transmitted from the FIFO 38 is a series of data strings of PLO, SYNC, DATA, ECC, and POST, and is a data string that can be directly recorded via the data recording circuit 11. When the WG signal rises, the NRZ data is directly recorded on the recording medium. Therefore, it is not necessary to indicate the recording position with the SBD signal as described above, and the timing control is simplified.
[0189]
<Playback operation>
During the reproduction operation, the data correction circuit 15 activates the VALID signal simultaneously with the transmission of the NRZ data. The VALID signal and NRZ data are connected to the FIFO 38 of the data flow control circuit 22 as shown in FIG. When the VALID signal is active, the FIFO 38 takes in the NRZ data, and then sends the data to the decoding circuit 16.
[0190]
The detailed timing of the VALID signal is the same as that of FIG. 18 described above except that the NRZ data is the data before being decoded by the decoding circuit 16, and corresponds to the timing of the data output to the NRZ data. Occur. The rising edge of the SBD signal is output by detecting the SYNC area on the recording medium, and the NRZ data and the VALID signal are output after a reproduction delay time after SYNC detection. The data flow control circuit 22 outputs the NRZ data to the buffer control circuit 23 via the decoding circuit 16.
[0191]
According to the above-described embodiment, even with a data recording / reproducing apparatus having a different configuration, the control circuit can be similarly simplified by configuring the magnetic recording / reproducing apparatus based on the control signal (VALID signal) indicating the data output period. .
[0192]
-Other embodiments-
In the first, second, third, and fourth embodiments, the magnetic disk device has been described as an example. However, other data recording / reproducing devices such as a magneto-optical disk device and a magnetic tape device are also described. The present invention can be applied. Further, the present invention can also be applied to an LSI level data reproducing apparatus which is a component constituting a data recording / reproducing apparatus such as a magnetic disk apparatus, a magneto-optical disk apparatus, and a magnetic tape apparatus.
[0193]
【The invention's effect】
According to the data reproduction apparatus of the present invention, the synchronization information detection signal is output from the synchronization information detection means having substantially no delay, instead of outputting the synchronization information detection signal from the data reproduction means whose output is delayed by the reproduction delay time. Therefore, the end position of the block on the recording medium can be accurately calculated based on the synchronization information detection signal without being influenced by the reproduction delay time. Therefore, it is not necessary to provide an additional area (pad area PAD for a magnetic disk) longer than the reproduction delay time at the end of the block in order to ensure that the data reproducing means reads the information of the block from the recording medium. . Therefore, the additional area can be minimized, the data storage area that can be used effectively can be increased, and the data recording efficiency can be improved.
[0194]
Similarly, a decrease in data recording efficiency due to a recording delay can be minimized in the recording operation.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a magnetic disk device according to a first embodiment.
FIG. 2 is an internal block diagram of a format control circuit and a data flow control circuit according to the first embodiment.
FIG. 3 is a timing chart showing a relationship between information on a track and a format control signal according to the first embodiment.
FIG. 4 is a timing diagram of a single sector reproduction operation according to the first embodiment.
FIG. 5 is a timing diagram of continuous sector reproduction operation according to the first embodiment.
FIG. 6 is a reproduction operation timing chart when symbol synchronization information SYNC is not detected according to the first embodiment.
FIG. 7 is an explanatory diagram illustrating a control procedure of the sequencer and the data flow control circuit according to the first embodiment.
FIG. 8 is a block diagram showing a main part of a magnetic disk device according to a second embodiment.
FIG. 9 is a timing diagram of continuous sector reproduction operation according to the second embodiment.
FIG. 10 is a reproduction operation timing chart when symbol synchronization information SYNC is not detected according to the second embodiment.
FIG. 11 is an internal block diagram of a format control circuit and a data flow control circuit according to a second embodiment.
FIG. 12 is an explanatory diagram showing a control procedure of a sequencer and a data flow control circuit according to the second embodiment.
FIG. 13 is an explanatory diagram of a general track format of a magnetic disk.
FIG. 14 is a timing chart showing the relationship between information on a track and a format control signal in a conventional magnetic disk device.
FIG. 15 is a block diagram showing a magnetic recording / reproducing apparatus according to a third embodiment.
FIG. 16 is an internal block diagram of a format control circuit and a data flow control circuit according to a third embodiment.
FIG. 17 is a timing diagram of a single sector recording operation according to the third embodiment.
FIG. 18 is a timing diagram of a single sector reproduction operation according to the third embodiment.
FIG. 19 is a block diagram showing a magnetic recording / reproducing apparatus according to a fourth embodiment.
FIG. 20 is an internal block diagram of a format control circuit and a data flow control circuit according to a fourth embodiment.
FIG. 21 is a timing diagram of a single sector recording operation according to the fourth embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Magnetic disk apparatus, 2 ... Magnetic disk, 6, 6 '... Recording / reproduction processing circuit, 7, 7' ... Data control circuit, 21, 41 ... Format control circuit, 22, 42 ... Data flow control circuit, 33, 50 ... Sequencer, 40 ... SYNC code generation circuit, SBD ... Synchronization information detection signal, RG ... Read gate signal.

Claims (3)

A recording in which a data sequence having bit synchronization information for performing bit synchronization, symbol synchronization information for performing symbol synchronization, data, correction information for correcting this data, and an additional area is recorded as a block Synchronization information detecting means for detecting symbol synchronization information of a block to be reproduced from the medium and outputting a synchronization information detection signal;
Block end position calculating means for calculating an end position of the block on the recording medium based on the synchronization information detection signal;
Data reproducing means for reproducing the data up to the end position of the block and the correction information from a recording medium;
The synchronization information detection signal on the basis of the, process the data and the correction information are played back after the elapse of the reproduction delay time, the data reproducing apparatus comprising the data processing means for outputting. A first unit including the synchronization information detecting means and the data reproducing means;
A second unit including the block end position calculating means and the data processing means,
The synchronization information detection signal is sent from the first unit to the second unit, and after the synchronization information detection signal is sent, the data is sent from the first unit to the second unit. The data reproducing apparatus according to claim 1, wherein A data range defining means for outputting a data confirmation signal indicating a range of data output from the data reproducing means; a first unit including the synchronization information detecting means and the data reproducing means;
A second unit including the block end position calculating means and the data processing means,
The synchronization information detection signal is sent from the first unit to the second unit, and after the synchronization information detection signal is sent, the data and the data confirmation signal are sent from the first unit to the second unit. The data reproducing apparatus according to claim 1, wherein:

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