JP2002544587A - デジタル信号プロセッサ計算コア - Google Patents

デジタル信号プロセッサ計算コア

Info

Publication number
JP2002544587A
JP2002544587A JP2000616500A JP2000616500A JP2002544587A JP 2002544587 A JP2002544587 A JP 2002544587A JP 2000616500 A JP2000616500 A JP 2000616500A JP 2000616500 A JP2000616500 A JP 2000616500A JP 2002544587 A JP2002544587 A JP 2002544587A
Authority
JP
Japan
Prior art keywords
operand
digital signal
instruction
signal processor
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000616500A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002544587A5 (enExample
Inventor
アンダーソン，ウィリアム・キャロル
エドモンドソン，ジョン
フリードマン，ジョセ
ホッフマン，マーク
リヴィン，ラッセル・エル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of JP2002544587A publication Critical patent/JP2002544587A/ja
Publication of JP2002544587A5 publication Critical patent/JP2002544587A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Image Processing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Error Detection And Correction (AREA)
JP2000616500A 1999-05-12 2000-05-12 デジタル信号プロセッサ計算コア Pending JP2002544587A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13376699P 1999-05-12 1999-05-12
US60/133,766 1999-05-12
PCT/US2000/013232 WO2000068783A2 (en) 1999-05-12 2000-05-12 Digital signal processor computation core

Publications (2)

Publication Number Publication Date
JP2002544587A true JP2002544587A (ja) 2002-12-24
JP2002544587A5 JP2002544587A5 (enExample) 2007-07-05

Family

ID=22460216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000616500A Pending JP2002544587A (ja) 1999-05-12 2000-05-12 デジタル信号プロセッサ計算コア

Country Status (3)

Country Link
EP (4) EP1188112A2 (enExample)
JP (1) JP2002544587A (enExample)
WO (1) WO2000068783A2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235004A (ja) * 2004-02-20 2005-09-02 Altera Corp 乗算器−累算器ブロックモード分割
JP2008530642A (ja) * 2005-02-07 2008-08-07 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト 低レイテンシーの大量並列データ処理装置
JP2020507154A (ja) * 2017-01-23 2020-03-05 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 回路、システム、および組合せ結果を演算するように再設定可能な複数の再設定可能ユニットを備えたプロセッサにより実装される方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2001269394A1 (en) * 2000-07-28 2002-02-13 Delvalley Limited A method of processing data
JP4338514B2 (ja) 2001-08-29 2009-10-07 メディアテック インコーポレーテッド プロセッサ性能を改善するためのフラッシュバーストモードを利用する方法および装置
CN100559905C (zh) 2005-07-20 2009-11-11 大唐移动通信设备有限公司 基带芯片
US7555514B2 (en) 2006-02-13 2009-06-30 Atmel Corportation Packed add-subtract operation in a microprocessor
JP5481793B2 (ja) 2008-03-21 2014-04-23 富士通株式会社 演算処理装置および同装置の制御方法
CA2751388A1 (en) * 2011-09-01 2013-03-01 Secodix Corporation Method and system for mutli-mode instruction-level streaming
FR3021428B1 (fr) * 2014-05-23 2017-10-13 Kalray Multiplication de matrices de bits utilisant des registres explicites
CN108334337B (zh) * 2018-01-30 2022-02-01 江苏华存电子科技有限公司 含自动管理功能的低延迟指令调度器及过滤猜测访问方法
CN113157636B (zh) * 2021-04-01 2023-07-18 西安邮电大学 协处理器、近数据处理装置和方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255433A (ja) * 1985-05-07 1986-11-13 Mitsubishi Electric Corp 演算装置
JPH0876977A (ja) * 1994-09-06 1996-03-22 Matsushita Electric Ind Co Ltd 固定小数点演算装置
JPH0922379A (ja) * 1995-05-02 1997-01-21 Hitachi Ltd マイクロコンピュータ
WO1997008608A1 (en) * 1995-08-31 1997-03-06 Intel Corporation A set of instructions for operating on packed data
JPH09212361A (ja) * 1996-02-07 1997-08-15 Mitsubishi Electric Corp データ処理装置およびデータ処理方法
JPH10512988A (ja) * 1995-09-01 1998-12-08 フィリップス エレクトロニクス ノース アメリカ コーポレイション プロセッサのカスタム動作のための方法及び装置
JPH11500547A (ja) * 1994-12-01 1999-01-12 インテル・コーポレーション 乗算を有するマイクロプロセッサ
JPH11511577A (ja) * 1995-08-31 1999-10-05 インテル・コーポレーション パック・データの乗加算演算を実行する装置

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
JPH077356B2 (ja) * 1989-05-19 1995-01-30 株式会社東芝 パイプライン方式のマイクロプロセッサ
US5175863A (en) * 1989-10-23 1992-12-29 International Business Machines Corporation Signal data processing system having independently, simultaneously operable alu and macu
US5926644A (en) * 1991-10-24 1999-07-20 Intel Corporation Instruction formats/instruction encoding
DE69327504T2 (de) * 1992-10-19 2000-08-10 Koninklijke Philips Electronics N.V., Eindhoven Datenprozessor mit Operationseinheiten, die gemeinsam Gruppen von Registerspeichern benutzen
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
US5710914A (en) * 1995-12-29 1998-01-20 Atmel Corporation Digital signal processing method and system implementing pipelined read and write operations
US5822606A (en) * 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5954811A (en) 1996-01-25 1999-09-21 Analog Devices, Inc. Digital signal processor architecture
GB2317466B (en) * 1996-09-23 2000-11-08 Advanced Risc Mach Ltd Data processing condition code flags
US6530014B2 (en) * 1997-09-08 2003-03-04 Agere Systems Inc. Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits
US6260137B1 (en) 1997-09-12 2001-07-10 Siemens Aktiengesellschaft Data processing unit with digital signal processing capabilities

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255433A (ja) * 1985-05-07 1986-11-13 Mitsubishi Electric Corp 演算装置
JPH0876977A (ja) * 1994-09-06 1996-03-22 Matsushita Electric Ind Co Ltd 固定小数点演算装置
JPH11500547A (ja) * 1994-12-01 1999-01-12 インテル・コーポレーション 乗算を有するマイクロプロセッサ
JPH0922379A (ja) * 1995-05-02 1997-01-21 Hitachi Ltd マイクロコンピュータ
WO1997008608A1 (en) * 1995-08-31 1997-03-06 Intel Corporation A set of instructions for operating on packed data
JPH11511575A (ja) * 1995-08-31 1999-10-05 インテル・コーポレーション パック・データを処理する１組の命令
JPH11511577A (ja) * 1995-08-31 1999-10-05 インテル・コーポレーション パック・データの乗加算演算を実行する装置
JPH10512988A (ja) * 1995-09-01 1998-12-08 フィリップス エレクトロニクス ノース アメリカ コーポレイション プロセッサのカスタム動作のための方法及び装置
JPH09212361A (ja) * 1996-02-07 1997-08-15 Mitsubishi Electric Corp データ処理装置およびデータ処理方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235004A (ja) * 2004-02-20 2005-09-02 Altera Corp 乗算器−累算器ブロックモード分割
JP2008530642A (ja) * 2005-02-07 2008-08-07 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト 低レイテンシーの大量並列データ処理装置
JP2020507154A (ja) * 2017-01-23 2020-03-05 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 回路、システム、および組合せ結果を演算するように再設定可能な複数の再設定可能ユニットを備えたプロセッサにより実装される方法

Also Published As

Publication number Publication date
EP2267596B1 (en) 2018-08-15
WO2000068783A3 (en) 2001-08-09
EP2267597A3 (en) 2012-01-04
EP1188112A2 (en) 2002-03-20
WO2000068783A2 (en) 2000-11-16
EP2267597A2 (en) 2010-12-29
EP2267896A2 (en) 2010-12-29
EP2267596A3 (en) 2012-01-04
EP2267896A3 (en) 2013-02-20
EP2267596A2 (en) 2010-12-29

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