JP2002534739A5 - - Google Patents
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- Publication number
- JP2002534739A5 JP2002534739A5 JP2000592743A JP2000592743A JP2002534739A5 JP 2002534739 A5 JP2002534739 A5 JP 2002534739A5 JP 2000592743 A JP2000592743 A JP 2000592743A JP 2000592743 A JP2000592743 A JP 2000592743A JP 2002534739 A5 JP2002534739 A5 JP 2002534739A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/224,184 US6243782B1 (en) | 1998-12-31 | 1998-12-31 | Method and apparatus for disabling a graphics device when an upgrade device is installed |
US09/224,184 | 1998-12-31 | ||
PCT/US1999/029705 WO2000041085A1 (en) | 1998-12-31 | 1999-12-14 | Method and apparatus for disabling a graphics device when an upgrade device is installed |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2002534739A JP2002534739A (ja) | 2002-10-15 |
JP2002534739A5 true JP2002534739A5 (US06811534-20041102-M00003.png) | 2007-01-25 |
JP4503851B2 JP4503851B2 (ja) | 2010-07-14 |
Family
ID=22839618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000592743A Expired - Fee Related JP4503851B2 (ja) | 1998-12-31 | 1999-12-14 | アップグレード・デバイスがインストールされるとグラフィックス・デバイスを使用不可にする方法および装置 |
Country Status (10)
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6760031B1 (en) * | 1999-12-31 | 2004-07-06 | Intel Corporation | Upgrading an integrated graphics subsystem |
US7079149B2 (en) * | 2001-10-09 | 2006-07-18 | Texas Instruments Incorporated | System, method, and device for accelerated graphics port linking |
US20050228877A1 (en) * | 2004-04-07 | 2005-10-13 | Arnold Monitzer | System for managing a device |
US6985152B2 (en) * | 2004-04-23 | 2006-01-10 | Nvidia Corporation | Point-to-point bus bridging without a bridge controller |
US20050273525A1 (en) * | 2004-06-03 | 2005-12-08 | Anderson David D | Dynamic I/O disabling systems and methods |
TWM261731U (en) * | 2004-08-03 | 2005-04-11 | Uniwill Comp Corp | A display expanding structure for a portable information device |
US20160070665A1 (en) * | 2014-09-08 | 2016-03-10 | Htc Corporation | Portable electronic device and user data access method therefor |
US11356236B2 (en) * | 2019-05-16 | 2022-06-07 | Texas Instruments Incorporated | Bidirectional re-driver for half-duplex interfaces |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220069A (ja) * | 1985-07-19 | 1987-01-28 | Canon Inc | 画像情報変換方式 |
JPH0671310B2 (ja) * | 1986-03-04 | 1994-09-07 | キヤノン株式会社 | 画像読取装置 |
JP2698834B2 (ja) * | 1988-11-22 | 1998-01-19 | 株式会社日立製作所 | 不揮発性記憶装置 |
JPH02162762A (ja) * | 1988-12-16 | 1990-06-22 | Hitachi Ltd | 半導体集積回路装置 |
US5280579A (en) * | 1990-09-28 | 1994-01-18 | Texas Instruments Incorporated | Memory mapped interface between host computer and graphics system |
WO1992018936A1 (en) * | 1991-04-18 | 1992-10-29 | Intel Corporation | Method and apparatus for upgrading a computer processing system |
EP0527015A2 (en) * | 1991-08-06 | 1993-02-10 | AT&T Corp. | Low power signaling using output impedance delay |
JPH05274868A (ja) * | 1992-03-26 | 1993-10-22 | Mitsubishi Electric Corp | メモリ制御装置 |
JP3529805B2 (ja) * | 1992-03-27 | 2004-05-24 | ナショナル・セミコンダクター・コーポレイション | ハードウェア制御パワー管理機能と選択可能な入出力制御ピンとを有するマイクロプロセッサ |
AU1989395A (en) * | 1994-03-14 | 1995-10-03 | Apple Computer, Inc. | A peripheral processor card for upgrading a computer |
JPH09135159A (ja) * | 1995-11-07 | 1997-05-20 | Oki Data:Kk | 駆動能力切替機能付き出力バッファ装置 |
US5740409A (en) * | 1996-07-01 | 1998-04-14 | Sun Microsystems, Inc. | Command processor for a three-dimensional graphics accelerator which includes geometry decompression capabilities |
US5866958A (en) * | 1996-12-10 | 1999-02-02 | Samsung Electronics Co., Ltd. | Power control device for redundant reset outputs in an ATM system and method of power control thereof |
US5996037A (en) * | 1997-06-03 | 1999-11-30 | Lsi Logic Corporation | System and method for arbitrating multi-function access to a system bus |
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1998
- 1998-12-31 US US09/224,184 patent/US6243782B1/en not_active Expired - Lifetime
-
1999
- 1999-12-14 EP EP99967318A patent/EP1141846B1/en not_active Expired - Lifetime
- 1999-12-14 CN CNB998153613A patent/CN1230760C/zh not_active Expired - Fee Related
- 1999-12-14 DE DE69907966T patent/DE69907966T2/de not_active Expired - Lifetime
- 1999-12-14 KR KR10-2001-7008236A patent/KR100393717B1/ko not_active IP Right Cessation
- 1999-12-14 AU AU23618/00A patent/AU2361800A/en not_active Abandoned
- 1999-12-14 WO PCT/US1999/029705 patent/WO2000041085A1/en active IP Right Grant
- 1999-12-14 JP JP2000592743A patent/JP4503851B2/ja not_active Expired - Fee Related
-
2000
- 2000-01-13 TW TW088123323A patent/TW459180B/zh not_active IP Right Cessation
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2001
- 2001-10-29 HK HK01107534A patent/HK1036657A1/xx not_active IP Right Cessation