JP2002530774A - Numerical operations in data processing systems - Google Patents

Abstract

(57) [Summary] In the case of the general operation, in order to execute the multiplication of Q15 and the accumulation operation of Q31 together, the processing proceeds as follows. First, the value of Q15 is read out from register bank (8) onto buses A and B and provided as input to single cycle integer multiplier (16). The result, having a format similar to Q30, is fed back to the register bank (8). When one of the new instructions (eg, the QDADD instruction) is executed in a subsequent processing cycle, a multiplication result similar to Q30 is read out to the A bus, and the Q31 accumulated value is read out to the B bus. The value similar to Q30 is left shifted or saturated by one bit by the shift and saturation unit (26) and provided as one input to the arithmetic and logic unit (22).

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a data processing system. More particularly, the present invention relates to a data processing system for performing a mathematical operation suitable for performing a saturated arithmetic operation.

[0002] Many DSP algorithms use algorithms known as Q15 and Q31 operations. Q15 number is the normal two's complement integers of 16 bits, have been recognized to represent the integer divided by 2 ^15. 16 2's complement integer bits -2 ¹⁵ +2 ¹⁵ - Since a number up to 1 can be represented, Q15 can represent a number from -1 to + (1-2 ^-15 ).

Similarly, the Q31 number is an ordinary 32-bit two's complement integer, which is recognized as an integer divided by 2 ³¹ , from −1 to − ( ^1-2−31 ). Can be represented. By analogy, a (N + 1) -bit QN number can be defined for any value of N.

An important feature of the Q15 and Q31 math operations is that they are “saturated”
ng) ". If the mathematical operation result of the operation exceeds the positive maximum value (+1-2 ^-N ), the saturated result is the positive maximum value. Similarly, if the mathematical operation result is smaller than -1, the saturated result is It is -1. For example, in the Q15 numerical operation, if A = 0x8000 (representing -1) and B = 0xC000 (representing -0.5), the result of adding A and B is the normal 16-bit two's complement result 0x4000. 0x8000 (representing -1).

[0005] The most demanding and commonly occurring operation in DSP algorithms is the "multiply-accumulate" operation, that is, the multiplication of two operands followed by a third operand, the result = (A ^* B) + C.

A serious problem arises when one wants to use such a multiply-accumulate instruction for a saturated numerical operation (sometimes known as clipping). This problem is particularly true when performing numerical operations on QN numbers.

[0007] Adapting a variety of different types of instructions to both saturated and non-saturated forms requires a significant amount of instruction code bit space. Moreover, the pursuit of single-cycle multiplication performance adds the burden of having to deal with saturation and the associated tuning requirements. That is, the worst case, if not required, saturation multiply instruction will limit the clock speed.

Viewed from one aspect, the present invention comprises a command decoder for generating a processing control signal in response to a data processing command, and a data processing operation controlled by the processing control signal for a data operand word. Processing logic to execute, wherein the command decoder generates a control signal for controlling the processing logic in response to a first command word, wherein the first decoder decodes the first N-bit data. Data that performs a data processing operation on operand word P and a second N-bit data operand word Q to produce an N-bit result data word R given by R = Sat (Fun (P) + Q) A processing device is provided. Where Sat (X) is a function that returns a saturated value X, and Fun (X) is at least a value of X that can be generated by a signed multiplication of N / 2 bits and N / 2 bits. A function that operates on the shifted word to generate a shifted word by shifting X by a shift amount and returns a value obtained by saturating the shifted word.

The present invention recognizes that it is very advantageous to provide special purpose instructions suitable for addressing the requirements of a saturated multiply-accumulate operation. More specifically, the timing requirements for a standard desired single-cycle multiply are needed to address the saturating nature of the math that easily adapts to the cycles used in subsequent instructions that perform the accumulation operation. Relaxed by adjustment. This new instruction eliminates the need to define a saturated version of some multiply instructions, reducing the bit space of the opcode and other overhead required to support saturated math. Finally, the new instructions are implemented with little additional hardware to the hardware already provided in the system and can address other aspects of unsaturated and saturated math.

It will be appreciated that the hardware used to execute this new instruction can take many different forms. The various operations required to generate the N-bit final result data word are grouped in various different ways and performed in various circuit blocks. All of these different alternatives for using a single instruction to generate an N-bit final result data word of the same final value as the value given above are all embodiments of the present invention.

Similar to the above instructions used in saturation multiplication / accumulation operations, similar instructions can be provided to support saturation multiplication / subtraction.

The shift amount used in the instruction of the present invention can take various different values.
However, a shift amount such that the shifted word is twice the first N-bit data operand word P is particularly useful.

When an integer multiplication is performed on two Q15 numbers, the result that typically occurs is a Q30-like number of 32 bits, for which a normal 32-bit code is used. since the value of 2's complement attached is recognized to be divided by 2 ^30, -2 + ^- represents the number of up to (2-2 ^30). A number similar to Q30 may be considered a signed 32-bit fixed-point number with 30 binary positions. However, in such a situation, what is required for the subsequent processing is the Q31 number. To address this problem, the instructions of the present invention are executed after a standard integer multiplication, and before the result of the integer multiplication saturates and accumulates or decrements, the result is doubled, similar to Q30. The shift amount may be used to change the format from the changed format to the Q31 format. Thus, one of the problematic adjustments needed to support saturated math is that the integers that are accommodated in subsequent instructions are not instructions that must be provided at the end of the multiplication cycle. An adjustment to the result of the multiplication is provided.

The logic that performs the saturation can take many different forms. However, in a preferred embodiment of the present invention, saturating the shifted word comprises:
If a predetermined characteristic of the bit data operand word P is detected and detected, the shifted value is exchanged with a value at an end point of the allowable value range.

It has been recognized that this feature can be saturated by detecting the feature of the first N-bit data operand word P in some circumstances. This is because the operations performed on the feature are of a relatively limited form and can clearly detect situations where an overflow or underflow requiring saturation can be detected, resulting in a hard response. This is because the requirements of the wear are comprehensively relaxed.

In particular, when the shift amount used doubles the first N-bit data operand word P, it is necessary to saturate the first N-bit data operand word P
It is very easily detected by comparing the bits.

Comparing the relatively limited range of situations in which the overflow or underflow of the Fun (X) instruction can occur, because the overflow or underflow of the Sat (X) function occurs more commonly, In a preferred embodiment, Sat (X) detects whether X is outside the allowable value range, and if detected, replaces each end point of X and the allowable value range with the N-bit result data word R. appear.

Although the new instructions of the present invention have their own advantages, as described above, these instructions are based on a third N / 2-bit data operand word A and a fourth N / 2-bit data word. It is particularly well suited to embodiments where multiplying the operand word B executes a second instruction word that generates a first N-bit data operand word.

The instructions of the present invention can be used for any kind of operand. However, this instruction is particularly useful in an embodiment because the first N bits
The operand data word P, the second N-bit operand data word Q and the N-bit result data word R are −1 ≦ P <+1, −1 ≦ Q <+1, −1 ≦ R <+ 1 is a signed fixed-point data word embodiment with a decimal point immediately to the right of the most significant bit position such that Sat (X) exists for the range −1 ≦ X <+1. .

As discussed above, such QN operands require the coordination and saturation provided effectively by the instructions of the present invention without unduly affecting the rest of the data processing system.

The most useful value of the first N-bit data operand word P is the value that can be generated by N / 2-bit and N / 2-bit signed multiplication. However, the preferred embodiment of the present invention extends the functionality of Fun (X) so that all possible N-bit values of X can be shifted and saturated.

The present invention can be used in systems where N has a variety of different values. However, the type of DSP operation for which the present invention is particularly useful usually requires a value of N, such as N = 32.

While it will be appreciated that the invention can be implemented as a system including discrete components, it is highly preferred that the data processing device be implemented as an integrated circuit.

Viewed from another aspect, the present invention comprises a step of generating a processing control signal in response to a data processing instruction, and a data processing operation on a data operand word under the control of the processing control signal. And generating a control signal for controlling the processing logic in response to a first command;
A data processing operation is performed on the N-bit data operand word P and the second N-bit data operand word Q, and an N-bit result data word given by R = Sat (Fun (P) + Q) A data processing method for generating R is provided. Where Sat (X) is a function that returns a saturated value X, and Fun (X) is at least a value of X that can be generated by a signed multiplication of N / 2 bits and N / 2 bits. A function that operates on the shifted word to generate a shifted word by shifting X by a shift amount and returns a value obtained by saturating the shifted word.

There is also provided an aspect of the complementary method of the present invention, in which the instruction performs a subtraction rather than an addition operation.

Hereinafter, embodiments of the present invention will be described by way of example only with reference to the accompanying drawings.

FIG. 1 shows a portion of an integrated circuit 2 including an instruction decoder 4 and processing logic 6 (similar to a portion of an ARM9TDMI microprocessor manufactured by ARM, Cambridge, UK). The processing logic 6 consists of a number of different individual functional elements. The register bank 8 stores data operand words (P, Q) to be operated. These words are read from the register bank 8 and provided to the various other processing units in the processing logic 6 via the multiplexers 10, 12, 14. The integer multiplier 16 is provided to execute signed integer multiplication among functions. The adder 18 is provided to execute the unsaturated multiplication / accumulation operation and to convert the result of the multiplier from the carry-save into a two's complement format. A shifter 20 and an arithmetic logic unit 22 are also provided. The above basic components of the processing logic 6 are generally known. Control signals 24 from command decoder 4 are applied to various elements in processing logic 6 to control and coordinate their operation. More specifically,
When the instruction is decoded by the instruction decoder, a control signal 24 is output, various multiplexers in the processing logic 6 are switched to select a desired data path, and various logic units in the processing logic 6 are activated. Configure and perform the operation specified by the decoded instruction. For clarity, the signal lines connecting the individual components to the command decoder have been omitted from this figure.

To support additional instructions for saturating math (QDADD, DQDSUB and QDRSB)
A shifting and saturating unit (shifting and saturating unit) upstream of the arithmetic and logic unit 22
A full saturating unit 28 is provided in the feedback path to the register bank 8 of the next pipeline stage after the pipeline stage in which the arithmetic and logic unit 22 operates. Have been. In operation, the shift / saturation unit 26 first receives the input 32-bit data.
Check to determine that the two most significant bits of the data word are not equal. Shifting one bit left when this condition is detected will result in an overflow or underflow if the input data word represents a Q30-like word that is converted to a Q31 word by this left shift. When the two most significant bits are “01”, the shift / saturation unit 26 outputs 0x7FFFFFFF representing the maximum end point of the allowable value range. Similarly, when the two most significant bits are “10”, the shift / saturation unit 26 outputs 0x80000000 representing the minimum end point of the allowable value range. If none of these conditions are detected,
The shift / saturation unit 26 shifts the input binary data value to the left by one bit position in response to doubling the input binary data value, and is thus obtained by integer multiplication of the Q15 number and the Q15 number. The expression similar to Q30 is converted into the expression of Q31 required for subsequent processing (eg, accumulation) and saturation.

If the particular instruction being decoded does not require this operation, the shift-saturation unit 26 can be disconnected from the operation in response to the appropriate control signal 24 from the instruction decoder 4. Since the shift / saturation unit 26 is arranged on the A bus, the timing constraint of this bus is usually less strict than that of the B bus including the shifter 20. Thus, no significant timing issues are added to the shift and saturation unit 26.

The full saturation unit 28 is provided in a return path that the arithmetic and logic unit 22 uses after performing the required addition or subtraction. The total saturation unit 28
Operating according to known principles, it is possible to detect an overflow or underflow of a signed result generated by the arithmetic and logic unit 22 and correct the result to a value at the maximum or minimum endpoint of the allowable value range. Like the shift / saturation unit 26,
The full saturating unit 28 can decouple the full saturating unit 28 from operation in response to an appropriate control signal 24 if this saturation is not required. Since the full saturating unit 28 is normally in a pipeline stage that does nothing for add and subtract instructions, no timing problems occur. However, the full saturating unit 28 may use
During one cycle, the processor requests that it interlock. This interlock is handled in the same way as the interlock that occurs in many microprocessors when the value loaded by a load instruction is used by the immediately following instruction.

In the case of the overall operation, in order to execute the multiplication of Q15 and Q15 together with the accumulation operation of Q31,
Processing proceeds as follows. First, the value of Q15 is read from register bank 8 onto buses A and B and sent as input to single cycle integer multiplier 16. The result, having a format similar to Q30, is fed back to register bank 8. In a subsequent processing cycle, one of the new instructions (eg, the QDADD instruction) is executed, the result of the multiplication similar to Q30 is read on the A bus, and the Q31 accumulated value is read on the B bus. The value similar to Q30 is left shifted or saturated by one bit in the shift / saturation unit 26 and supplied to the arithmetic and logic unit 22 as one input. The value of the B bus Q31 is provided as a separate input to the arithmetic logic unit 22 by using an appropriate control signal 24 which prevents the shifter 20 from shifting its input value. shift·
When saturating unit 26 corrects the value similar to Q30 to the required saturated value of Q31, arithmetic logic unit 22 adds this value to the value of Q31 on the B bus.
Once the output from the arithmetic and logic unit 22 is provided to the full saturation unit 28, the value of this value is determined by detecting the overflow and underflow flags and other standard conditions from the arithmetic and logic unit 22. Becomes saturated in Q31 before being stored in the register bank 8. Instead of the arithmetic logic unit 22 performing the addition, it is appropriate to subtract the value of the A bus from the value of the B bus with the QDRSB instruction, or to subtract the value of the B bus from the value of the A bus with the QDSUB instruction. The control may be performed by the control signal 24. The configuration of the arithmetic and logic unit that performs the subtraction in response to the appropriate control signal 24 from the command decoder can be implemented in various standard ways.

It can be seen from the above that the operations performed by the QDADD, QDSUB and QDRSB instructions are divided in various ways among the various functional units in the processing logic. Those skilled in the art will recognize that the division of these operations among the various units can be performed in many different ways while producing the same end result.

FIG. 2 is a flowchart showing processing steps executed by the QDADD instruction. At step 40, a test is performed as to whether the two most significant bits of the first 32-bit data operand word are equal to "01". In this case, since the overflow when it shifted left by 1 bit, using steps 42, setting this value to a positive maximum allowable value (+ 1-2 ^31). Similarly, step 44 determines that the two most significant bits are
Check to see if it is "10", indicating that shifting left will result in underflow. If detected in this case, step 46 determines this value as the minimum allowable value-
Set to 1.

If neither an overflow nor an underflow is detected, step 48 comprises a first
Is shifted left by one bit position, and if the left shift is the shift indicated by the digit, the data word is converted from a format similar to Q30 to a Q31 format. The operations from step 40 to step 48 correspond to the shift and saturation unit 26 and the function provided by the previously described Fun (x) function.

In step 50, an addition is performed. This addition corresponds to the addition performed by the arithmetic and logic unit 22 of FIG.

Steps 52 and 54 detect and address overflow of the saturation value resulting from step 50. Similarly, steps 56 and 58 deal with underflow. If neither overflow nor underflow is detected, no correction is made. The result R of the QDADD instruction is stored in a register in the register bank 8 in step 60.

The calculation performed in steps 52 to 58 is performed by the full saturation unit 2 in FIG.
8 corresponds to the operation given by the Sat (X) function discussed above.

FIG. 3 is a similar flowchart, but in this case for a QDSUB instruction. In this instruction, step 50 of FIG. 2 is replaced by step 62 in which the second 32-bit operand data word Q is subtracted from the shifted and saturated first operand data word P.

FIG. 4 is similar to FIG. 3, but in this case, the subtraction performed in step 62 of FIG. 3 is reversed in step 64 in FIG.

[Brief description of the drawings]

FIG. 1 is a diagram showing an instruction decoder and processing logic in an integrated circuit.

FIG. 2 is a diagram showing a flowchart of an operation of an instruction prepared to support a saturated numerical operation.

FIG. 3 is a diagram showing a flowchart of an operation of an instruction prepared to support a saturated numerical operation.

FIG. 4 is a diagram showing a flowchart of an operation of an instruction prepared to support a saturated numerical operation.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] September 18, 2000 (2000.9.18)

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[0007] Adapting a variety of different types of instructions to both saturated and non-saturated forms requires a significant amount of instruction code bit space. In addition, the pursuit of single-cycle multiplication performance enhancements adds the burden of having to deal with saturation and the associated tuning requirements. That is, the worst case, if not required, saturation multiply instruction will limit the clock speed. Perform a full Q15 multiply-accumulate operation in UK published patent application GB-A-2,317,465
Multiply-doubling instruction (Multiply Double instructions) is, for example, optionally size is changed dest = SAT and ^{(acc + SAT (2 * src1} * src2)), optionally in that changed in size dest = ( It is disclosed that it is prepared by one instruction such as acc-SAT (2 ^* src1 ^* src2)) .

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Viewed from one aspect, the present invention comprises a command decoder for generating a processing control signal in response to a data processing command, and a data processing operation controlled by the processing control signal for a data operand word. Processing logic to execute, wherein the command decoder generates a control signal for controlling the processing logic in response to a first command word, wherein the first decoder decodes the first N-bit data. and operand word P, the second N-bit data operand word Q to perform data processing operations, R = Sat (Fun (P ) + Q) results of N bits provided by generating the data word R And a data processing device characterized by the following. Where Sat (X) is a function that returns a saturated value X, and Fun (X) is at least a value of X that can be generated by a signed multiplication of N / 2 bits and N / 2 bits. A function that operates on the shifted word to generate a shifted word by shifting X by a shift amount and returns a value obtained by saturating the shifted word.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] November 30, 2000 (2000.11.30)

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Viewed from another aspect, the present invention comprises a step of generating a processing control signal in response to a data processing instruction, and a data processing operation on a data operand word under the control of the processing control signal. And generating a control signal for controlling the processing logic in response to a first command;
A data processing operation is performed on the N-bit data operand word P and the second N-bit data operand word Q, and an N-bit result data word given by R = Sat (Fun (P) + Q) to provide a data processing method in a data processing equipment, characterized by generating a R. Where Sat (X) is a function that returns a saturated value X, and Fun (X) is at least a value of X that can be generated by a signed multiplication of N / 2 bits and N / 2 bits. A function that operates on the shifted word to generate a shifted word by shifting X by a shift amount and returns a value obtained by saturating the shifted word.

Claims (15)

[Claims] 1. A data processing apparatus, comprising: an instruction decoder for generating a processing control signal in response to a data processing instruction; and a data processing operation for a data operand word controlled by the processing control signal. And a processing logic comprising: a command decoder responsive to a first command to generate a control signal for controlling the processing logic; and a first N-bit data operand word. A data processing apparatus for performing data processing operations on P and a second N-bit data operand word Q to generate an N-bit result data word R given by: R = Sat (Fun (P) + Q) where Sat (X) is a function that returns the saturated value X, and Fun (X) is at least N / 2-bit and N / 2-bit signed A function that operates on the value of X that can be generated by multiplication, generates a shifted word by shifting X by a shift amount, and returns a value obtained by saturating the shifted word. It is. 2. A data processing apparatus, comprising: an instruction decoder for generating a processing control signal in response to a data processing instruction; and a data processing operation controlled by the processing control signal for a data operand word. And a processing logic comprising: a command decoder responsive to a first command to generate a control signal for controlling the processing logic; and a first N-bit data operand word. A data processing apparatus for performing data processing operations on P and a second N-bit data operand word Q to generate an N-bit result data word R given by: R = Sat (Fun (P) -Q) where Sat (X) is a function that returns the saturated value X, and Fun (X) is at least N / 2-bit and N / 2-bit signed A function that operates on the value of X that can be generated by multiplication, generates a shifted word by shifting X by a shift amount, and returns a value obtained by saturating the shifted word. It is. 3. A data processing device, comprising: an instruction decoder for generating a processing control signal in response to a data processing instruction; and a data processing operation controlled by the processing control signal for a data operand word. And a processing logic comprising: a command decoder responsive to a first command to generate a control signal for controlling the processing logic; and a first N-bit data operand word. A data processing apparatus for performing data processing operations on P and a second N-bit data operand word Q to generate an N-bit result data word R given by: R = Sat (Q−Fun (P)) where Sat (X) is a function that returns the saturated value X, and Fun (X) is at least N / 2 bit and N / 2 bit signed A function that operates on the value of X that can be generated by multiplication, generates a shifted word by shifting X by a shift amount, and returns a value obtained by saturating the shifted word. It is. 4. The data processing device according to claim 1, wherein the shift amount is such that the shifted word is the first N-bit data operand word P. The above data processing device, wherein the shift amount is doubled. 5. The data processing apparatus according to claim 1, wherein said saturating said shifted word is performed on said first N-bit data.
Detecting a predetermined feature of the operand word P, and if detected, the shifted value;
The data processing device for exchanging respective end points of an allowable value range. 6. The data processing device according to claim 4, wherein the first
The data processing device, wherein the N-bit data operand word is a signed value, and wherein the predetermined feature is that the two most significant bits of the first N-bit data operand word P are not equal. 7. The data processing device according to claim 1, wherein Sat (X) detects whether X is outside an allowable value range, and if detected, X; The data processing device for generating the N-bit result data word R by exchanging respective end points of the allowable value range. 8. The data processing apparatus according to claim 1, wherein the processing logic includes a multiplier, and wherein the first N-bit operand data word P is a second instruction word. The data processing device is a multiplication result generated by a signed multiplication of the third N / 2-bit data operand word A and the fourth N / 2-bit data operand word B in response to 9. The data processing apparatus according to claim 1, wherein said first N-bit operand data word P, said second N-bit operand data word Q and said N The bit result data word R is −1 ≦ P <+1, −1 ≦ Q <+
1, signed fixed-point data word with a decimal point immediately to the right of the most significant bit position, such that Sat (X) exists for the range −1 ≦ X <+1, with −1 ≦ R <+1 The data processing device described above. 10. The data processing apparatus according to claim 1, wherein Fun (X) operates on all N-bit values of X and shifts X by the shift amount. The data processing apparatus being a function that generates a shifted word and returns a value obtained by saturating the shifted word. 11. The data processing device according to claim 1, wherein N = 32. 12. The data processing device according to claim 1, wherein the data processing device includes an integrated circuit. 13. A method for processing data, the method comprising: generating a processing control signal in response to a data processing command; and performing a data processing operation on a data operand word under the control of the processing control signal. Executing a first control signal in response to a first command to control the processing logic;
The above method of performing a data processing operation on an N-bit data operand word P and a second N-bit data operand word Q to generate an N-bit result data word R given by: R = Sat (Fun (P) + Q) where Sat (X) is a function that returns the saturated value X, and Fun (X) is at least N / 2-bit and N / 2-bit signed A function that operates on the value of X that can be generated by multiplication, generates a shifted word by shifting X by a shift amount, and returns a value obtained by saturating the shifted word. It is. 14. A method of processing data, the method comprising: generating a processing control signal in response to a data processing command; and performing a data processing operation on a data operand word under control of the processing control signal. Executing a first control signal in response to a first command to control the processing logic;
The above method of performing a data processing operation on an N-bit data operand word P and a second N-bit data operand word Q to generate an N-bit result data word R given by: R = Sat (Fun (P) -Q) where Sat (X) is a function that returns the saturated value X, and Fun (X) is at least N / 2-bit and N / 2-bit signed A function that operates on the value of X that can be generated by multiplication, generates a shifted word by shifting X by a shift amount, and returns a value obtained by saturating the shifted word. It is. 15. A method of processing data, the method comprising: generating a processing control signal in response to a data processing command; and performing a data processing operation on a data operand word under control of the processing control signal. Executing a first control signal in response to a first command to control the processing logic;
The above method of performing a data processing operation on an N-bit data operand word P and a second N-bit data operand word Q to generate an N-bit result data word R given by: R = Sat (Q−Fun (P)) where Sat (X) is a function that returns the saturated value X, and Fun (X) is at least N / 2 bit and N / 2 bit signed A function that operates on the value of X that can be generated by multiplication, generates a shifted word by shifting X by a shift amount, and returns a value obtained by saturating the shifted word. It is.