JP2002373402A - Drive circuit for magnetic head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a miniature magnetic head drive circuit having low power consumption. SOLUTION: Transistors 106, 110, 108, 112 are turned on/off by pulse voltages from a control circuit 26, and currents changing over the polarity are made to flow into a coil 104 of a magnetic head to generate a magnetic field, then the information is recorded on a disk. A spike-like voltage produced in both ends of the coil at that time with a changeover timing is fed back to a gate through a parasitic capacity between the gate and a drain, but the operation of the parasitic capacitance is negated since the spike-like voltages of opposite polarity are supplied respectively to the gate of each transistor through capacitors 4, 6, 8, 10. Thus, equivalent input capacitance, formed by the mirror effect due to the parasitic capacitance, is eliminated, then the load is not imposed on the control circuit 26, and then reduction of power consumption and the miniaturization are realized. Also, the pulse voltages are supplied to the gates of the transistors 106, 108 through clamp circuits thereby a negative power source is dispensed with.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic head drive circuit for applying a magnetic field to an information recording medium in order to record information on the information recording medium.

[0002]

2. Description of the Related Art In recent years, a magneto-optical disk has been put to practical use as a recording medium for music and various digital data. In particular, a user can record music and data on a magneto-optical disk in addition to a reproduction-only medium. The system is widespread. As an information recording method for such a magneto-optical disk, a so-called magnetic field modulation method is widely used.

FIG. 5 is a conceptual diagram for explaining a recording operation in a magnetic field modulation system. As shown in FIG. 5, in the case of the magnetic field modulation method, the optical head 92 and the magnetic head 93 are used as recording heads for the disk 91.
That are arranged to face each other with the. During the recording operation, the perpendicular magnetic film 91a on the surface of the disk 19 is irradiated with laser light from the optical head 92, and the recording portion of the perpendicular magnetic film 91a is at a temperature higher than the Curie temperature. In this state, a magnetic field whose direction changes in response to the inversion of the recording data waveform is applied from the magnetic head 93, and the corresponding magnetic pattern is recorded on the perpendicular magnetization film 91a.
In a disk drive device that employs such a magnetic field modulation method, a drive circuit for the magnetic head 93 is provided, and the drive circuit controls the coil 93a of the magnetic head 93 by using the drive circuit.
A drive current corresponding to the recording data is supplied.

FIG. 6 is a circuit diagram showing an example of such a conventional magnetic head drive circuit. The magnetic head drive circuit 102 shown in FIG. 6 takes a form called an H-bridge circuit, and uses a P-channel MOS-FET as a switching element to supply a drive current to a coil 104 of the magnetic head.
(Metal-Oxide-Semiconductor Field Effect Transisto
r) first and third transistors 106, 1
08 and second and fourth transistors 110 and 112 which are N-channel MOS-FETs.

The drains of the first and second transistors 106 and 110 are connected to the coil 104 of the magnetic head.
And one end of the third and fourth transistors 1
The drains of 08 and 112 are connected to the other end of the coil 104. Further, the second and fourth transistors 11
The sources of 0 and 112 are connected to ground, and the sources of the first and third transistors 106 and 108 are connected to a positive power supply line 114. However, the drains of the first and third transistors 106 and 108 are connected to one end and the other end of the coil 104 via diodes 116 and 118, respectively.

In such a configuration, a pulse voltage 120 having a waveform corresponding to the waveform of data to be recorded on the disk 91 is applied to the gate of each transistor, and each transistor is turned on and off, so that the coil 104 A drive current IL whose polarity is switched according to the recording data waveform flows, and a corresponding magnetic field is generated to record information on the disk 91.

[0007]

The first to fourth transistors 106, 110, 108, 112
Constitute a switching circuit which is turned on / off by the pulse voltage applied to the gate as described above, and this switching circuit is also an inverting amplifier circuit having an extremely large voltage gain. Then, a parasitic capacitance exists between the gate and the drain of each transistor, and this parasitic capacitance acts as a feedback capacitance of the inverting amplifier having the extremely large voltage gain. As a result, a large-capacity capacitor Ci is equivalently connected as an input capacitance to the input of each inverting amplifier circuit, that is, to the gate of each transistor due to the Miller effect.

Therefore, the control circuit 122 for supplying a pulse voltage to each transistor must supply the pulse voltage to the gate of each transistor while charging and discharging the equivalent input capacitance Ci, and a large driving capability is required. Met. In particular, in order to increase the information recording density on the disk 91 and to improve the information transfer rate, each transistor must be turned on and off at a high speed, and unless the rising and falling of the pulse voltage is steep. Therefore, the control circuit 122 needs to have a higher driving capability.

However, the provision of the high driving capability increases the power consumption of the control circuit 122, which is disadvantageous for lowering the power consumption of the magnetic head driving circuit 102, and further requires control of a large circuit element. Enlargement of the circuit 122,
Therefore, the size of the magnetic head drive circuit 102 is increased.

In the conventional magnetic head drive circuit 102, in order to turn on the first and third transistors 106 and 108, a voltage sufficiently lower than the voltage Vdd of the power supply line 114 is applied to the gates of these transistors. There is a need to. Since the voltage Vdd of the power supply line 114 is usually about 1 to 2 V, it is necessary to apply a negative voltage to the gate in many cases in order to surely turn on the transistor. Accordingly, a negative power supply is provided for the control circuit 122 which conventionally generates the pulse voltage 120, and the voltage Vdd of the power supply line 114 is provided.
And a dedicated circuit for generating a pulse voltage that switches between a negative voltage and a negative power supply must be provided, which is disadvantageous in miniaturizing the control circuit 122.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a magnetic head drive circuit which is small and consumes less power.

[0012]

In order to achieve the above object, the present invention provides an on / off switch based on a voltage applied to a gate.
The first and second transistors are turned off, the drains of the first and second transistors are connected to one end of a coil of a magnetic head, and the drains of the third and fourth transistors are connected to the other end of the coil. Connected, the sources of the second and fourth transistors are connected to a first potential point, and the sources of the first and third transistors are connected to a second potential higher than the first potential point.
A magnetic head drive circuit that is connected to the potential point of 駆 動, supplies a drive current to the coil through the first to fourth transistors to generate a magnetic field, and records information on an information recording medium using the magnetic field. A first capacitor is connected between the gate of the first transistor and the drain of the third transistor, and a second capacitor is connected between the gate of the second transistor and the drain of the fourth transistor. A third capacitor is connected between a gate of the third transistor and a drain of the first transistor, and a third capacitor is connected between a gate of the fourth transistor and a drain of the second transistor. 4 is connected.

In the magnetic head drive circuit according to the present invention, the first and fourth transistors are controlled so as to be turned on / off simultaneously, while the second and third transistors are opposite in polarity to the first and fourth transistors. Is controlled to be turned on / off at the timing of. As a result, a drive current whose direction is switched flows through the coil, and a magnetic field corresponding to the drive current is generated, thereby recording information.

Here, when the direction of the drive current is switched, a spike-like voltage having a polarity corresponding to the direction of the drive current is generated at both ends of the coil. This spike voltage returns to the gate of each transistor through the parasitic capacitance between the gate and drain of each transistor, that is, the feedback capacitance. However, in the present invention, at the same time as the feedback through the parasitic capacitance, a spike voltage having a polarity opposite to that of the drain of the transistor is applied to the gate of each transistor from the terminal on the opposite side of the coil through each capacitor. Therefore, the spike-like voltage that is fed back by the parasitic capacitance is canceled by the spike-like voltage of the opposite polarity supplied through the capacitor, the effect of the parasitic capacitance is canceled, and the equivalent input capacitance due to the Miller effect is eliminated. as a result,
A control circuit that applies a pulse voltage to the gate of each transistor eliminates the burden of charging and discharging the equivalent input capacitance and only needs to have a low driving capability, so that power consumption can be reduced and the circuit can be downsized.

Further, the present invention includes first to fourth transistors which are turned on / off based on a voltage applied to a gate, and the drains of the first and second transistors are connected to one end of a coil of a magnetic head. Connected, the drains of the third and fourth transistors are connected to the other end of the coil, the sources of the second and fourth transistors are connected to a first potential point, and the first and third transistors are connected. A source of the transistor is connected to a second potential point higher in voltage than the first potential point, and supplies a drive current to the coil through the first to fourth transistors to generate a magnetic field, and the information is generated by the magnetic field. A magnetic head drive circuit for recording information on a recording medium,
The pulse voltage applied to the gate of the transistor of
A first clamping circuit for clamping the high-level voltage so as to substantially coincide with the voltage at the second potential point; and a pulse voltage applied to the gate of the third transistor, wherein the high-level voltage is A second clamp circuit for clamping the voltage to substantially match the voltage at the second potential point.

In the magnetic head drive circuit according to the present invention, the pulse voltage applied to the gate of the first transistor is controlled by the first clamp circuit so that the high-level voltage substantially matches the voltage at the second potential point. Is clamped to
The pulse voltage applied to the gate of the third transistor is clamped by the second clamp circuit so that the high-level voltage substantially matches the voltage at the second potential point.

Therefore, the pulse voltage does not need to be a pulse voltage that switches between the voltage at the second potential point and a voltage having a different polarity from the voltage at the second potential point. It may be a pulse voltage whose voltage level switches between the voltage at the second potential point. Therefore, a circuit for generating a voltage pulse only needs to generate a pulse voltage having the same voltage polarity as the second potential point, so that a special circuit is not required. There is no need to provide a power supply. Therefore, the circuit configuration is simplified, and the size of the circuit can be reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an example of a magnetic head drive circuit according to the present invention, and FIG. 2 is a waveform diagram showing the operation of the magnetic head drive circuit of FIG. 1, the same elements as those in FIG. 6 are denoted by the same reference numerals.
The magnetic head drive circuit 2 of the embodiment shown in FIG.
An H bridge circuit is formed in the same manner as in the prior art, and first and third P-channel MOS-FETs as switching elements are used to supply a drive current to the coil 104 of the magnetic head.
Transistors 106 and 108 and an N-channel MO
Second and fourth transistors 11 which are S-FETs
0 and 112 are included.

The drains of the first and second transistors 106 and 110 are connected to the coil 104 of the magnetic head.
And the drains of the third and fourth transistors 108 and 112 are connected to the other end of the coil 104 (point b). The sources of the second and fourth transistors 110 and 112 are connected to the ground, and the first and third transistors 106 and 108 are connected.
Is connected to a positive power supply line 24 (voltage Vdd is, for example, 1 to 2 V). However, the first and third
Of the transistors 106 and 108 are diodes 116 and 1 having the drain side as the anode, respectively.
18 to one end of the coil 104 and the other end.

Further, in this embodiment, first to fourth capacitors 4, 6, 8, and 10 are provided, and each capacitor is connected to the gate of the first transistor 106 and the drain of the third transistor 108, respectively. , Between the gate of the second transistor 110 and the drain of the fourth transistor 112, between the gate of the third transistor 108 and the drain of the first transistor 106, and the gate of the fourth transistor 112. And the drain of the second transistor 110.

Next, the operation of the magnetic head drive circuit 2 configured as described above will be described with reference to FIG. When the waveform of the data DR to be recorded on the disc (not shown) is as shown in FIG. 2A, the data waveform is at a high level, for example, in a period T1,
The control circuit 26 applies a low-level voltage Vg1 to the gate of the first transistor 106 (FIG. 2B), and applies a high-level voltage Vg4 to the gate of the fourth transistor 112 (FIG. 2B). (E of FIG. 2).
On the other hand, the low-level voltage Vg2 is applied to the gate of the second transistor 110 (FIG. 2C), and the high-level voltage Vg is applied to the gate of the third transistor 108.
g3 is applied (FIG. 2D).

As a result, during this period T1, the first
The fourth and fourth transistors 106 and 112 are turned on, the second and third transistors 110 and 108 are turned off, and the current IL flows through the coil 104 ((H) in FIG. 2). In a period T2 following the period T1, the data waveform is inverted to a low level. In the period T2, a voltage of the inverted polarity is applied from the control circuit 26 to the gate of each transistor. As a result, in the period T2, the first and fourth transistors 106 and 112 are turned off, and the second and third transistors 110 and 108 are turned off.
Is turned on, and a current IL having a polarity opposite to that of the period T1 flows through the coil 104 ((H) in FIG. 2). When such a drive current IL is supplied to the coil 104, information is recorded on the disk.

By the way, at the timing of starting the period T1 and the timing of transition from the period T1 to the period T2,
The pulse voltage applied to the gate of each transistor is
The level switches, and the current IL flowing through the coil 104 reverses its direction. Therefore, at these timings, the current IL changes rapidly, and the coil 10
A spike-like voltage having a high reverse polarity (for example, about 20 Vpp) is generated at both ends of 4. FIG. 2F shows the spike voltage Va at point a, and FIG. 2G shows the spike voltage Vb at point b.

These spike-like voltages (ie, high-frequency signals) are fed back to the gate through parasitic capacitance (feedback capacitance) between the gate and drain of each transistor. On the other hand, in the present embodiment, as described above, the first to fourth
These capacitors 4, 6, 8, 10 are connected, so that these spike voltages are applied to the gates of the respective transistors through the first to fourth capacitors 4, 6, 8, 10. That is, the spike voltage generated at the point a is applied to the gate of the third transistor 108 through the third capacitor 8 and to the gate of the fourth transistor 112 through the fourth capacitor 10. Further, the spike voltage generated at the point b is applied to the gate of the first transistor 106 through the first capacitor 4 and is applied to the gate of the second transistor 110 through the second capacitor 6.

The spike voltage applied to the gates of the first to fourth transistors 106, 110, 108, 112 through the first to fourth capacitors 4, 6, 8, 10 respectively is equal to the spike voltage. The polarity is opposite to the spike-like voltage that is fed back from the drain through the parasitic capacitance. Therefore, the spike-like voltage that is fed back by the parasitic capacitance is canceled by the spike-like voltage of the opposite polarity supplied through each capacitor, the effect of the parasitic capacitance is canceled, and the equivalent input capacitance due to the Miller effect is eliminated. As a result, in the present embodiment, the control circuit 26 does not need to supply a transient current to the equivalent input capacitance, and does not need to have a high driving capability as in the related art. Miniaturization can be realized.

As described above, the voltage supplied to the gate side of each transistor through the first to fourth capacitors 4, 6, 8, and 10 is opposite to the voltage fed back from the drain of each transistor through the parasitic capacitance. The first to fourth capacitors 4, 6, 8, and 10 function as neutralizing capacitors for neutralizing the parasitic capacitance because the capacitors have polarities and the effect of the parasitic capacitance is canceled by the operation of each capacitor. Can be said.

In the present embodiment, the drains of the first and third transistors 106 and 108 and the coil 104
Diodes 116 and 118 are interposed between each terminal of
Since the drain voltages of the first and third transistors 106 and 108 are prevented from being higher than the voltage Vdd of the power supply line 24, the first and third capacitors having one ends connected to the drains of these transistors are prevented. The maximum level of the spike voltage applied to 4, 8 is limited. Therefore, the capacity of the first and third capacitors 4, 8 is equal to the capacity of the second and fourth capacitors 6,
It is desirable to set the capacitance larger than 10 so that a spike-like voltage of the opposite polarity is applied to the gate with a sufficient magnitude. Specifically, good results can be obtained by setting the capacitances of the first and third capacitors 4 and 8 to, for example, about 50 pF, and the capacitances of the second and fourth capacitors 6, 10 to, for example, about 5 pF.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a magnetic head drive circuit as a second embodiment, and FIG. 4 is a waveform diagram showing the operation of the magnetic head drive circuit of FIG. In FIG. 3, FIG.
The same elements as those described above are denoted by the same reference numerals. As shown in FIG. 3, the magnetic head drive circuit 12 according to the second embodiment includes first and third transistors 106,
8 are connected to the first and second clamp circuits 14 and 16
Is different from the conventional one. The first and second clamp circuits 14, 16 are respectively provided with capacitors 18,
The capacitor 18 of the first clamp circuit 14 is connected in series to the gate of the first transistor 106, and the parallel circuit of the diode 20 and the resistor 22
The first transistor 1 with the anode of
06 and the power supply line 24. On the other hand, the capacitor 18 of the second clamp circuit 16
Is connected in series to the gate of the third transistor 108, and the parallel circuit of the diode 20 and the resistor 22
The diode 20 is connected between the gate of the third transistor 108 and the power supply line 24 with the anode of the diode 20 on the gate side.

In such a configuration, the control circuit 26
However, assuming that the voltage levels of the first and third transistors 106 and 108 are switched between 0 V and 3 V, for example, pulse voltages Vg1 and Vg3 are output.
These pulse voltages are entirely shifted in the negative direction by the first and second clamp circuits, and the high-level voltage is clamped to a voltage substantially equal to the voltage Vdd (1-2 V) of the power supply line 24. You.

The first clamp circuit 14 will be described in detail by way of example. As shown in FIG. 4A, when the pulse voltage Vg1 output from the control circuit 26 is high, for example, the diode 20 is turned on. As a result, the capacitor 18 is rapidly charged, and the voltage across the capacitor 18 is reduced from the high-level voltage Vgh (3 V) of the pulse voltage to the forward voltage drop V
The voltage becomes Vgh-Vdf obtained by subtracting df.

When the pulse voltage Vg1 becomes low level,
The electric charge accumulated in the capacitor 18 is discharged through the resistor 22. If the time constant determined by the resistor 22 and the capacitor 18 is set to be sufficiently large, this discharge becomes gentle, and the pulse voltage Vg1 is at a low level, and both ends of the capacitor 18 are discharged. Voltage Vgh-Vdf hardly changes. Therefore, the gate of the first transistor 106 has the pulse voltage Vg as shown in FIG.
A pulse voltage Vg1 'obtained by subtracting the voltage Vgh-Vdf at both ends of the capacitor 18 from 1 is applied. The high-level voltage of the pulse voltage Vg1 ′ exceeds the voltage of the power supply line 24 by a voltage corresponding to the forward voltage Vdf of the diode 20, but since the forward voltage Vdf of the diode 20 is small, the voltage of the power supply line 24 is almost the same. Matches. On the other hand, the low-level voltage Vdd-V of the pulse voltage Vg1 '
gh + Vdf is a negative voltage when the high-level voltage of the pulse voltage Vg1 is 3 V and the power supply voltage Vdd is 1 to 2 V. Since the first and second clamp circuits 14 and 16 have the same configuration, the same applies to the second clamp circuit 16.
Can be said about.

Therefore, in the present embodiment, the control circuit 26 only needs to generate a pulse voltage that switches between 0 V and 3 V, and switches between a negative voltage and a positive voltage as in the prior art. Since there is no need to generate a replacement pulse, no special circuit is required, and there is no need to provide a negative power supply. Therefore, the circuit configuration is simplified, and the size of the circuit can be reduced.

Here, the first and second clamp circuits 1 according to the present invention are added to the conventional magnetic head drive circuit.
Although the description has been given of the case where the magnetic head driving circuit 4 and 16 are provided, the clamp circuit according to the present invention is provided in the magnetic head driving circuit 2 of the first embodiment, and the above-described first to fourth capacitors 4, 6, and 8 are provided. 10 and the effect of the first and second clamp circuits 14 and 16 can be simultaneously obtained.

[0034]

As described above, in the magnetic head drive circuit of the present invention, the first and fourth transistors are controlled to be turned on and off simultaneously, while the second and third transistors are controlled to be the first and fourth transistors. It is controlled so as to be turned on / off at a timing opposite to that of the fourth transistor. As a result, a drive current whose direction is switched flows through the coil, and a magnetic field corresponding to the drive current is generated, thereby recording information.

Here, when the direction of the drive current is switched, a spike-like voltage having a polarity corresponding to the direction of the drive current is generated at both ends of the coil. This spike voltage returns to the gate of each transistor through the parasitic capacitance between the gate and drain of each transistor, that is, the feedback capacitance. However, in the present invention, at the same time as the feedback through the parasitic capacitance, a spike voltage having a polarity opposite to that of the drain of the transistor is applied to the gate of each transistor from the terminal on the opposite side of the coil through each capacitor. Therefore, the spike-like voltage that is fed back by the parasitic capacitance is canceled by the spike-like voltage of the opposite polarity supplied through the capacitor, the effect of the parasitic capacitance is canceled, and the equivalent input capacitance due to the Miller effect is eliminated. as a result,
A control circuit that applies a pulse voltage to the gate of each transistor eliminates the burden of charging and discharging the equivalent input capacitance and only needs to have a low driving capability, so that power consumption can be reduced and the circuit can be downsized.

In the magnetic head drive circuit of the present invention,
The pulse voltage applied to the gate of the first transistor is clamped by the first clamp circuit so that the high-level voltage substantially matches the voltage at the second potential point,
The pulse voltage applied to the gate of the third transistor is clamped by the second clamp circuit so that the high-level voltage substantially matches the voltage at the second potential point.

Therefore, the pulse voltage need not be a pulse voltage that switches between the voltage at the second potential point and a voltage having a different polarity from the voltage at the second potential point. It may be a pulse voltage whose voltage level switches between the voltage at the second potential point. Therefore, a circuit for generating a voltage pulse only needs to generate a pulse voltage having the same voltage polarity as the second potential point, so that a special circuit is not required. There is no need to provide a power supply. Therefore, the circuit configuration is simplified, and the size of the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a magnetic head drive circuit according to the present invention.

FIG. 2 is a waveform chart showing an operation of the magnetic head drive circuit of FIG.

FIG. 3 is a circuit diagram showing a magnetic head drive circuit as a second embodiment.

FIG. 4 is a waveform chart showing an operation of the magnetic head drive circuit of FIG. 3;

FIG. 5 is a conceptual diagram for explaining a recording operation in a magnetic field modulation method.

FIG. 6 is a circuit diagram showing an example of a conventional magnetic head drive circuit.

[Explanation of symbols]

2 ... magnetic head drive circuit, 4 ... first capacitor, 6 ... second capacitor, 8 ... third capacitor, 10 ... fourth capacitor, 12 ... magnetic head drive circuit, 14 ... ... first clamp circuit, 16 ... second clamp circuit, 18 ... capacitor, 20 ... diode, 22 ... resistor, 24 ... power supply line, 26 ...
… Control circuit, 91… disk, 92… optical head,
93 ... magnetic head, 93a ... coil, 102 ... magnetic head drive circuit, 104 ... coil, 106 ... first
Transistor 108, the third transistor,
110: second transistor, 112: fourth transistor, 114: power supply line, 116: diode, 118: diode, 120: pulse voltage, 122: control circuit.

Claims (9)

[Claims] A first transistor that turns on and off based on a voltage applied to a gate;
The drains of the first and second transistors are connected to one end of a coil of a magnetic head, and the third and fourth transistors are connected to one end of a coil of the magnetic head.
Are connected to the other end of the coil, the sources of the second and fourth transistors are connected to a first potential point, and the sources of the first and third transistors are connected to the first potential. A magnetic head connected to a second potential point higher in voltage than the point, supplying a drive current to the coil through the first to fourth transistors to generate a magnetic field, and recording information on an information recording medium by the magnetic field A drive circuit, wherein a first capacitor is connected between a gate of the first transistor and a drain of the third transistor, and a first capacitor is connected between a gate of the second transistor and a drain of the fourth transistor. A second capacitor is connected between the gate of the third transistor and the drain of the first transistor The third capacitor is connected, a magnetic head drive circuit a fourth capacitor is characterized in that it is connected between said fourth gate and a drain of the second transistor of the transistor. 2. A semiconductor device comprising: first to fourth transistors that are turned on / off based on a voltage applied to a gate;
The drains of the first and second transistors are connected to one end of a coil of a magnetic head, and the third and fourth transistors are connected to one end of a coil of the magnetic head.
Are connected to the other end of the coil, the sources of the second and fourth transistors are connected to a first potential point, and the sources of the first and third transistors are connected to the first potential. A magnetic head connected to a second potential point higher in voltage than the point, supplying a drive current to the coil through the first to fourth transistors to generate a magnetic field, and recording information on an information recording medium by the magnetic field A drive circuit, comprising: a first clamp circuit that clamps a pulse voltage applied to a gate of the first transistor such that a high-level voltage substantially matches a voltage at the second potential point; The pulse voltage applied to the gate of the third transistor is clamped such that its high-level voltage substantially matches the voltage at the second potential point. Second magnetic head driving circuit, characterized in that it includes a clamp circuit that. 3. The first clamp circuit includes a diode and a capacitor, and the diode has a cathode having the second potential point side and the second potential point and the first potential point.
3. The magnetic head drive circuit according to claim 2, wherein the capacitor is connected between the gate of the first transistor and the capacitor, and the capacitor is connected in series with the gate of the first transistor. 4. The second clamp circuit includes a diode and a capacitor, wherein the diode has a cathode having the second potential point side and the second potential point connected to the third potential point.
3. The magnetic head drive circuit according to claim 2, wherein the capacitor is connected between the gate of the third transistor and the capacitor is connected in series with the gate of the third transistor. 5. A pulse voltage for simultaneously turning on and off the first and fourth transistors is applied to the gates of the first and fourth transistors, and the gate of the second and third transistors is applied to the gates of the second and third transistors. 3. A pulse voltage applied to turn off the first and fourth transistors when the first and fourth transistors are on and to turn on the first and fourth transistors when the first and fourth transistors are off. The magnetic head drive circuit according to the above. 6. The magnetic head drive circuit according to claim 1, wherein the first potential point is a ground, and the second potential point is a positive power supply line. 7. The drain of the first transistor is connected to one end of the coil through a diode having the drain side as an anode, and the drain of the third transistor is connected to the diode having the drain side as an anode. 2. The magnetic head drive circuit according to claim 1, wherein the magnetic head drive circuit is connected to the other end of the coil. 8. The magnetic head drive circuit according to claim 7, wherein the capacities of the first and third capacitors are larger than the capacities of the second and fourth capacitors. 9. The magnetic head according to claim 1, wherein the first and third transistors are P-channel MOS-FETs, and the second and fourth transistors are N-channel MOS-FETs. Drive circuit.