JP3144601B2 - Magnetic head drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 3 and 4) Problems to be Solved by the Invention (FIGS. 3 to 5) Means for Solving the Problems (FIGS. 1 and 2) Action (FIGS. 1 and 2) Embodiments (1) Configuration of Embodiment (FIGS. 1 and 2) (2) Effects of Embodiment (3) Other Embodiments Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic head drive device, and more particularly, to a magnetic head drive device suitable for use in a magneto-optical disk device for thermomagnetically recording desired information by applying a thermomagnetic recording technique.

[0003]

2. Description of the Related Art Conventionally, in thermomagnetic recording, a predetermined magnetic magnetic recording medium is irradiated with a light beam while applying a modulation magnetic field corresponding to recording information, so that the irradiation position of the light beam is determined by the modulation magnetic field. Magnetization is performed perpendicularly to the polarity, so that desired information can be recorded.

Therefore, in this type of thermomagnetic recording,
By driving the magnetic head using a magnetic head drive circuit, a drive current whose polarity is switched according to recorded information is supplied to a coil of the magnetic head. At this time, in this type of magnetic head drive circuit, since the coil of the magnetic head is an inductive load, the sag of the drive current is reduced, and thereby a uniform and sufficient modulation magnetic field can be formed. I have.

[0005] For example, as shown in FIG.
In the magnetic head drive circuit 1 described in the publication, P and N channel power MOS transistors 2 and 4 are connected in series through a series connection circuit of protection diodes D1 and D3, and these transistors 2 and 4 are connected to a power source 6. Connecting. Further, in the magnetic head drive circuit 1, similarly, a P diode is connected via a series connection circuit of protection diodes D2 and D4.
And N-channel power MOS transistors 8 and 10
Are connected in series, and the transistors 8 and 10 are connected to the power supply 6.

For the transistors 2 to 10, the magnetic head driving circuit 1 connects a magnetic head 12 for forming a modulation magnetic field in parallel with a capacitor 14, and connects the magnetic head 12 to a connection point between the diodes D1 and D3 and a diode. It is connected between the connection points of D2 and D4. Further, the magnetic head drive circuit 1 connects a series circuit of the damper diode D5 and the resistor 16 and a series circuit of the damper diode D6 and the resistor 18 to both ends of the magnetic head 12.

Thus, in the magnetic head drive circuit 1, the transistors 2 and 10 can be switched on to form a first current flow path of the transistor 2-diode D1-magnetic head 12-diode D4-transistor 10, Conversely, the transistors 4 and 8 are turned on, and the transistor 8-diode D2-magnetic head 1
A second current flow path of the 2-diode D3-transistor 4 can be formed.

Further, in the magnetic head drive circuit 1,
When the transistor 2 or the transistor 8 is turned off in a state where the first or second current flow path is formed, a sudden current fluctuation of the magnetic head 12 causes a diode D1 side terminal of the magnetic head 12 and a diode D1, respectively. A flyback pulse is formed at the D2 side terminal, and the terminal voltage of the magnetic head 12 sharply rises. As a result, in the magnetic head drive circuit 1, the second or first current flow path is subsequently formed, and the magnetic head 12 is formed by utilizing the flyback pulse.
Can be rapidly increased.

That is, as shown in FIG. 4, in the magnetic head drive circuit 1, the control signal
D1 and a predetermined clock CK (FIGS. 4 (A) and (B)) are received, and drive signals S1 to S4 (FIGS. 4 (C) to (F)) for the transistors 2 to 10 are generated.
In the control signal generation circuit 20, the transistors 2 and 10 and the transistors 4 and 8 are turned on / off in accordance with the recording information SD1, thereby forming first and second current flow paths.

At this time, in the control signal generating circuit 20, the second and first current flow paths are formed with a predetermined time delay from the timing of switching the transistors 2 and 8 to the off state, thereby forming the magnetic head 12
Are formed at both ends of the magnetic head 12 (FIGS. 4 (G) and 4 (H)), and the driving current I1 of the magnetic head 12 is formed.
Is rapidly switched (FIG. 4 (I)). Further, in the control signal generation circuit 20, after forming the first and second current flow paths, the transistors 2 and 8 are controlled to be turned on and off in synchronization with the clock CK, thereby lowering the drive current I1 indicated by the chain line. To prevent

Thus, in the magnetic head drive circuit 1, when the current flow path is switched, a flyback pulse is formed to rapidly switch the drive current I1, and then the transistors 2 and 8 are turned on and off little by little.
The drive current I1 is maintained at a constant value, so that a uniform and sufficient modulation magnetic field can be formed.

In the capacitor 14 connected in parallel to the magnetic head 12, when the transistors 2 and 8 are turned off, the resistor 16 and the diode D5 are connected.
A magnetic head 12-capacitor 14 and a resistor 18-diode D6-a current flow path for the magnetic head 12-condenser 14 is formed, whereby a flyback pulse P1 having a pulse width determined by the inductance of the magnetic head 12 and the capacity of the capacitor 14 And P2 are generated. In the magnetic head drive circuit 1, the capacitance of the capacitor 14 is selected to suppress the peak value of the flyback pulse P1.

[0013]

In the magnetic head drive circuit 1 shown in FIG. 3, it is necessary to secure the voltage of the power supply 6 at least about 6 [V]. There are difficult problems. For this reason, for example, it has been difficult to use the magnetic head drive circuit 1 in a portable magneto-optical disc device driven by a dry battery.

Further, in the magnetic head drive circuit 1,
By driving the transistors 2 to 10 in synchronization with the clock CK, the gate capacitances of the transistors 2 to 10 cannot be neglected, so that the configuration of the control signal generating circuit 20 becomes complicated.

As a method for solving this problem, for example, as shown in FIG.
Diodes D1 and D2, transistor 25, resistor 26
Are connected in series to a power supply VC, and the transistors 24 and 25 are alternately turned on and off according to the recording information D1. That is, in the magnetic head drive circuit 22, the connection midpoint between the diodes D1 and D2 is grounded by a series circuit of the capacitors 27 and 28, thereby driving the magnetic head 12 with the voltage across the capacitor 28.

However, in the magnetic head drive circuit 22, the drive current cannot be set large, and it is necessary to secure a power supply voltage of about 5 [V], and there is a problem that the drive current sag becomes large.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a magnetic head drive device capable of forming a uniform and sufficient modulation magnetic field even with a low power supply voltage with a simple configuration. .

[0018]

According to the present invention, there is provided a magnetic head driving apparatus for performing recording by applying a modulating magnetic field to a magnetic recording medium, wherein a first end of which is connected to a power supply voltage VDD. And the second switch means Q3, the other end of which is connected to the ground voltage, and the third switch means Q1, the other end of which is connected to the power supply voltage.
Switch means Q2 and the fourth switch means Q4, the other end of which is connected to the ground voltage, are connected in series, and the recording information signal S
D1 is directly applied to the first and fourth switch means Q1, Q4 and the second and third switch means Q2, Q3, and complementarily turned on / off, thereby controlling the first and second switch means Q1, Q3. A resistor 32 and a magnetic head 1 are connected between the connection midpoint and the connection midpoint of the third and fourth switch means Q2, Q4.
2 drive coils are connected in series and the magnetic head 1
The capacitor 14 was connected in parallel to the second drive coil.

[0019]

Further, in the present invention, the first, second, third and fourth switch means Q1, Q3, Q2, Q4 are
It is configured by a field effect transistor or a bipolar transistor.

[0021]

The first and third switch means Q1, Q2 and the second switch means
And the fourth switch means Q3 and Q4 are complementarily turned on and off, and the connection point of the first and second switch means Q1 and Q3 is connected to the third and fourth switch means via a resistor 32 having a predetermined resistance value. If the connection point between Q2 and Q4 is connected to the drive coil of the magnetic head 12, the polarity of the drive current can be changed to the recording information SD.
1, the sag of the drive current I2 can be reduced.

A capacitor 1 having a predetermined capacity is connected to the drive coil.
4, the polarity of the drive current I2 can be rapidly switched.

Further, the first, second, third and fourth switch means Q1, Q3, Q2, Q4 can be constituted by field effect transistors or bipolar transistors, so that the overall structure can be simplified.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Configuration of the embodiment In FIG. 1 where the same reference numerals are assigned to the corresponding parts in FIG. 3, reference numeral 30 denotes a magnetic head drive circuit as a whole, and a connection point between the diodes D1 and D3 and the magnetic head. A resistor 32 is interposed between 12. Further, in the magnetic head drive circuit 30, transistors Q1 to Q4 composed of general MOS-FETs are arranged in place of the P and N channel power MOS transistors 2 to 10, and these transistors Q1 to Q4
Are driven by drivers 34 to 40 having a CMOS-TTL configuration.

Here, as shown in FIG.
0, recording information SD1 composed of an EFM modulated signal
The transistors Q1 to Q4 are driven based on (FIG. 2A), and when the recording information SD1 is at the logic "H" level, the transistors Q1 and Q4 are switched to the ON state (FIG.
(B)), transistor Q1-diode D1-resistor 3
2-magnetic head 12-diode D4-transistor Q
4 is formed.

On the other hand, in the drivers 34 to 40, when the recording information SD1 is at the logical "L" level, the transistors Q2 and Q3 are used instead of the transistors Q1 and Q4.
Is turned on (FIG. 2C), and the transistor Q
A second current flow path comprising a 2-diode D2-magnetic head 12-resistor 32-diode D3-transistor Q3 is formed.

Thus, in the magnetic head drive circuit 30, the polarity of the drive current I2 (FIG. 2D) for driving the magnetic head 12 is switched according to the recording information D1, so that a predetermined modulation magnetic field can be formed. It has been done.

Further, in the drivers 34 to 40, the timing at which the transistors Q1 and Q2 are turned on is switched after a predetermined period of time from the timing at which the corresponding transistors Q2 and Q1 are turned off. When the current I2 is switched, a flyback pulse is formed to rapidly raise the drive current I2.

Thus, in the drivers 34 to 40,
Following the recording information SD1, the transistors Q1 to Q4
Need only be controlled on and off, the transistors Q1 to Q4 can be driven at a low frequency at which the gate capacitance of the transistors Q1 to Q4 can be ignored. Thereby, in the magnetic head drive circuit 30, the CMOS-T
The whole can be configured using the drivers 34 to 40 having a simple configuration of the TL configuration, and the entire configuration can be simplified accordingly.

When the magnetic head 12 is driven in this manner with the resistor 32 omitted, the driving current I2
, A sag as shown by a dashed line occurs. This kind of sag changes according to the load connected between the diodes D1 and D2, and can be reduced by increasing the resistance value of this load.

However, if the L / R of the magnetic head 12 is simply reduced, adverse effects such as difficulty in rapidly changing the polarity of the drive current I2 occur. Therefore, in this embodiment, the resistor 32 is interposed between the diode D1 and the magnetic head 12, thereby suppressing the sag of the drive current I2.

As a result, in the magnetic head drive circuit 30, the peak value of the drive current I2 can be suppressed, and the voltage of the drive power supply V _DD is reduced by the voltage of the transistors Q1 to Q4.
_It can be reduced to _TH , and a uniform and large modulation magnetic field can be formed with a correspondingly lower power supply voltage.

Furthermore, since a wide variety of general MOS-FETs can be used for the transistors Q1 to Q4, design work and the like can be simplified accordingly. Further, if the resistor 32 is connected to the magnetic head 12 in this manner, the resistance value of the resistor 32 is selected and the driving current I2
And the current value of the drive current I2 can be freely selected as needed.

(2) Effects of the Embodiment According to the above-described configuration, the magnetic head is driven by connecting a resistor in series between the transistors of the switch circuit configuration that complementarily turns on and off, thereby driving the magnetic head with a simple configuration. Can reduce the sag of the driving current flowing through the device, and can form a uniform and sufficient modulation magnetic field with a correspondingly lower power supply voltage.

(3) Other Embodiments In the above-described embodiments, a case has been described in which a switch circuit that performs complementary ON / OFF operation is formed using a MOS-FET. However, the present invention is not limited to this. Various semiconductors such as a bipolar transistor can be widely applied.

[0037]

As described above, according to the present invention, switch circuits that are turned on and off complementarily are connected in series, the two sets of switch means connected in series are connected to a power supply, and the magnetic head has a predetermined resistance. By connecting a resistor of a value in series and connecting the two sets of switch circuits, sag of the drive current flowing through the magnetic head can be reduced with a simple configuration, and a capacitor can be connected in parallel to the magnetic head. Further, it is possible to obtain a magnetic head drive circuit capable of rapidly switching the polarity of the drive current and forming a uniform and sufficient modulation magnetic field with a correspondingly lower power supply voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a magnetic head drive circuit according to one embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation.

FIG. 3 is a block diagram showing a conventional magnetic head drive circuit.

FIG. 4 is a signal waveform diagram for explaining the operation.

FIG. 5 is a block diagram of a magnetic head drive circuit for explaining a problem of the conventional example.

[Explanation of symbols]

1, 22, 30 ... magnetic head drive circuit, 2, 4, 8,
10, 24, 25, Q1 to Q4 ... transistors, 12
...... Magnetic head, 14, 27, 28 ... Capacitor, 1
6, 18, 32: resistance, 34 to 40: driver, D
1 to D6: diodes.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 5/02 G11B 11/10

Claims (3)

(57) [Claims] 1. A recording method in which a modulation magnetic field is applied to a magnetic recording medium to perform recording.
A first switch means having one end connected to a power supply voltage;
In series with a second switch means having an end connected to the ground voltage
A third switch means connected to the power supply voltage and having one end connected to the power supply voltage.
And a fourth switch hand having the other end connected to the ground voltage.
Connect the stages in series,The recording information signal is transmitted to the first and fourth switch means and the
Directly apply to the second and third switch means and
Complementary on / off control,  The connection midpoint between the first and second switch means and the third switch means
And the connection point of the fourth switch means.Resistance and magnetism
Connect the head drive coil in series and
A capacitor was connected in parallel with the head drive coilthing
A magnetic head drive device characterized by the above-mentioned. 2. The first, second, third and fourth switches.
Means especially that consisting of field-effect transistors
2. The magnetic head drive device according to claim 1, wherein: 3. The first, second, third and fourth switches.
Means especially that consisting of the bipolar transistor
2. The magnetic head drive device according to claim 1, wherein: