JP2002368171A - Lead-type semiconductor element and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield and reliability of a lead-type semiconductor element and at the same time, to reduce the cost of the element by avoiding the occurrence of cracks in a chip by increasing the thicknesses of solder layers immediately below leads, and by reducing the thickness of solder a the terminating end sections of the chip, and so on. SOLUTION: The lead-type semiconductor element is provided with the chip 15, in which diffusion layers 12a and 12b and electrodes 14 connected to the layers 12a and 12b, are formed on the main surface of a substrate and leads 18 which are soldered to the main surfaces of the chip 15 and have truncated cone-shaped front ends. The front end angles of the leads 18 between tapered surfaces S of the leads 18 and the main surface of the substrate are adjusted to 10-18 deg..

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead type semiconductor element in which a chip having an element portion formed on a semiconductor substrate and a lead are brought into contact with each other using solder, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, there has been known a technique in which leads are connected to both main surfaces of a chip constituting an SBD (Schottky barrier diode) element by using solder. FIG.
(A) to (C) show a conventional method for manufacturing a lead-type semiconductor element in the order of steps.

First, p-type impurities are introduced into the surface of an n-type Si substrate 1 to form p-type diffusion layers 2a and 2b, respectively.
Next, a frame-shaped oxide film 3 is formed on the substrate 1 so as to partially overlap the diffusion layers 2a and 2b. Next, a square electrode 4 is formed on the surface side of the substrate 1 so that the end portion extends to the oxide film 3 to obtain an SBD chip. Thereafter, the solder tablets 5a and 5b are arranged on both main surface sides of the SBD chip (see FIG. 4A).

Next, the solder tablets 5a and 5b are melted to form solder layers 6a and 6b (see FIG. 4B). Subsequently, as shown in FIG. 5, a lead 7 having a truncated cone shape is mounted on both main surfaces of the SBD chip. At this time, the solder layers 6a and 6b crawl along the tapered surface S of the lead 7 (see FIG. 4C). Although not shown, after that, molding resin molding is performed to seal the SBD chip and a part of the lead 7.

In the conventional lead type semiconductor device, as shown in FIG. 5, the lead 7 has a tip angle (θ) between the tapered surface S of the lead 7 and the main surface of the substrate (SBD chip) of about 32 °. And big. Such a large tip angle is based on the reason that lead processing is easy.

[0006]

However, according to the prior art, when the lead 7 is soldered to the SBD chip, the solder layer 6a (or 6b) climbs up to near the base P of the tapered surface S of the lead 7, The thickness of the solder layer directly under the lead (the part where the lead contacts the chip) is reduced,
Or the thickness of the solder layer 6a on the oxide film 3 at the end of the solder layer 6 increases. Therefore, the Schottky barrier is destroyed by the temperature expansion and contraction at the time of joining and the mechanical stress at the time of molding the molding resin, and the reverse voltage characteristic is deteriorated (chip crack).

In order to solve such a problem, it is conceivable to increase the thickness of the solder layer immediately below the leads by increasing the amount of the solder pile. However, in this case, the solder layer also becomes thicker at the chip termination (the interface between the oxide film 3 and the substrate 1), and the Schottky barrier is broken by thermal stress at the time of joining and mechanical stress at the time of molding resin molding. Reverse voltage characteristics deteriorate. For this reason, in the yield reduction and the reliability evaluation (thermal stress evaluation), the reverse voltage characteristics are defective and the cost is increased.

The present invention has been made in view of such circumstances. A chip having a diffusion layer and an electrode connected to the diffusion layer formed on a main surface of a substrate and a tip soldered to the chip main surface are provided. An inverted truncated-cone-shaped lead, and a tip angle between the tapered surface of the lead and the main surface of the substrate is 10 ° to 1 °.
By adopting the configuration of 8 °, the thickness of the solder layer immediately below the leads is increased, and the thickness of the solder at the chip end portion is reduced, so that chip cracks can be avoided and the yield and reliability can be improved. An object is to provide a low-cost lead-type semiconductor element.

Further, according to the present invention, a solder tablet is placed on at least one side of a chip having a diffusion layer and an electrode connected to the diffusion layer formed on the main surface of the substrate, and the solder tablet is melted to perform solder filling. After that, the tip angle between the tapered surface and the main surface of the substrate at the soldered portion of the chip is 10 °.
It is an object of the present invention to provide a method for manufacturing a lead-type semiconductor element in which the same effect as described above can be obtained by mounting a lead having a truncated conical shape having an angle of 18 ° to 18 °.

[0010]

According to a first aspect of the present invention, there is provided a chip in which a diffusion layer and an electrode connected to the diffusion layer are formed on a main surface of a substrate, and a tip soldered to the main surface of the chip has a conical tip. A lead-type semiconductor device comprising a trapezoidal lead, wherein a tip angle between a tapered surface of the lead and a main surface of the substrate is 10 ° to 18 °.

[0011] The second invention of the present application is a step of placing a solder tablet on at least one side of a chip having a diffusion layer and an electrode connected to the diffusion layer on the main surface of the substrate, and melting the solder tablet to form a solder. A step of mounting, and a step of mounting a truncated-cone-shaped lead having a tip angle of 10 ° to 18 ° between a tapered surface and a main surface of the substrate at a solder-filled portion of the chip, This is a method for manufacturing a lead-type semiconductor device.

In the present invention, the reason why the tip angle is defined as described above is that when the tip angle is less than 10 °, it is difficult to process the lead, and when the tip angle exceeds 18 °, the thickness of the solder layer immediately below the lead becomes thin. This is because the thickness of the solder layer on the oxide film is increased or chip cracks are easily caused.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead type semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS.

(1) First, the surface of the n-type Si substrate 11 is
A p-type diffusion layer 12a, 12b having a rectangular shape was formed by introducing a type impurity such as boron. Next, a frame-shaped oxide film 13 was formed on the substrate 11 so as to partially overlap the diffusion layers 12a and 12b. Next, a square-shaped electrode 14 is formed on the surface side of the substrate 11 so that an edge portion extends over the oxide film 13.
The SBD chip 15 was used. Thereafter, solder tablets 16a and 16b were arranged on both main surfaces of the SBD chip 15 (see FIG. 1A).

(2) Next, the tablets 16a, 16
b was melted to form solder layers 17a and 17b (FIG. 1B).
reference). Subsequently, as shown in FIG. 2, nickel-plated copper leads 18 having a truncated cone shape were mounted on both main surfaces of the SBD chip 15. In this mount, two leads 18 are arranged above and below the SBD chip 15 to sandwich the SBD chip.
The heat treatment was performed at 00 ° C. Here, the tip angle θ between the tapered surface S of the lead 18 and the main surface of the substrate is 10 ° to 18 °.
It is. At the time of mounting, the solder layers 17a, 17b
Crawled up along the tapered surface S of the lead 18 (see FIG. 1C). Although not shown, after that, a molding resin molding was performed to seal the SBD chip 15, the solder layers 17a and 17b, and part of the leads 18.

The lead type semiconductor device manufactured in this manner has a configuration in which the taper surface S of the lead 18 is mounted on the main surface of the SBD chip 15 so that the tip angle of the taper surface S with respect to the main surface of the substrate is 10 ° to 18 °. The solder layer 1
7a (or 7b) can be suppressed from climbing up to the vicinity of the root P of the tapered surface S of the lead 18. Therefore, the thickness of the solder layers 17a and 17b immediately below the leads can be made thicker as compared with the conventional one as shown in FIG.
It can be avoided that the thickness of the solder layer 17a on the oxide film 13 at the end of the first layer becomes large, and the deterioration of the reverse electrical characteristics in the test process can be extremely reduced.

Further, since the thickness of the solder layer immediately under the leads can be increased without increasing the amount of chip solder, the thickness of the solder layer at the end of the chip can be reduced. Therefore, thermal and mechanical stress can be greatly reduced.

As described above, the yield is greatly improved, and a decrease in reliability due to a heat cycle can be prevented. In fact, FIG. 3 shows the thickness distribution of the solder layer immediately under the leads of the conventional and lead semiconductor devices according to the present invention. From FIG. 3, it is clear that the semiconductor element of the present invention is distributed in a portion where the thickness of the solder layer is significantly larger than that of the conventional semiconductor element.

In the above embodiment, the case where the present invention is applied to an SBD diode has been described. However, the present invention is not limited to this and can be applied to all semiconductor devices having leads.

[0020]

As described above in detail, according to the lead type semiconductor device of the present invention, a chip having a diffusion layer and an electrode connected to the diffusion layer formed on the main surface of the substrate, and a chip soldered to the chip main surface. A tip having an inverted truncated cone-shaped lead;
The tip angle between the tapered surface of the lead and the main surface of the substrate is 1
By adopting a configuration of 0 ° to 18 °, the thickness of the solder layer immediately below the leads is increased, and the chip thickness can be avoided by reducing the thickness of the solder at the end of the chip, thereby improving the yield and reliability. And cost reduction.

According to the method of manufacturing a lead-type semiconductor device of the present invention, a solder tablet is placed on at least one side of a chip having a diffusion layer formed on a main surface of a substrate and electrodes connected to the diffusion layer. After the solder tablet is melted and solder piled up, by mounting a lead in the shape of a truncated cone with a tip angle of 10 ° to 18 ° formed between the tapered surface and the main surface of the substrate on the soldered portion of the chip, The same effect as described above can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a method of manufacturing a lead-type semiconductor device according to one embodiment of the present invention in the order of steps.

FIG. 2 is an explanatory diagram of a lead which is one configuration of the lead-type semiconductor element in FIG.

FIG. 3 is a distribution diagram showing a thickness of a solder layer immediately below a lead in a conventional lead type semiconductor device according to the present invention.

FIG. 4 is an explanatory view showing a conventional method for manufacturing a lead-type semiconductor element in the order of steps.

FIG. 5 is an explanatory diagram of a lead which is one configuration of the lead-type semiconductor element in FIG. 4C.

[Explanation of symbols]

 11: n-type Si chip, 12a, 12b: p-type diffusion layer, 13: oxide film, 14: electrode, 15: SBD chip, 16a, 16b: solder tablet, 17a, 17b: solder layer, 18: lead.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yoshiaki Inoue 647 Mobara, Mobara-shi, Chiba Prefecture Toshiba Components Corporation (72) Inventor Noriyuki Morioka 70 Minowa, Kimitsu-shi, Chiba Prefecture Toshiba Components Corporation

Claims (2)

[Claims] 1. A chip having a diffusion layer and an electrode connected to the diffusion layer on a main surface of a substrate, and a lead soldered to the main surface of the chip and having a truncated conical tip. 10 ° angle between the tapered surface and the main surface of the substrate
A lead-type semiconductor device, wherein the angle is set to 18 °. 2. A step of placing a solder tablet on at least one side of a chip having a diffusion layer and an electrode connected to the diffusion layer formed on the main surface of the substrate, and a step of melting the solder tablet to perform solder filling. The tip angle between the tapered surface and the main surface of the substrate in the solder-filled portion of the chip is 10 ° or more.
Mounting a lead having a shape of a truncated cone of 18 [deg.].