JP2002368131A - Automatic alignment method for active region and deep trench - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an automatic alignment method for active region and deep trench, with which alignment can be performed automatically and influence due to alignment errors can be avoided. SOLUTION: A first dielectric layer, deep trench, capacitor dielectric structure, embedded contact band, second dielectric layer, third dielectric layer and mask layer provided with first openings substantially facing a pair of adjacent deep trenches are formed successively on a semiconductor wafer, a second opening, which can be automatically positioned to each of adjacent deep trenches, is formed from the first opening by twice selective etchings and a shallow trench isolating region having no eccentricity due to alignment errors is formed from the second opening by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly, to an automatic alignment method between an active region and a deep trench suitable for manufacturing a trench type DRAM.

[0002]

2. Description of the Related Art Semiconductor parts having a high performance and a low price have been produced one after another due to the wide application of integrated circuits. Among them, DRA
M is indispensable for the IT industry.

[0003] While the degree of integration of integrated circuits is increasing,
The storage capacity of the DRAM has reached 64 MB or more than 256 MB. Therefore, in order to further increase the storage capacity of the DRAM and improve the access speed, the size of the storage cell and the transistor must be significantly reduced.

The technique of forming a three-dimensional capacitor is very useful for greatly reducing the area occupied by a capacitor on a semiconductor substrate, and is therefore used in a DRAM manufacturing process. For example, a DRAM having a storage capacity of 64 Mb or more generally incorporates a trench capacitor.

An important part of the trench DRAM manufacturing method lies in the formation of an electrical connection between the trench capacitor and the transistor. For example, as shown in FIG. 1, a buried contact zone (BS) is formed between the upper portion of the deep trench (DT) capacitor and the diffusion region of the transistor to electrically connect them. Since this contact band is formed at the bottom of the substrate, the space for forming the memory cell on the surface of the substrate is increased, and the storage capacity is further improved. In addition, since the contact band is formed before the substrate surface element is formed, damage to the substrate surface element during manufacturing can be avoided.

On the other hand, how to control the diffusion length and resistance of the buried contact zone is the most important in quality control of the internal wiring. The diffusion length varies depending on the width and thickness of the contact zone, and the width of the contact zone depends on the alignment between the active region and the deep trench. Therefore, in order to properly adjust the diffusion length of the buried contact zone and achieve good electrical connection, it is necessary to prevent the alignment error between the active region and the deep trench from affecting the width of the buried contact zone.

FIG. 2 is a plan view showing a local portion of the DRAM.
In FIG. 2, a deep trench (DT) 10, a gate conductive layer (GC) 12, an active region (AA) 14, and a bit line contact hole (CB) 16, that is, a plurality of deep trenches and an overlap between these deep trenches and the active region. The structure is shown. As shown in FIG. 2, when the alignment between the active region and the deep trench is performed accurately, the overlap width between the active region and the deep trench is defined as L. , L2, it becomes larger or smaller.

FIG. 3 is a sectional view taken along line XX of FIG. Here, reference numeral 22 denotes a shallow trench isolation region (ST
I) and 24 indicate buried contact zones (BS). As shown in FIG. 3, when there is an alignment error between the active region and the deep trench, the widths L1 and L2 of both buried contact zones 24 are different. Therefore, the electrical connection between the capacitor and the transistor is affected, and a short circuit may occur.

Therefore, the above-mentioned problem is solved and the trench type D
It is necessary to complement the RAM manufacturing method.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide an automatic alignment method of an active region and a deep trench which can automatically perform alignment and avoid the influence of an alignment error. Is to provide.

It is another object of the present invention to provide an automatic alignment method between an active region and a deep trench so as not to affect the buried contact band width when there is an alignment error between the active region and the deep trench. .

Still another object of the present invention is to provide a method for automatically aligning an active region with a deep trench, which can automatically align the active region with the deep trench in the longitudinal direction of the active region.

[0013]

SUMMARY OF THE INVENTION In general, according to the present invention, there is provided a method for automatically aligning an active region with a deep trench, comprising forming a buried connection layer, depositing a thick liner layer, and further etching the liner layer. Backing may form a sidewall on the inner wall above the deep trench), an opening that is automatically aligned with the deep trench by photolithography and two selective etches after forming a flat dielectric layer Is formed, and the substrate is anisotropically etched from the opening to form a shallow trench isolation region without bias due to an alignment error.

More specifically, the method for automatically aligning an active region and a deep trench according to the present invention comprises the steps of: (a) forming a first dielectric layer on a semiconductor substrate; and (b) Forming at least a pair of adjacent deep trenches in the substrate through the first dielectric layer; and (c) sequentially forming a capacitor structure and a buried contact zone in the deep trenches. (D) depositing a second dielectric layer uniformly and entirely on the first dielectric layer surface, the inner wall and the buried contact zone surface; and (e) a third dielectric layer on the second dielectric layer. Depositing (f)
Forming a mask layer in the third dielectric layer having a pattern of an active region and including a first opening substantially opposing an adjacent deep trench; and (g) exposing a surface of the second dielectric layer. Etching the third dielectric layer from the first opening to cause the second dielectric layer to be exposed;
Selectively etching said dielectric layer and said underlying first dielectric layer to automatically form a second opening aligned with said adjacent deep trench; and (i) said second opening.
Further etching the substrate and the deep trench from the opening to form a shallow trench in the deep trench;
(J) filling a fourth dielectric layer in the shallow trench to form a shallow trench isolation region.

Further, in order to carry out the selective etching, in the method of the present invention described above, the material of the second dielectric layer is the same as the material of the first dielectric layer but is the same as the material of the third dielectric layer. You may comprise so that it may differ. For example,
The material of the second and first dielectric layers is silicon nitride, and the material of the third dielectric layer is silicon oxide.

Further, in the method of the present invention described above,
In the case of the etching in the step (h), the etching selectivity of the second dielectric layer to the third dielectric layer is 2.5: 1 or more. In the case of the etching in the step (i), the etching of the substrate to the third dielectric layer is performed. Preferably, the selectivity is 2-3: 1.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of an embodiment of the present invention which achieves the above-mentioned objects and solves the problems of the related art will be described in detail with reference to the accompanying drawings.

The method of the present invention will be described with reference to FIGS. First, as shown in FIG. 4, a first dielectric layer 104 (for example, a silicon nitride layer) is formed on the surface of the semiconductor substrate 100. This first dielectric layer 104 is not shown,
Other dielectric layers, for example, an oxide layer may be included. In this embodiment, the dielectric layer 104 comprises an approximately 10 nm oxide layer and an approximately 200 nm silicon nitride layer formed on the oxide layer.

After forming the first dielectric layer 104 on the substrate surface, the substrate 1 is passed through the dielectric layer 104 by photolithography and etching (eg, reactive ion etching).
At 00, a pair of adjacent deep trenches 102 are formed. It is assumed that only one pair of trenches 102 is formed for convenience of description, but a plurality of pairs of trenches 102 may be formed.

Next, a thin dielectric layer 106 is formed as a capacitor dielectric film (ie, a capacitor structure) in the deep trench 102 (the inner wall and the bottom surface). The dielectric layer 106 may be formed, for example, by a thermal oxidation method or a chemical vapor deposition (CV) method.
D) method. The thickness of the dielectric layer 106 is 5-10n
m. The material of the dielectric layer 106 is, for example, any one of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

Next, the first trench 108 is filled with a first conductive layer 108 (eg, made of N ⁺ doped polycrystalline silicon or other electrically conductive material). Thereafter, the dielectric layer 106 and the first conductive layer 108 are etched back to expose the upper half of the deep trench 102.

Next, as shown in FIG.
An annular insulating layer 110 is formed on the inner wall of the upper half portion of the second.
This annular insulating layer 110 is usually an oxide layer or another insulating material layer. As a forming method, a thermal oxidation method can be used. Alternatively, the annular insulating layer 110 may be formed by performing upper anisotropic etching deposited by a CVD method. In this embodiment, the thickness of the annular insulating layer 110 is 5
It is 0-100 nm.

Next, as shown in FIG. 6, the second conductive layer 112 is further filled in the deep trench 102 and the surface of the second conductive layer 112 is dry-etched so as to be recessed into the substrate 100. Etch back by law. Usually, the material of the second conductive layer 112 is the same as that of the first conductive layer, for example, both are doped polycrystalline silicon.

Next, as shown in FIG.
The annular insulating layer 110 is partially removed by etching with hydrofluoric acid or another etching method so that the surface of the second conductive layer 112 is lower than the surface of the second conductive layer 112.

Next, as shown in FIG. 8, the second conductive layer 1
12 so as to cover the upper part of the annular insulating layer 110.
Is deposited in the deep trench 102. After the deposition, first, a flattening process is performed by a chemical mechanical polishing (CMP) method, and then a dry etching is performed so that the surface thereof is recessed into the deep trench. The third conductive layer 114 thus formed is a buried contact zone.

After the formation of the buried zones, the main steps according to the method of the invention are performed as follows.

First, as shown in FIG. 9, the first dielectric layer 1
04 and inner wall of deep trench 102 and buried contact zone 11
At 4 a second dielectric layer 116 is deposited uniformly and entirely. In the present embodiment, the material of the second dielectric layer 116 and the material of the first dielectric layer 104 thereunder are preferably the same, for example, both are preferably silicon nitride. Also,
The thickness of the second dielectric layer 116 may be 30-50. In the present embodiment, the second dielectric layer 116 is
As a stop layer when etching the dielectric layer (to be described later), and an opening automatically aligned with the deep trench is formed. After depositing the second dielectric layer 116, the second dielectric layer 116 may be further etched back by an anisotropic etching method so that only a portion (referred to as a sidewall) corresponding to the inner wall of the deep trench 102 is left.

In FIG. 9, the left side of the broken line is an array area 200 of the element, and the right side is a peripheral circuit area 300.

Next, as shown in FIG. 10, a third dielectric layer 118 is deposited on the second dielectric layer 116. Here, it is better to deposit the third dielectric layer 118 thickly so as not to be recessed above the deep trench 102. Although the thickness is appropriately adjusted based on the etching conditions in the subsequent steps, the thickness is about 150 to 350 nm. In the present invention, the material of the third dielectric layer 118 is different from the material of the second dielectric layer 116 in order to perform selective etching. For example, the second and first
When both materials of the dielectric layers 116 and 104 are silicon nitride, the material of the third dielectric layer 118 is silicon oxide. In this embodiment, the material of the third dielectric layer 118 is borosilicate glass (BSG).

Next, as shown in FIG. 10, a mask layer 120 (for example, a photoresist mask) is formed on the third dielectric layer 118. Note that, in order to improve the resolution in the photolithography process, the third
An anti-reflection layer (not shown) may be formed on the dielectric layer 118.

Next, an active region pattern is defined in the photoresist layer 120 by photolithography. Among them, an opening 122 (first opening) substantially facing the adjacent deep trenches 102 is formed. Similarly, the photoresist mask 12 in the peripheral circuit 300 is
An opening 124 substantially equal to the opening 122 is also formed at 0.
Openings 122 are used to define shallow trench isolation (STI) regions in adjacent deep trenches 102.

Note that the opening 122 is not aligned with the central region of both deep trenches because there is an alignment error in FIG. (Conventionally, when such an alignment error exists, a shallow trench as shown by a broken line in the figure is formed and a circuit short circuit occurs.) Next, a shallow trench is formed. In this case, the mask layer 120
In contrast to the conventional method of forming a shallow trench by etching from the opening 122 (first opening) after defining a pattern in the present invention, the present invention employs the first and second etching steps to form the central region of the deep trench. An opening (second opening) that is automatically aligned is formed, and a shallow trench is formed from the second opening.

FIG. 11 shows the first etching step described above.
FIG. Exposing the surface of the second dielectric layer 116
The third dielectric layer 118 from the openings 122 and 124
To run. That is, etching is performed until the etching end point is detected.
To run. Here, the material of the third dielectric layer 118 is an oxide silicon.
In the case of recon, a fluorocarbon (for example, C₄F ₈
Or C₅F₈) As an etching seed and CO, A
r, O₂(<5%) gas is also used. I also mentioned earlier
An anti-reflection layer such as an organic reflection layer
When an anti-reflection layer is formed, first, the anti-reflection layer
₂/ O₂Or N ₂/ H₂50 with mixed gas by
Etching must be performed at a bias voltage of 0 V or less
There is.

FIG. 12 is a diagram showing the stage of the second etching described above. First, the photoresist layer 120 is removed. Then, the remaining third is exposed so as to expose the substrate surface.
The second dielectric layer 118 exposed as a hard mask
Of the dielectric layer 116 and the underlying first dielectric layer 104 are selectively etched. In the case of this etching, it is preferable that the etching selectivity of the second dielectric layer 116 (or the first dielectric layer 104) to the third dielectric layer 118 be 2.5: 1 or more. In order to obtain such an etching selectivity, for example, the second dielectric layer 116 and the first dielectric layer 10
4 is silicon nitride, and the third dielectric layer 11
When the material of 8 is silicon oxide, a fluorinated hydrocarbon (eg, CHF ₃ , CH ₃ F or CH ₂ F ₂ ) is used as an etching seed, and a gas such as CO, Ar, O ₂ (<5%) is also used. As a result, the opening 126 (the second
Opening) was formed. The opening 126 is formed between the first and second dielectric layers 1 located between the adjacent deep trenches 102.
04 and 116 are removed, the opening 126 can still be automatically aligned with the central region of both deep trenches 102 despite the large deviation of the opening 122 due to the alignment error described above. That is,
Automatic alignment is possible.

Next, as shown in FIG. 13, the substrate and the deep trench 102 are further anisotropically etched from the opening 126 to form a shallow trench 128. Similarly, the shallow trench 130 is formed in the peripheral circuit region 300 by etching. In this case, the etching selectivity of the substrate to the third dielectric layer is preferably 2-3: 1. For example, when the material of the third dielectric layer 118 is silicon oxide and the substrate is a silicon substrate, Cl and HBr may be used as etching species. If the etching selectivity of silicon to silicon oxide is too large during etching, projections may be formed on the annular oxide layer 110. In this case, the extra annular oxide layer is removed by etching to increase the etching selectivity of silicon oxide to silicon, or the extra oxide layer 110 is removed by wet etching.
Since the remaining third dielectric layer 118 serves as a hard mask when etching the shallow trench, the thickness of the third dielectric layer 118 is reduced until all the etching on the silicon substrate is completed. It must be set so that it is still retained.

Next, as shown in FIG. 14, the remaining third dielectric layer 118 is removed by wet etching. Thereafter, a fourth dielectric layer is filled in the shallow trench 128 to form a shallow trench isolation region 132. The fourth dielectric layer forming the shallow trench isolation region 132 is usually an oxide layer. Specifically, for example, the first dielectric layer 10 is first filled with an oxide layer into the shallow trenches 128 and 130 by high density plasma chemical vapor deposition (HDPCVD).
Then, the same oxide layer is deposited on 4 and the entire surface is flattened by the CMP method using the first dielectric layer 104 as a polishing stopper layer to remove an extra oxide layer other than the shallow trench. Thus, a shallow trench isolation region 132 is formed. At the same time, the region 13 is also formed in the shallow trench 130 of the peripheral circuit region 300.
4 is formed.

Finally, the remaining first dielectric layer 104 is removed by a wet etching method. Thus, the definition of the shallow trench isolation region and the active region is completed (see FIG. 15).

Although the present invention has been presented as in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications within the spirit and scope of the present invention. Therefore, the scope of the present invention is in accordance with the appended claims.

[0039]

As described above, according to the production method of the present invention,
Even if there is an alignment error between the active region and the deep trench (see FIG. 10), the shallow trench isolation region can still be automatically aligned with the deep trench isolation region (see FIG. 15), i.e., active region and deep trench isolation. The alignment of the trench is performed automatically. Therefore, the size of the buried contact zone is not affected by the alignment error.

[Brief description of the drawings]

FIG. 1 is a diagram showing a unit configuration of a DRAM having a buried contact band.

FIG. 2 is a plan view showing a local portion of a DRAM.

FIG. 3 is a view showing a cross section taken along line XX of FIG. 2;

FIG. 4 is a cross-sectional view illustrating a first part of an automatic alignment method between an active region and a deep trench according to an embodiment of the present invention;

FIG. 5 is a view showing a step that follows the step shown in FIG. 4;

FIG. 6 is a view showing a step that follows the step shown in FIG. 5;

FIG. 7 is a view showing a step that follows the step shown in FIG. 6;

FIG. 8 is a view showing a step that follows the step shown in FIG. 7;

FIG. 9 is a view showing a step that follows the step shown in FIG. 8;

FIG. 10 is a view showing a step that follows the step shown in FIG. 9;

FIG. 11 is a view showing a step that follows the step shown in FIG. 10;

FIG. 12 is a view showing a step that follows the step shown in FIG. 11;

FIG. 13 is a view showing a step that follows the step shown in FIG. 12;

FIG. 14 is a view showing a step that follows the step shown in FIG. 13;

FIG. 15 is a view showing a step that follows the step shown in FIG. 14;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor substrate 102 deep trench 104 first dielectric layer 106 capacitor dielectric layer 108 first conductive layer 110 annular insulating layer 112 second conductive layer 114 third conductive layer 116 second dielectric layer 118 third dielectric layer Reference Signs List 120 mask layer 122, 124, 126, 128, 130 opening 132, 134 fourth dielectric layer 200 array area 300 peripheral circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F083 AD17 LA16 NA01 PR29 PR39 PR39 PR40

Claims (15)

[Claims] 1. A method for aligning an active region with a deep trench, comprising: (a) forming a first dielectric layer in a semiconductor substrate; and (b) at least one pair of adjacent dielectrics in the substrate through the first dielectric layer. Forming a matching deep trench; and (c) sequentially forming a capacitor structure and a buried contact zone in the deep trench. (D) depositing a second dielectric layer uniformly and entirely on the surface of the first dielectric layer, the inner wall and the surface of the buried contact zone; and (e) a third dielectric layer on the second dielectric layer. (F) forming a mask layer in the third dielectric layer having an active region pattern and including a first opening substantially opposite to an adjacent deep trench; and (g) forming a mask layer in the third dielectric layer. Etching the third dielectric layer through the first opening to expose the surface of the second dielectric layer; and (h) exposing the second dielectric layer and the underlying second dielectric layer. Selectively etching the one dielectric layer to form a second opening that is automatically aligned with the adjacent deep trench; and (i) further etching the substrate and the deep trench from the second opening. Forming a shallow trench in a deep trench , (J) the shallow fourth active region and depth automatic alignment method of a trench of a dielectric layer filling forming a shallow trench isolation region in the trench. 2. Between the steps (d) and (e),
2. The method of claim 1, further comprising etching back the second dielectric layer to form a sidewall on the inner wall of the deep trench. 3. Between step (e) and step (f),
3. The method of claim 1, further comprising forming an anti-reflection layer on the third dielectric layer. 4. Between step (g) and step (h),
2. The method of claim 1, further comprising the step of removing the mask layer. 5. Between step (i) and step (j),
2. The method of claim 1, further comprising the step of removing the remaining third dielectric layer. 6. After the step (j), the residual first
2. The method of claim 1, further comprising the step of removing the dielectric layer. 7. The material of the second dielectric layer is the same as the material of the first dielectric layer but different from the material of the third dielectric layer, and the etching in the step (i) uses selective etching. 2. The method of claim 1, wherein the active region is aligned with the deep trench. 8. The material of the second and first dielectric layers is silicon nitride, the material of the third dielectric layer is silicon oxide, and the mask layer and the fourth dielectric layer are each a photoresist. A step of removing the photoresist layer between the steps (g) and (h), and the third step between the steps (i) and (j).
8. The method of claim 7, further comprising the step of removing said dielectric layer. 9. The method according to claim 7, wherein in the selective etching in the step (h), an etching selectivity of the second dielectric layer to the third dielectric layer is 2.5: 1 or more. 4. The method for automatically aligning an active region and a deep trench according to 1. 10. In the selective etching in the step (i), the etching selectivity of the substrate to the third dielectric layer is 2
9. The automatic alignment method between an active region and a deep trench according to claim 7, wherein the ratio is -3: 1. 11. The method of claim 8, wherein in the etching in the step (g), fluorocarbon is used as an etching species. 12. The method of claim 11, wherein the etching in step (g) uses C ₄ F ₈ or C ₅ F ₈ as an etching species. 13. The method of claim 9, wherein the selective etching in the step (h) uses a fluorocarbon as an etching species. 14. The method of claim 13, wherein the selective etching in the step (h) uses CHF ₃ , CH ₃ F or CH ₂ F ₂ as an etching species. Alignment method. 15. The method of claim 10, wherein in the selective etching in step (i), Cl and HBr are used as etching species.