JP2002368002A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral hetero bipolar transistor that is formed on an SOI substrate, has a small amount of parasitic capacitance and resistance, and can be operated at high speed. SOLUTION: After an element forming groove is formed at the center of an island-shaped SOI layer, an N<-> type diffusion layer used as a collector and a p<+> type diffusion layer used as an outside base are formed while the groove is held between the layers. Then, after an SiGe layer is formed for the inside base at the sidewall section of the element forming groove, an N<+> type polysilicon film is formed for the emitter so that the groove is buried.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comprising a lateral bipolar transistor and a method for manufacturing the same, and more particularly to a method for manufacturing a heterostructure such as Si / SiGe formed on an insulating substrate such as SOI (Silicon on Insulator). It is related to what was used.

[0002]

2. Description of the Related Art In recent years, as the performance and miniaturization of mobile communication devices have advanced, semiconductor devices mounted on communication devices have been required to operate at higher speed with lower power consumption. As one means for satisfying such requirements, a BiCMOS type semiconductor device mounted on an SOI substrate has been proposed.

This semiconductor device has a CMO on an SOI substrate.
By forming a bipolar transistor with S, excellent characteristics such as low operating voltage, complete isolation between elements, and reduction of parasitic capacitance are realized. In addition, crosstalk between an analog circuit and a digital circuit poses a problem in a transmission / reception unit of a communication device. However, by using an SOI substrate, a significant reduction in crosstalk can be expected as compared with the related art.

On the other hand, an element capable of operating in a higher frequency band, which has been considered difficult by the conventional technology using a silicon process, is Si / SiGe or Si / Si.
A hetero bipolar transistor using a hetero structure such as GeC has been put to practical use. In this device, by using a heterostructure in which the band gap of the base is smaller than the band gap of the emitter, reverse injection of carriers from the base to the emitter can be suppressed. There are advantages over conventional silicon bipolar transistors, such as being smaller.

However, in the above-described BiCMOS type semiconductor device, if a bipolar transistor is to be formed on an SOI substrate, the SOI layer must be thickened to some extent in a vertical structure suitable for high-speed operation. On the other hand, CMO
As for S, it is necessary to reduce the thickness of the SOI layer in order to operate at high speed and to suppress leakage current. Then, thin SO
If a bipolar transistor can be formed using the I layer, the manufacturing process can be greatly simplified, but a lateral bipolar transistor is promising as a means for realizing it. In addition, there is a report that the use of the horizontal type reduces parasitic resistance and is advantageous for high-speed operation.
As an example of such an attempt, T.S. There is a report by Shino et al. (IEDM98).

Hereinafter, such a lateral bipolar transistor will be described with reference to the drawings. FIG. 4 is a structural view showing a conventional lateral bipolar transistor. In FIG. 4, 1000 is a silicon layer (Si substrate), 1001 is a BOX (Buried Oxide) layer, 1002
Is a collector, 1004 is an internal base, 1005 is an emitter, 1006 is an external base, and 1099 is an SOI layer.

As shown in FIG. 4, a horizontal bipolar transistor is formed on an SOI substrate including a BOX layer 1001 made of a silicon oxide film and an SOI layer 1099 made of silicon. By using the SOI substrate, the parasitic capacitance of the element can be reduced. The thickness of the SOI layer 1099 is 0.1 μm. Internal base 1004 is boron P
It is connected to two external bases 1006 which are heavily doped and heavily doped with boron. The emitter 1005 and the collector 1002 are provided in a direction perpendicular to a line connecting the two external bases 1006, and are formed so as to be in contact with the internal base 1004. The emitter 1005 is heavily N-type doped with arsenic. The collector 1002 is N-type doped with arsenic, but the portion near the internal base 1004 has a low concentration in order to increase the breakdown voltage, and has a retrograde structure in which the concentration increases as the distance from the base increases. The overall plan shape is a cross so that the parasitic capacitance between the electrodes is reduced. With such a lateral bipolar transistor, a maximum oscillation frequency fmax of 31 GHz is realized.

Next, a method of manufacturing the above-mentioned lateral bipolar transistor will be described with reference to the drawings. 5 and 6 are perspective views showing a manufacturing process of a conventional lateral bipolar transistor. 5 and 6, 11
00 is a silicon layer, 1101 is a BOX layer, 1102 is a collector, 1104 is an internal base, 1105 is an emitter,
1106 is an external base, 1107 is an N ⁻ type diffusion region, 1
110 is a Si ₃ N ₄ mask, 1111 is TEOS (Tetra
Ethyl Ortho Silicate) mask.

First, as shown in FIG. 5A, phosphorus is implanted into the SOI layer 1099 to form an N ⁻ type diffusion region 1107 which becomes an active region of a lateral bipolar transistor. After that, a SiO ₂ film and a Si ₃ N ₄ film are formed thereon, and then a dock-bone type resist mask 1108 is provided. Using this as a mask, boron is dosed at 4E15 cm.
P ⁺ type diffusion region 1109 which becomes an external base by implanting with ^-2
To form

Next, as shown in FIG. 5B, the nitride film is etched and side-etched using the resist mask 1108 to form a resist mask 1108.
An Si ₃ N ₄ mask 1110 is formed with an offset of about 0.2 μm from the end.

Next, as shown in FIG. 5C, after removing the resist mask 1108, a TEOS film is formed thereon. Thereafter, a dock-bone type resist mask (not shown) is crossed with respect to the Si ₃ N ₄ mask 1110.
And a TEOS mask 1111 is formed in the base formation region. Thereafter, a resist mask (not shown) is provided in the collector formation region, and boron is selectively doped at a dose of 1E.
The implantation is performed at 14 cm ^-2 and an acceleration energy of 25 keV.

Next, as shown in FIG. 6D, the implanted boron is diffused laterally to form an internal base 1104. Here, the width of the internal base is the TEOS mask 11
It is determined by the diffusion distance of boron diffused from the end of the eleventh region.

Finally, portions serving as an emitter, a collector, and an external base are mesa-etched using a Si ₃ N ₄ mask 1110 and a TEOS mask 1111. Thereafter, arsenic is implanted into the emitter 1105 and the collector 1102 at a dose of 1E15 cm ⁻² and an acceleration energy of 120 keV, respectively.
And a dose of 1E16 cm ^-2 and an acceleration energy of 65 ke
It is formed by implantation with V.

As described above, the parasitic capacitance is small and f
A lateral bipolar transistor having a high max and capable of high-speed operation can be formed.

[0015]

However, the above conventional example has the following problems.

First, since the width of the internal base 1104 is determined by the diffusion of boron, a desired steep and uniform impurity distribution cannot be obtained. Also, since the emitter 1105 also forms an emitter-base junction by arsenic diffusion, it is difficult to form a steep junction. Therefore,
There is a problem that the current amplification factor and the cutoff frequency are easily reduced, and it is difficult to obtain stable electric characteristics without variation.

Second, the structure is such that the parasitic capacitance of the element is minimized.
The semiconductor material of 104 and the collector 1102 is the same silicon, and the operation speed is limited. That is, when the impurity concentration of the internal base 1104 is increased to lower the base resistance, the internal base 1104 causes the emitter 110
Holes are reversely injected on the fifth side, which lowers the current amplification factor. Conversely, when the impurity concentration is reduced, there is a problem that the base resistance increases and the operation speed decreases.

The present invention solves the above problems,
It is an object of the present invention to provide a semiconductor device including a lateral hetero bipolar transistor formed on an SOI substrate and having a small parasitic capacitance and a small parasitic resistance and capable of operating at high speed, and a method for manufacturing the same.

[0019]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device comprising a lateral bipolar transistor formed on an SOI substrate, which is formed on a buried insulating film, Island-shaped first
Semiconductor layer, an isolation groove formed around the first semiconductor layer, an isolation layer formed so as to embed a dielectric film inside the isolation groove, and an isolation layer formed at the center of the first semiconductor layer. An element forming groove, a first diffusion layer of a first conductivity type which is formed between the element forming groove and the isolation groove in a predetermined region of the first semiconductor layer and serves as a collector, and a first diffusion layer outside the predetermined region. On the opposite side of the diffusion layer, a second conductivity type second diffusion layer formed between the element formation groove and the isolation groove and serving as an external base, and a first diffusion layer formed on the side wall of the element formation groove Forming a PN junction in contact with the second conductive type second semiconductor layer serving as an internal base;
A first PN junction formed to fill the inside of the element forming groove and in contact with the second semiconductor layer to form a PN junction and to be an emitter
A third semiconductor layer of a conductivity type.

In the above-described semiconductor device, the first buried conductor layer formed on one side of the separation layer in contact with the first diffusion layer and serving as a collector electrode, and the first diffusion layer in contact with the first buried conductor layer A third diffusion layer of the first conductivity type formed on the side wall of the layer and serving as a collector contact layer; and a second buried conductor layer formed on one side of a separation layer in contact with the second diffusion layer and serving as a base electrode And a fourth diffusion layer of the second conductivity type formed on the side wall of the second diffusion layer in contact with the second buried conductor layer and serving as a base contact layer.

In the above semiconductor device, the first semiconductor layer is silicon, the second semiconductor layer is an alloy of silicon and germanium or an alloy of silicon and germanium containing carbon, and the third semiconductor layer is silicon. Preferably it is polysilicon.

Next, according to a method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device including a lateral bipolar transistor formed on an SOI substrate, the first semiconductor layer formed on the buried insulating film is removed. A step A of forming an isolation groove for electrical isolation, an element formation groove in the center of the first semiconductor layer, and a step B of forming an isolation layer by embedding a dielectric film inside the isolation groove; A step C of forming a first diffusion layer of a first conductivity type serving as a collector between an element formation groove and an isolation groove in a predetermined region of the first semiconductor layer; and forming a first diffusion layer of the first diffusion layer outside the predetermined region. On the other side, a step D of forming a second conductive type second diffusion layer serving as an external base between the element formation groove and the separation groove, and etching only the dielectric film embedded in the element formation groove Step E of exposing the first semiconductor layer; Step of exposing the first semiconductor layer is etched smooth semiconductor surface exposed to the interior of Narumizo F
And a UH on the semiconductor surface exposed inside the device forming groove.
The second conductive type second base which becomes an internal base by the V-CVD method
G for selectively forming a semiconductor layer of the first type, and H for forming a third semiconductor layer of the first conductivity type serving as an emitter on the second semiconductor layer so as to bury the inside of the element formation groove. And characterized in that:

In the above-described method for manufacturing a semiconductor device, the dielectric film embedded in the separation layer in contact with the first diffusion layer and the second diffusion layer is etched only on one side in contact with each of the diffusion layers to form a contact groove. Step I of forming
A step J of forming a third diffusion layer of the first conductivity type serving as a collector contact layer on the side wall of the first diffusion layer exposed inside the contact groove; and a second diffusion layer exposed inside the contact groove. Forming a fourth diffusion layer of the second conductivity type to be a base contact layer on the side wall of the layer; and forming the third diffusion layer and the fourth diffusion layer so as to bury the inside of the contact groove.
And a step L of forming a first buried conductor layer to be a collector electrode and a second buried conductor layer to be a base electrode so as to be in contact with the respective diffusion layers.

In the above-described method for manufacturing a semiconductor device, the first semiconductor layer is made of silicon, and the second semiconductor layer is made of an alloy of silicon and germanium or an alloy of silicon and germanium containing carbon. Preferably, the semiconductor layer is polysilicon.

According to the above configuration, a steep and uniform impurity distribution can be obtained in the internal base, and a steep junction can be formed in the emitter-base junction. Therefore, the current amplification factor and the cutoff frequency can be prevented from lowering and stable without any variation. The obtained electrical characteristics can be obtained.

Also, by forming a heterojunction, the reverse injection of carriers from the internal base to the emitter is suppressed, so that the current amplification factor is prevented from lowering and the base resistance is reduced by increasing the impurity concentration of the internal base. it can.
Furthermore, each diffusion layer is arranged in one direction of the SOI layer, and the element area is reduced, so that the parasitic capacitance can be reduced.

Therefore, according to the present invention, after forming an element forming groove at the center of an island-like SOI layer by a simple manufacturing process,
An N ⁻ -type diffusion layer serving as a collector and a P-type diffusion layer serving as an external base are formed on one side so as to sandwich the groove,
Next, a P-type S serving as an internal base is formed on the side wall of the element forming groove.
After the iGe layer is formed, an N ⁺ -type polysilicon film serving as an emitter is formed so as to fill the trench, so that the parasitic device has a small parasitic capacitance and a small parasitic resistance and can be operated at high speed. Can be realized.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A and 1B show a semiconductor device including a lateral hetero bipolar transistor formed on an SOI substrate according to the present embodiment, and FIG.
Is a plan view, and (b) is a cross-sectional view taken along the line XX ′ of the plan view. In FIG. 1, a field film, a contact hole, and a wiring formed in a final step of the semiconductor device are not shown.

In FIG. 1, 1 is a BOX layer made of a buried insulating film, and 2 is an SOI made of a silicon layer in an element region.
Layer 3, SiO ₂ film, 4 Si ₃ N ₄ film, 5 an isolation layer made of a dielectric film, 6 an N ⁻ type diffusion layer serving as a collector, 7 a P ⁺ type diffusion layer serving as an external base, 8 Is a P-type SiGe layer serving as an internal base, 9 is an N ⁺ -type polysilicon film serving as an emitter, 10 is an N ⁺ -type diffusion layer serving as a collector contact layer, 11 is a P ⁺ -type diffusion layer serving as a base contact layer, 1
2 is a buried metal layer, 25 is an isolation groove, 26 is an element formation groove, and 27 is a contact groove.

As shown in FIG. 1, the lateral hetero bipolar transistor is formed on an SOI layer 2 provided on a BOX layer 1. By using the SOI substrate in this manner, the parasitic capacitance of the element is reduced. P-type SiGe is formed on the side wall of the element forming groove 26 formed in the center of the island-shaped SOI layer 2.
The internal base of layer 8 is formed. An outer base of the high-concentration P ⁺ -type diffusion layer 7 is formed in contact with one side of the inner base, and is connected to a base contact layer of the P ⁺ -type diffusion layer 11 formed on the side wall of the isolation groove 25. I have. Also, as embedded in the element forming groove 26,
An emitter of an N ⁺ -type polysilicon film 9 forming a PN junction with the P-type SiGe layer 8 is formed.

Next, an element forming groove 2 is formed on the side opposite to the external base.
6, a collector of the N ⁻ -type diffusion layer 6 forming a PN junction with the P-type SiGe layer 8 is formed, and a collector contact layer of the N ⁺ -type diffusion layer 10 formed on the side wall of the isolation groove 25 is formed. Connected to Further, the separation layers 5 in contact with the N ⁺ type diffusion layer 10 and the P ⁺
The contact groove 27 is formed on one side, and the buried metal layer 12 is formed inside the contact groove 27.

Next, a method for manufacturing the above semiconductor device will be described with reference to the drawings. 2 and 3 are cross-sectional views illustrating a process for manufacturing a semiconductor device including a lateral hetero-bipolar transistor formed on an SOI substrate according to the present embodiment.

First, as shown in FIG. 2A, an SOI having an SOI layer 2 having a thickness of about 0.1 μm on a BOX layer 1 is formed.
After forming a SiO ₂ film 3 of about 10 nm on the substrate,
Depositing the Si ₃ N ₄ film 4 to 300 nm. Subsequently, a separation groove 25 is formed by a known photolithography and etching technique. At this time, the element forming groove 2 is formed at the center of the island-shaped SOI layer 2.
6 is also formed at the same time. Then, TEO consisting of a dielectric film
An S film is deposited and planarized by a CMP (Chemical Mechanical Polishing) or an etch-back method to form a separation layer 5. At this time, the TEOS film is also buried in the element forming groove 26.

Next, as shown in FIG. 2B, a first resist mask 21 having an opening extending from the element formation groove 26 to the separation groove 25 is formed, and phosphorus or arsenic is applied to the collector region by an accelerating voltage. About 10 to 80 keV, dose 1E
The N ⁻ type diffusion layer 6 is formed by ion implantation at about 13 to 1E14 cm ⁻² .

Next, as shown in FIG. 2C, a second resist mask 22 having an opening extending from the element formation groove 26 to the separation groove 25 is formed, and boron is applied to the external base region at an acceleration voltage of 10 keV. Degree, dose 1E14 to 1E15
Ion implantation is performed at about cm ⁻² , and the P ⁺ -type diffusion layer 7 is formed so as to sandwich the element forming groove 26 on the opposite side of the N ⁻ -type diffusion layer 6.

Next, as shown in FIG.
Forming a resist mask (not shown) so as to cover
Only the TEOS film embedded in the element forming groove 26 is etched by a known etching technique. Thereafter, the exposed SOI layer 2 is etched by a known etching technique to form a smooth silicon surface.

Next, as shown in FIG.
CVD (Ultra High Vacuum-Chemical Vapor Depositi
on), the N ⁻ exposed inside the element forming groove 26 is formed.
A P-type SiGe layer 8 having a thickness of 50 to 200 nm and a boron concentration of about 1 to 5E18 cm ^-3 is selectively epitaxially grown only on the side wall portions of the P-type diffusion layer 6 and the P ⁺ -type diffusion layer 7 to form an internal base. . Subsequently, after depositing doped polysilicon having a phosphorus concentration of about 1 to 7E20 cm ^-3 , planarization is performed by CMP or etch-back, and N ⁺ -type polysilicon serving as an emitter is buried in the element forming groove 26 so as to become an emitter. A film 9 is formed.

Next, as shown in FIG. 3F, the TEOS film embedded in the separation layer 5 in contact with the N ⁻ type diffusion layer 6 and the P ⁺ type diffusion layer 7 is diffused by a known etching technique. The contact groove 27 is formed by etching only one side in contact with the layer. When a plurality of lateral bipolar transistors are arranged in a chain, when adjacent diffusion layers are of the same conductivity type, etching may be performed without leaving the TEOS film on the opposite side of the separation layer 5. Then, the N ^- type diffusion layer 6
A third resist mask 23 having an opening in a separation groove 25 in contact with is formed, and phosphorus or arsenic is applied to the exposed side walls of the N ⁻ type diffusion layer 6 at an acceleration voltage of about 10 keV and a dose of about 1E15 to 1E16 cm ^−2. N ⁺ type diffusion layer 1 to be a collector contact layer by performing ion implantation of 4 rotations
0 is formed.

Next, as shown in FIG. 3G, a fourth resist mask 24 having an opening in a separation groove 25 in contact with the P ⁺ type diffusion layer 7 is formed, and the exposed P ⁺ type diffusion layer is formed. 7 at an acceleration voltage of about 10 keV and a dose of 1
P ⁺ -type diffusion layers 11 serving as base contact layers are formed by ion implantation of about four times at E15 to 1E16 cm ^-2 . Subsequently, R at 850 to 1100 ° C. for 10 to 60 seconds
TA (Rapid Thermal Anneal) processing is performed to activate each diffusion layer formed by ion implantation.

Next, as shown in FIG. 3 (h), after a tungsten film is deposited by a sputtering method or the like so as to fill the inside of the contact groove 27, flattening is performed by CMP or etch back to obtain N ^+. A buried metal layer 12 in contact with the diffusion layer 10 and the P ⁺ diffusion layer 11 is formed. Finally, after depositing a field film 13 made of an insulating film, a contact hole and a wiring are formed by a known photolithography and etching technique to form a base electrode 14, an emitter electrode 15 and a collector electrode 1 made of a metal film.
6 is formed.

As described above, the internal base is UHV-CV
Since the P-type SiGe layer 8 is formed by epi growth using the D method, a steep and uniform impurity distribution can be obtained as compared with the conventional example. In addition, since the emitter is also formed of the N ⁺ type polysilicon film 9, the junction between the emitter and the base can be formed to be steeper than in the conventional example. Therefore, a decrease in the current amplification factor and cutoff frequency of the lateral heterobipolar transistor is prevented, and stable electrical characteristics without variation can be obtained. Even if the internal base is formed of a Si layer instead of the SiGe layer, a steep and uniform impurity distribution is similarly obtained in the internal base, and a steep junction between the emitter and the base can be formed.

Further, the emitter-base junction is formed in a hetero structure, and suppresses the reverse injection of carriers from the internal base to the emitter.
The base resistance can be reduced by increasing the impurity concentration of the internal base. Further, each diffusion layer is arranged in one direction of the SOI layer, and the element area is reduced as compared with the conventional example.
Parasitic capacitance can be reduced. Therefore, the parasitic capacitance and the parasitic resistance of the lateral hetero bipolar transistor can be reduced with a simple configuration, and high-speed operation can be realized.

In the above-described embodiment, among the bipolar transistors, an NPN transistor is particularly formed, but this may be a PNP transistor.

In the above embodiment, the internal base is formed of the SiGe layer.
It may be a mixed crystal semiconductor layer such as a SiC layer.

In the above embodiment, the buried metal layer is formed of a tungsten film, but may be a conductor film such as a polysilicon film or a metal silicide film.

[0046] Further, in the above embodiment, although the separation layer was formed by TEOS film, which is a SiO ₂ film, Si ₃ N
_It may be a dielectric film such as _four films.

Further, in the above embodiment, the collector and the external base are formed so as to face each other and sandwich the rectangular element forming groove.
It may be formed so as to surround three sides of the square.

In the above embodiment, the island-shaped SOI layer or the element forming groove is formed in a quadrilateral, but may be formed in an octagon, a circle, or the like.

[0049]

As is evident from the foregoing description, the present invention is a simple manufacturing process, after forming the element forming groove in the center of the island-shaped SOI layer, the collector to one so as to sandwich the groove N ^-
And a P-type diffusion layer serving as an external base on the other side, and then forming a P-type diffusion layer serving as an internal base on the side wall of the element forming groove.
After forming the SiGe layer, an N ⁺ -type polysilicon film serving as an emitter is formed so as to fill the trench, so that the parasitic capacitance and the resistance are small, and a semiconductor composed of a lateral hetero bipolar transistor capable of high-speed operation is provided. The device can be realized.

[Brief description of the drawings]

FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the present invention. FIG. 1B is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a structural view showing a conventional semiconductor device.

FIG. 5 is a perspective view showing a manufacturing process of a conventional semiconductor device.

FIG. 6 is a perspective view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 BOX layer 2 SOI layer 3 SiO ₂ film 4 Si ₃ N ₄ film 5 Separation layer 6 N ⁻ type diffusion layer 7 P ⁺ type diffusion layer 8 SiGe layer 9 N ⁺ type polysilicon film 10 N ⁺ type diffusion layer 11 P ⁺ Mold diffusion layer 12 buried metal layer 13 field film 14 base electrode 15 emitter electrode 16 collector electrode 21 first resist mask 22 second resist mask 23 third resist mask 24 fourth resist mask 25 separation groove 26 element formation groove 27 contact groove 1000 silicon layer 1001 BOX layer 1002 collector 1004 internal base 1005 emitter 1006 external base 1099 SOI layer 1100 silicon layer 1101 BOX layer 1102 collector 1104 internal base 1105 emitter 1106 external base 1107 N ^- type diffusion region 1108 resist Mask 1109 P ⁺ type diffusion region 1110 Si ₃ N ₄ mask 1111 TEOS mask

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 AA07 BB01 BB18 BB19 CC01 FF01 GG06 5F003 AP05 AZ03 BA96 BB01 BB04 BB06 BE01 BE07 BF03 BF06 BG03 BH06 BH99 BM01 BN01 BP11 BP22 BP33

Claims (6)

[Claims] 1. A semiconductor device comprising a lateral bipolar transistor formed on an SOI substrate, wherein an island-shaped first semiconductor layer is formed on a buried insulating film, and is formed around the first semiconductor layer. A separation groove formed so as to bury a dielectric film inside the separation groove; an element formation groove formed at the center of the first semiconductor layer; A first diffusion layer of a first conductivity type formed between the element forming groove and the isolation groove and serving as a collector in a predetermined region; and on the opposite side of the first diffusion layer outside the predetermined region, A second conductive type second diffusion layer formed between the element forming groove and the separation groove and serving as an external base; and a second diffusion layer formed on a side wall of the element forming groove and in contact with the first diffusion layer. Forming a PN junction and forming a second conductive type And a third semiconductor layer of the first conductivity type, which is formed so as to fill the inside of the element forming groove, is in contact with the second semiconductor layer, forms a PN junction, and serves as an emitter. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a first buried conductor layer formed on one side of the separation layer in contact with the first diffusion layer and serving as a collector electrode; and the first buried conductor. A third diffusion layer of a first conductivity type formed on a side wall of the first diffusion layer in contact with a layer and serving as a collector contact layer; formed on one side of the separation layer in contact with the second diffusion layer; A second buried conductor layer serving as a base electrode; a second conductive type fourth diffusion layer formed on a side wall of the second diffusion layer in contact with the second buried conductor layer and serving as a base contact layer; A semiconductor device, further comprising: 3. The semiconductor device according to claim 1, wherein the first semiconductor layer is silicon, and the second semiconductor layer is an alloy of silicon and germanium or an alloy of silicon and germanium containing carbon. Wherein the third semiconductor layer is made of polysilicon. 4. A method for manufacturing a semiconductor device comprising a lateral bipolar transistor formed on an SOI substrate, comprising: a separation groove for electrically separating a first semiconductor layer formed on a buried insulating film; A step A of forming an element forming groove at the center of the first semiconductor layer; a step B of forming an isolation layer by burying a dielectric film inside the isolation groove; and a predetermined region of the first semiconductor layer. A step C of forming a first diffusion layer of a first conductivity type which becomes a collector between the element formation groove and the separation groove; and, outside the predetermined region, on a side opposite to the first diffusion layer, Forming a second conductive type second diffusion layer serving as an external base between the element formation groove and the separation groove; and etching only the dielectric film embedded in the element formation groove. Exposing the first semiconductor layer E; a step F of etching the first semiconductor layer exposed inside the element formation groove to expose a smooth semiconductor surface; and F on the semiconductor surface exposed inside the element formation groove.
A step G of selectively forming a second semiconductor layer of a second conductivity type serving as an internal base by UHV-CVD, and a step of burying the inside of the element forming groove on the second semiconductor layer. Forming a third semiconductor layer of the first conductivity type to be an emitter. 5. The method for manufacturing a semiconductor device according to claim 4, wherein said dielectric film embedded in said separation layer in contact with said first diffusion layer and said second diffusion layer is formed as a respective diffusion layer. Forming a contact groove by etching only one side in contact with the first diffusion layer; forming a third diffusion layer of a first conductivity type serving as a collector contact layer on a side wall portion of the first diffusion layer exposed inside the contact groove; Forming a base contact layer on the side wall of the second diffusion layer exposed inside the contact groove;
Forming a diffusion layer of the third type;
Forming a first buried conductor layer serving as a collector electrode and a second buried conductor layer serving as a base electrode so as to be in contact with the first diffusion layer and the fourth diffusion layer, respectively.
And a method for manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the first semiconductor layer is silicon, and the second semiconductor layer is an alloy of silicon and germanium or silicon and germanium containing carbon. A method of manufacturing a semiconductor device, wherein the third semiconductor layer is polysilicon.