JP2002366445A5 - - Google Patents

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Publication number
JP2002366445A5
JP2002366445A5 JP2002121551A JP2002121551A JP2002366445A5 JP 2002366445 A5 JP2002366445 A5 JP 2002366445A5 JP 2002121551 A JP2002121551 A JP 2002121551A JP 2002121551 A JP2002121551 A JP 2002121551A JP 2002366445 A5 JP2002366445 A5 JP 2002366445A5
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JP
Japan
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data
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combining
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JP2002121551A
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English (en)
Japanese (ja)
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JP2002366445A (ja
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Priority claimed from US09/853,955 external-priority patent/US6948112B2/en
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Publication of JP2002366445A publication Critical patent/JP2002366445A/ja
Publication of JP2002366445A5 publication Critical patent/JP2002366445A5/ja
Withdrawn legal-status Critical Current

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JP2002121551A 2001-05-10 2002-04-24 コンピュータでバックワード・エラー・リカバリを実行するためのシステム Withdrawn JP2002366445A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/853,955 2001-05-10
US09/853,955 US6948112B2 (en) 2001-05-10 2001-05-10 System and method for performing backward error recovery in a computer

Publications (2)

Publication Number Publication Date
JP2002366445A JP2002366445A (ja) 2002-12-20
JP2002366445A5 true JP2002366445A5 (enExample) 2005-09-22

Family

ID=25317332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002121551A Withdrawn JP2002366445A (ja) 2001-05-10 2002-04-24 コンピュータでバックワード・エラー・リカバリを実行するためのシステム

Country Status (2)

Country Link
US (1) US6948112B2 (enExample)
JP (1) JP2002366445A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7440884B2 (en) * 2003-01-23 2008-10-21 Quickturn Design Systems, Inc. Memory rewind and reconstruction for hardware emulator
US7263649B2 (en) * 2004-08-09 2007-08-28 Phison Electronics Corporation Converting circuit for preventing wrong error correction codes from occurring due to an error correction rule during data reading operation
KR100632952B1 (ko) * 2004-09-30 2006-10-11 삼성전자주식회사 정전으로 인한 프로그램 페일의 유무를 판별할 수 있는방법 및 장치
DE102004059392B4 (de) * 2004-12-09 2015-09-10 Infineon Technologies Ag Verfahren zur Neubelegung eines Befehlsspeichers, Subsystem zur Durchführung eines derartigen Verfahrens, sowie Mikrokontroller
US8078910B1 (en) * 2008-12-15 2011-12-13 Open Invention Network, Llc Method and system for providing coordinated checkpointing to a group of independent computer applications
US7555424B2 (en) 2006-03-16 2009-06-30 Quickturn Design Systems, Inc. Method and apparatus for rewinding emulated memory circuits
US8549532B2 (en) * 2010-07-12 2013-10-01 International Business Machines Corporation Parallel checkpointing for migration of workload partitions
US8578214B2 (en) 2010-09-09 2013-11-05 International Business Machines Corporation Error handling in a virtualized operating system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573851A (en) * 1968-07-11 1971-04-06 Texas Instruments Inc Memory buffer for vector streaming
JPS59157887A (ja) 1983-02-28 1984-09-07 Hitachi Ltd 情報処理装置
US5230045A (en) 1986-11-12 1993-07-20 Xerox Corporation Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus
US4849978A (en) 1987-07-02 1989-07-18 International Business Machines Corporation Memory unit backup using checksum
US5446691A (en) 1994-03-15 1995-08-29 Shablamm! Computer Inc. Interleave technique for accessing digital memory
US5761695A (en) 1995-09-19 1998-06-02 Hitachi, Ltd. Cache memory control method and apparatus, and method and apparatus for controlling memory capable of interleave control

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