JP2002366120A - Display device, power circuit of display device, driving circuit of display device, driving method of display device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for voltage adjustment when a panel is incorporated and to maximize a contrast ratio. SOLUTION: The power circuit 500 of a display device having a pixel, where a pixel capacitor varying in optical density with an applied voltage and a switching element turning on when the applied voltage exceeds a threshold are connected in series, between a scanning line and a data line is equipped with a memory 522 which previously stores voltage data, a D/A converter 526 which converts the voltage data into a target voltage Vref on an analog basis, a voltage generating circuit 530 which generates a voltage +VS corresponding to the target voltage Vref, and an inverting circuit 540 which generates a voltage -VS by inverting the polarity of the voltage +VS. Then the power circuit 500 supplies the voltages ±VS as a select signal which forces the switching element to turn on irrelevantly to the voltage applied to the data line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, a power supply circuit of a display device, a drive circuit of a display device, a method of driving a display device, and an electronic apparatus, which do not require voltage adjustment individually required at an installation destination. About.

[0002]

2. Description of the Related Art In recent years, a display device which performs display by electro-optical change of an electro-optical material such as a liquid crystal has been developed using a cathode ray tube (C).
As a display device replacing (RT), it is widely used in various electronic devices and televisions. Such display devices can be classified according to the driving method and the like.
It can be broadly classified into a matrix type and a passive matrix type in which a pixel capacitance is driven without using a switching element.

[0003] Among them, in the former active matrix type, a thin film transistor (TFT: Thin Film Transistor) is further provided depending on the type of switching element.
r) and two-terminal switching elements such as thin film diodes (TFDs). The latter two-terminal switching elements can be classified into two types. Since the type used has no intersection of wiring on a single board,
It is advantageous in that short circuit failure between wirings does not occur in principle, that the film forming process and photolithography process can be shortened, and that it is suitable for low power consumption.

By the way, in a display device using a two-terminal type as a switching element, the voltage-concentration characteristics tend to be different for each individual due to variations during manufacturing and the like. For this reason, before actually using the display device, it is necessary to set a voltage optimized for the voltage-concentration characteristics for each display device. Therefore, a configuration having a semi-fixed volume or the like for voltage adjustment is generally widely used.

[0005]

However, it has been pointed out that the configuration having a semi-fixed volume for voltage adjustment has the following disadvantages. That is,
In such a configuration, since external components such as a semi-fixed volume are required, there have been problems in that the manufacturing process of the display device is complicated and the cost is high.
Particularly in recent years, display device manufacturers (panel manufacturers)
And the person who incorporates this display device as a display unit (assembly maker) are often different from each other due to various factors such as changes in the social situation in recent years and cost reduction, but the panel maker adjusts the semi-fixed volume. In this case, the adjusted semi-fixed volume may be out of order at the time of transportation to the assembly maker or at the stage of assembling. However, if the assembly maker adjusts the semi-fixed volume,
It has also been pointed out that the assembly process becomes too complicated.

[0006] The present invention has been made in view of such circumstances, and an object of the present invention is to eliminate the need for voltage adjustment when a display device is incorporated in an electronic device, thereby reducing the complexity of the process. It is an object of the present invention to provide a display device, a power supply circuit of the display device, a driving circuit of the display device, a driving method of the display device, and an electronic device which are prevented.

[0007]

In order to achieve the above object, in a display device according to the present invention, a pixel capacitor whose optical density changes according to an applied voltage between a scanning line and a data line is provided. A display device including a pixel in which a switching element that is turned on when an applied voltage becomes equal to or higher than a threshold value is connected in series, and for one scanning line, a pixel belonging to the one scanning line The selection voltage for turning on the switching element regardless of the voltage of the data line is changed to the non-conducting state for the other scanning lines, regardless of the voltage of the data line. A scanning line driving circuit that selects and supplies a non-selection voltage to be turned on, and turns on when a pixel capacitance of a pixel corresponding to one data line and a scanning line to which the selection voltage is supplied is to be turned on. Voltage A data line drive circuit for supplying the non-lighting voltage to the one data line when the off display state is to be provided, storage means for storing voltage data in advance, and voltage data stored in the storage means And a voltage generating circuit for generating the selected voltage and supplying the selected voltage to the scanning line driving circuit as the selection voltage. In this configuration, when the switching element is turned on, the optical density of the pixel capacitance is mainly determined by the selection voltage of the scanning line and the data voltage, but the selection voltage forces the switching element to be turned on. The optical density is, in fact,
It is determined by the voltage of the data line when the selection voltage is applied. In other words, the selection voltage has a characteristic of determining a reference when the optical density of the pixel capacitance changes, and the voltage of the data line is determined by how much from the reference,
It is a characteristic that defines whether to change the optical density.
According to this configuration, the selection voltage that determines the reference when the optical density of the pixel capacitor changes is defined by the voltage data stored in advance in the storage unit.
If the voltage data optimized for the voltage-density characteristics of the display device is stored after the manufacture of the display device, it is not necessary to adjust the voltage thereafter.

Here, in the present invention, it is preferable that the storage means is formed on an IC chip integrated with a part or all of the power generation circuit. According to this configuration, it is possible to reduce the circuit scale, speed up the processing at the time of starting the display device, and the like. Further, according to the present invention, there is provided an inverting circuit for inverting the polarity of the voltage generated by the voltage generating circuit with reference to an intermediate value between the lighting voltage and the non-lighting voltage. It is preferable that one of the voltages by the inverting circuit is alternately selected as the selection voltage to be supplied to the one scanning line at every one or more vertical scanning periods. According to this configuration, it is possible to prevent a DC component from being applied to the pixel capacitance. Furthermore, since the electronic device according to the present invention includes the above-described display device, it is possible to eliminate the need for voltage adjustment when the display device is incorporated into the electronic device. Note that such electronic devices include a personal computer, a mobile phone, a digital still camera, and the like.

On the other hand, in order to achieve the above object, in a power supply circuit of a display device according to the present invention, a pixel capacitor whose optical density changes in accordance with an applied voltage between a scanning line and a data line; A switching element that is turned on when an applied voltage becomes equal to or higher than a threshold; and a switching element that is connected in series, and for one scanning line, a switching element of a pixel belonging to the one scanning line is connected to a data line. A selection voltage for making the conductive state regardless of the voltage, and for other scanning lines, a non-selection voltage for making the switching elements of the pixels belonging to the other scanning line non-conductive state regardless of the voltage of the data line, When the pixel capacitance of the pixel corresponding to one data line and the scanning line to which the selection voltage is supplied is to be turned on while the lighting voltage is to be turned off, To A power supply circuit that generates a voltage selected as at least the selection voltage for a display device that supplies a lighting voltage to the one data line, wherein a storage unit that stores voltage data in advance; And a voltage generation circuit that generates a voltage corresponding to the stored voltage data and supplies the voltage to the scanning line driving circuit as the selection voltage. According to this configuration, since the voltage corresponding to the stored voltage data is supplied as the selection voltage, there is no need to adjust the voltage thereafter.

According to another aspect of the present invention, there is provided a driving circuit for a display device according to the present invention, wherein a pixel capacitor whose optical density changes according to an applied voltage between a scanning line and a data line; A driving circuit of a display device that drives a pixel in which a switching element that is turned on when an applied voltage becomes equal to or higher than a threshold value drives a pixel connected in series. The selection voltage for turning on the switching elements of the pixels belonging to the data line regardless of the voltage of the data lines is not applied to the other scanning lines regardless of the voltage of the data lines. A case in which the scanning line drive circuit that selects and supplies the non-selection voltage to be turned on and the pixel capacitance of the pixel corresponding to one data line and the scanning line to which the selection voltage is supplied are to be turned on. To When the lighting voltage is to be set to the off display state, the non-lighting voltage is supplied to the one data line, a data line driving circuit that supplies the data line, a storage unit that stores voltage data in advance, and a storage unit that stores the voltage data. A voltage generation circuit that generates a voltage corresponding to the voltage data and supplies the voltage as the selection voltage to the scanning line driving circuit. With this configuration also, the voltage corresponding to the stored voltage data is supplied as the selection voltage, so that there is no need to adjust the voltage thereafter.

Further, in order to achieve the above object, in the method of driving a display device according to the present invention, the display device is provided corresponding to the intersection of the scanning line and the data line, and the optical density varies according to the applied voltage. And a switching element that is turned on when an applied voltage becomes equal to or higher than a threshold value. A method of driving a display device that drives a pixel in which a voltage corresponding to voltage data stored in advance. And selecting and supplying the generated voltage to one scanning line as a selection voltage for turning on a switching element of a pixel belonging to the one scanning line, and selecting one data line and a selection voltage. When the pixel capacitance of the pixel corresponding to the supplied scanning line is to be turned on, the lighting voltage is supplied to the one data line, and when the pixel capacitance is turned off, the non-lighting voltage is supplied to the data line. It is characterized in that way. According to this method as well, the voltage corresponding to the stored voltage data is supplied as the selection voltage, so that there is no need to adjust the voltage thereafter. In this method, it is preferable that the voltage data is stored in correspondence with a selection voltage at which the ratio between the optical density of the pixel capacitance in the on display state and the optical density of the pixel capacitance in the off display state is maximized. . When such voltage data is stored, for each display device,
High quality display can be promised.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

<Configuration> First, the electrical configuration of the display device according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing an electrical configuration of the display device. As shown in this figure, the panel 100 of the display device includes:
While a plurality of data lines (segment electrodes) 212 are formed extending in the column (Y) direction, a plurality of scanning lines (common electrodes) 312 are formed extending in the row (X) direction. The pixel 116 is formed at each intersection of the data line 212 and the scanning line 312. Here, each pixel 116
Denotes a pixel capacitor 118 and a TFD (Thin Film Diode) which is an example of a two-terminal switching element.
220 in series. Of these, the pixel capacitance 11
8 has a configuration in which a liquid crystal, which is an example of an electro-optical material, is sandwiched between a scanning line 312 functioning as a counter electrode and a pixel electrode, as described later. In this embodiment, for convenience of explanation, the total number of the scanning lines 312 is assumed to be 160 and the total number of the data lines 212 is assumed to be 120,
Although the present invention will be described as a matrix type display device having rows × 120 columns, the present invention is not limited to this.

Next, the Y driver 350 is generally called a scanning line driving circuit, and scan signals Y1 and Y
2, Y3,..., Y160 are represented in the first and second rows, respectively.
The third line,..., Are supplied to the 160th scanning line 312. More specifically, the Y driver 350 selects 160 scanning lines 312 one by one as described later, and applies a selection voltage to the selected scanning line 312, a non-selection voltage to the other scanning lines 312, Each is supplied.

The X driver 250 is generally called a data line driving circuit, and the Y driver 350
, X120 are applied to the pixel 116 located on the scanning line 312 selected by
The data is supplied via the corresponding data line 212 according to the display content. The detailed configuration of the X driver 250 and the Y driver 350 will be described later.

On the other hand, the control circuit 400
It supplies gradation data, various control signals, clock signals, and the like to be described later to the 0 and Y drivers 350 to control both. The power supply circuit 500 generates the voltage ± V _S and the voltage ± V _D / 2 used for the panel 100, respectively. In the present embodiment, the voltage ± V _S is used as the selection voltage in the scanning signal. In addition, the voltage ± V _D / 2 is configured so that the non-selection voltage in the scanning signal and the data voltage in the data signal are also used. The detailed configuration of the power supply circuit 500 will be described later.

<Mechanical Configuration> Next, the mechanical configuration of panel 100 will be described. FIG. 2 is a perspective view showing the overall configuration of panel 100. FIG. 3 is a partial cross-sectional view showing a configuration when the panel 100 is broken along the X direction. FIG. 4 is a partial cross-sectional view showing a configuration when the panel 100 is broken along the Y direction. FIG. As shown in these figures, the panel 100 includes an element substrate 200 located on the back side and an element substrate 2 located on the observation side.
The counter substrate 300, which is one size smaller than 00, is bonded with a certain gap kept by the sealing material 110 mixed with conductive particles (conductive material) 114 also serving as a spacer.
c) Type liquid crystal 160 is sealed. The sealing material 110 is formed in a frame shape along the inner peripheral edge of the counter substrate 300 as shown in FIG.
A portion is open for enclosing 60. Therefore, after the liquid crystal is sealed, the opening is sealed by the sealing material 112.

On the opposing surface of the opposing substrate 300, scanning lines 3 which are strip-shaped electrodes extending in the row (X) direction are provided.
In addition to 12, an alignment film 308 is formed and rubbing is performed in a certain direction. Here, one end of the scanning line 312 is connected to the sealing material 1 as shown in FIG.
It has been extended to 10 formation areas. A polarizer 131 is attached to the outside (observation side) of the counter substrate 300 (omitted in FIG. 2), and the absorption axis of the polarizer 131 is aligned with the alignment film 308.
Is set according to the direction of the rubbing process.

On the other hand, on the opposite surface of the element substrate 200, Y
A rectangular pixel electrode 234 is formed adjacent to the data line 212 extending in the (column) direction, an alignment film 208 is formed, and a rubbing process is performed in a certain direction. Now, the wiring 342 is provided on the element substrate 200 in one-to-one correspondence with each of the scanning lines 312. Specifically, one end of the wiring 342 is formed so as to face one end of the corresponding scanning line 312 in the formation region of the sealant 110, as shown particularly in FIG.
Here, the conductive particles 114 are dispersed in the sealing material 110 at such a ratio that at least one conductive particle 114 is interposed in a portion where one end of the scanning line 312 and one end of the wiring 342 face each other. Therefore, the scanning lines 31 formed on the opposite substrate 300
2 is an element substrate 200 via the conductive particles 114.
Are connected to the wiring 342 on the opposing surface of, and are drawn out of the formation region of the sealing material 110.
Further, one end of the data line 212 formed on the element substrate 200 is pulled out to the outside of the formation region of the sealing material 110 as it is. Further, a polarizer 121 is attached to the outside (back side) of the element substrate 200 (omitted in FIG. 2), and the absorption axis thereof is set according to the direction of the rubbing process on the alignment film 208. Note that, since the panel 100 in the present embodiment is of a transmission type, a backlight unit for uniformly irradiating light is provided on the back side of the element substrate 200, but is not directly related to the present invention, Illustration is omitted.

Next, a description will be given of the area outside the display area of the panel 100. As shown in FIG. Driver 25
0 and a Y driver 350 for driving the scanning line 312 are mounted by COG (Chip On Glass) technology. As a result, the X driver 250
While supplying a data signal directly to the data line 212,
The Y driver 350 includes the wiring 342 and the conductive particles 11
4, a scanning signal is supplied to the scanning line 312 indirectly.

An FPC (Flexible Printed Circuit) is provided near the outside of the area where the X driver 250 is mounted.
One end of the substrate 150 is joined. Here, near the center of the FPC board 150, an IC chip constituting the power supply circuit 500 is mounted by COF (Chip On Film) technology. The connection destination of the other end of the FPC board 150 is omitted in FIG. 2, but is usually the control circuit 400 in FIG. That is, the control circuit 400
However, various signals are supplied to the power supply circuit 500, the X driver 250, and the Y driver 350, respectively. However, as will be described later, the connection destination of the other end of the FPC board 150 is immediately after the panel 100 is assembled, and serves as an adjustment device when setting the selection voltage. The X driver 250 and the Y driver 350 in FIG. 1 are different from those in FIG.
Are located to the left and above, respectively,
It is only a convenient measure for describing the electrical configuration. Further, the X driver 250 and the Y driver 350
Are mounted on the element substrate 200, for example, using a TAB (Tape Automated Bonding) technique, and a TCP (Ta) on which each driver and a power supply circuit are mounted.
pe Carrier Package) may be electrically and mechanically connected by an anisotropic conductive film.

<Structure of Pixel> Next, the detailed structure of the pixel 116 in the panel 100 will be described. FIG. 5 is a partially broken perspective view showing the structure. In this figure, the orientation film 20 shown in FIGS.
8, 308 and the polarizers 121 and 131 are omitted. As shown in FIG. 5, rectangular pixel electrodes 234 made of a transparent conductor such as ITO (Indium Tin Oxide) are arranged in a matrix on the opposing surface of the element substrate 200. The pixel electrodes 234 arranged in columns are connected to one data line 212 by TFD2, respectively.
20 are commonly connected. Here, TFD22
Reference numeral 0 denotes a first conductor 222 formed of tantalum alone or a tantalum alloy or the like and branched from the data line 212 in a T-shape when viewed from the substrate side, and the first conductor 222 is anodized. 224 and a second conductor 226 such as chromium to form a conductor / insulator / conductor sandwich structure. Therefore, the TFD 220 has a diode switching characteristic in which the current-voltage characteristic is non-linear in both positive and negative directions.

The insulator 201 formed on the upper surface of the element substrate 200 has transparency and insulating properties. The reason why the insulator 201 is formed is to prevent the first conductor 222 from peeling off by heat treatment after the deposition of the second conductor 226, and to diffuse impurities into the first conductor 222. This is to prevent it. Therefore, when these do not cause a problem, the insulator 201 can be omitted.

On the other hand, the opposite surface of the opposite substrate 300
Scan lines 312 made of O or the like extend in a row direction orthogonal to the data lines 212 and are arranged at positions facing the pixel electrodes 234. Thereby, the scanning line 312 becomes
It will function as a counter electrode of the pixel electrode 234.
Therefore, at the intersection of the data line 212 and the scanning line 312, the pixel capacitance 118 in FIG.
12, the pixel electrode 234, and the liquid crystal 160 sandwiched between them.

Then, in such a configuration, regardless of the data voltage applied to the data line 212, T
When a selection voltage for forcibly turning on the FD 220 is applied to the scan line 312, the TFD 220 corresponding to the intersection of the scan line 312 and the data line 212 turns on, and the pixel connected to the turned on TFD 220 Charge corresponding to the difference between the selection voltage and the data voltage is stored in the capacitor 118. After the charge accumulation, even if the non-selection voltage is applied to the scanning line 312 to turn off the TFD 220, the accumulation of the charge in the pixel capacitor 118 is maintained.
Here, according to the amount of charge stored in the pixel capacitance 118,
Since the alignment state of the liquid crystal 160 changes, the polarizer 121,
The amount of light passing through 131 also changes according to the amount of accumulated charge. Therefore, by controlling the amount of charge stored in the pixel capacitor 118 for each pixel by the data voltage when the selection voltage is applied, a predetermined gradation display can be performed.

<Driving Method> Next, in the panel 100 according to the present embodiment, the pixels 116 are driven by a four-value driving method (1 / 2H select, 1H inversion). Since this driving method is not directly related to the present invention, a detailed description thereof will be omitted, but for simplicity, one horizontal scanning period 1H is divided into two parts, a first half period and a second half period. For example, the selection voltage is applied to the scanning line in the latter half period, and the data voltage corresponding to the display content of the pixel located in the scanning line is applied to the corresponding data line. This is a driving method in which a reverse polarity voltage of a voltage to be applied is previously applied to the data line. In this embodiment, the scanning line 3
12 and the polarity standard of the voltage applied to the data line 212 are as follows:
It is based on the intermediate voltage of the data voltage ± V _D / 2 applied to the data line 212.

According to such a four-value driving method, the effective value of the data voltage is constant across the data lines without depending on the display pattern, so that the occurrence of so-called crosstalk is prevented. . Hereinafter, signals, configurations, and the like necessary to execute the four-value driving method will be described.

<Control Circuit> First, various signals such as a control signal and a clock signal generated by the control circuit 400 in FIG. 1 will be described.

First, the signals used on the Y (vertical scanning) side will be described. First, as shown in FIG. 7, the start pulse DY is a pulse output at the beginning of one vertical scanning period (1F). Second, the clock signal YCK
Is a reference signal on the Y side, and as shown in FIG.
It has a cycle of a horizontal scanning period (1H). Third, the polarity instructing signal POL is a signal for instructing the polarity of the selection voltage in the scanning signal, and as shown in FIG. The level is inverted, and the logic level is inverted even if attention is paid to the same horizontal scanning period in adjacent vertical scanning periods. Fourth, the control signal INH is a signal for defining a selection voltage application period in one horizontal scanning period 1H. Note that the control signal INH is obtained by shifting the phase of the clock signal YCK by 180 degrees as a result.

Next, signals used on the X (horizontal scanning) side will be described. First, as shown in FIG. 9, the start pulse DX is a pulse that is output at the start of supplying the grayscale data Dpix for one row. Here, the gradation data Dpix is data indicating a gradation of a pixel, and in this embodiment, is 3 bits for convenience. Therefore, the display device according to the present embodiment performs 8 (= 2 ³ ) gradation display for each pixel according to the 3-bit gradation data Dpix. Second, the clock signal XC
K is a reference signal on the X side, and its cycle corresponds to a period during which the gradation data Dpix for one pixel is supplied, as shown in FIG. Third, the latch pulse LP is 1
It is a pulse that rises at the start of the horizontal scanning period (1H), and is a pulse that is output at a timing after the grayscale data Dpix for one row is supplied, as particularly shown in FIG. Fourth, the reset signal RES is a pulse signal that is output at the beginning of the first half of the horizontal scanning period and at the beginning of the second half of the period, as shown in FIG. Fifth, as shown in the figure, in each of the first half and the second half of one horizontal scanning period (1H), the gradation code pulse GCP is a pulse arranged at a position of a period corresponding to the intermediate gradation. It is. Here, in the present embodiment, if the 3-bit grayscale data Dpix is (000), it indicates white display, which is the highest grayscale, while (11)
In the case of 1), assuming that black display, which is the lowest gray scale, is instructed, the gray scale code pulse GCP has a gray (11) excluding white or black in one half of one horizontal scanning period.
0), (101), (100), (011), (01)
The pulses are arranged in correspondence with the six pulses (0) and (001). The gradation code pulse GCP is actually set in consideration of the voltage-transmittance (density) characteristics of the panel 100.

<Y Driver> Next, details of the Y driver 350 will be described. FIG. 6 shows this Y driver 350.
FIG. 3 is a block diagram showing the configuration of FIG. In this figure, a shift register 352 has one scan line 312 corresponding to the total number.
It is a 60-bit shift register. Specifically, the shift register 352 sequentially shifts the start pulse DY supplied at the beginning of one vertical scanning period according to the clock signal YCK, and transfers the transfer signals Ys1, Ys2, Ys3,.
These are sequentially output as Ys160. Here, the transfer signals Ys1, Ys2, Ys3,..., Ys160 correspond one-to-one with the first, second, third,. When one of the transfer signals goes to the H level, it means that the horizontal scanning period in which the corresponding scanning line 312 should be selected.

Subsequently, the voltage selection signal forming circuit 354
In addition to these transfer signals, the voltage selection signals a, b, c, and d that determine the voltage to be applied to the scanning line 312 are exclusively obtained from the polarity indication signal POL and the control signal INH.
It is output in correspondence with every twelve. Here, in the present embodiment, as described above, the voltage of the scanning signal applied to the scanning line 312 is + V _S (positive electrode side selection voltage) and + V _D
/ 2 (positive electrode side non-selection voltage), - V _S (anode-side non-selection voltage), - a four values of V _D / 2 (negative-side selection voltage), of which the selection voltage + V _S or -V _S is The period in which the voltage is actually applied is 1 / 2H of the latter half of one horizontal scanning period. Further, the non-selection voltage is + V _D / 2 after the selection voltage + V _S is applied, −V _D / 2 after the selection voltage −V _S is applied, and is unambiguous by the immediately preceding selection voltage. It is fixed.

Therefore, the voltage selection signal forming circuit 354
Generates the voltage selection signals a, b, c, and d such that the voltage levels of the scanning signals have the following relationship. That is, the level of any one of the transfer signals Ys1, Ys2,.
When NH becomes H level and is informed of the latter half of the horizontal scanning period, the voltage selection signal forming circuit 35
4 indicates the voltage level of the scanning signal to the scanning line 312,
First, the voltage is a selection voltage having a polarity corresponding to the signal level of the polarity instruction signal POL. Generate

Specifically, the voltage selection signal forming circuit 354
When the polarity instruction signal POL is at the H level during the period in which the control signal INH is at the H level, the positive side selection voltage +
A voltage selection signal a to select V _S output during the period,
Thereafter, when the control signal INH transitions to the L level, a voltage selection signal b for selecting the positive-side non-selection voltage + V _D / 2 is output, and during the period when the control signal INH is at the H level, the polarity indication signal POL There a voltage selection signal d for selecting the negative-side selection voltage -V _S if L level is output during the period, after this, the control signal INH is if a transition to the L level, the negative-side non-selection voltage -V _D / 2 to output a voltage selection signal c.

Next, the level shifter 356 outputs the voltage selection signal a, output by the voltage selection signal forming circuit 354,
The voltage amplitudes of b, c, and d are respectively enlarged.
Then, the selector 358 actually selects the voltage indicated by the voltage selection signals a ′, b ′, c ′, and d ′ whose voltage amplitudes have been enlarged, and outputs the voltage to each of the corresponding scanning lines 312 as a scanning signal. To be applied.

<Voltage Waveform of Scanning Signal> Next, the voltage waveform of the scanning signal supplied by the Y driver 350 having the above configuration will be examined. First, as shown in FIG. 7, the start pulse DY is sequentially shifted by the shift register 352 in each horizontal scanning period 1H according to the clock signal YCK, and this is transferred to the transfer signals Ys1, Ys2,.
It is output as Ys160. Here, in one horizontal scanning period in which a certain transfer signal is at the H level, the latter half period ＨH is selected by the control signal INH, and according to the logic level of the polarity instruction signal POL in the latter half period, the transfer signal is A selection voltage for the corresponding scan line is determined.

More specifically, the voltage of the scanning signal supplied to a certain scanning line is equal to the polarity indication signal P in the latter half ＨH of one horizontal scanning period 1H in which the scanning line is selected.
If OL is at the H level, for example, it becomes the positive-side selection voltage + V _S , and then holds the positive-side non-selection voltage + V _D / 2 corresponding to the selection voltage. Then, one vertical scanning period (1
F) elapses and in the second half of one horizontal scanning period, the polarity instruction signal POL is inverted to the L level, so that the voltage of the scanning signal supplied to the scanning line is negative-side selection voltage −V _S, and the subsequently will retain negative-side non-selection voltage -V _D / 2 corresponding to the selected voltage.
For example, in a certain vertical scanning period, the first scanning line 31
2, the voltage of the scanning signal Y1 as shown in FIG.
Positive-side selection voltage + V _S becomes the second half period of the horizontal scanning period, then holding the cathode-side non-selection voltage + V _D / 2. In the second half period of the next horizontal scanning period, the level of the AC driving signal MY goes L level inverted from the previously selected voltage of the scanning signal Y1 to the scanning line is negative-side selection voltage -V _S Then, the negative side non-selection voltage −
V _D / 2 is maintained. Hereinafter, this cycle is repeated.

Further, the polarity instruction signal POL is supplied for one horizontal scan.
Since the logic level is inverted every period 1H, each scanning line 31
The voltage of the scanning signal supplied to 2 is 1H during 1 horizontal scanning period.
Polarity, ie, alternately for each scanning line 312
The relationship is reversed. For example, in a certain frame, 1
The selection voltage of the scanning signal Y1 in the row is positive-side selection voltage + V _S
Then, after the lapse of one horizontal scanning period, the scanning of the second row
The selection voltage of the inspection signal Y2 is a negative selection voltage −V_SBecomes

<X Driver> Next, the details of the X driver 250 will be described. FIG. 8 shows this X driver 250.
FIG. 3 is a block diagram showing the configuration of FIG. In this figure, a shift register 25100 sequentially shifts a start pulse DX output at a supply start timing of the grayscale data Dpix for one row at every rising edge of a clock signal XCK, and obtains sampling control signals Xs1, Xs2, Xs
.., Xs120.

Subsequently, the register (Reg) 2520 is
The supplied gradation data Dpix, which is provided in one-to-one correspondence with the data lines 212, is sampled and held at the rising edge of the sampling control signal. Further, the latch circuit (L) 2530 is provided in one-to-one correspondence with the register 2520, and converts the gradation data Dpix held by the register 2520 by the rise of the latch pulse LP supplied at the start of the horizontal scanning period. It is latched and output.

On the other hand, at the rise of the reset signal RES, the counter 2540 sets (111) corresponding to the black display of the gradation data as an initial value, and sets the initial value every time the gradation code pulse GCP rises. It counts down and outputs the count result C. Next, a comparator (CMP) 2550 is provided in one-to-one correspondence with the latch circuit 2530, and
540 and the corresponding latch circuit 253
By comparing with the gradation data Dpix latched by 0,
When the latter becomes higher than the former, a signal which becomes H level is output.

The EX-OR circuit 2562 generates an exclusive OR signal M of the polarity designating signal POL and the control signal INH.
X is obtained, and the selection by the switch 2560 is thereby controlled. Specifically, switch 2560 is
If the exclusive OR signal MX is at the H level, the data voltage + V _D / 2 is applied to the voltage supply line 2568 and the data voltage −V _D / 2 is applied to the voltage supply line 2564 at the position indicated by the solid line in the figure. If the exclusive OR signal MX is at L level, the data voltage + V _D / 2 is applied to the voltage supply line 2 by taking the position shown by the broken line in the figure.
564, the data voltage −V _D / 2 is applied to the voltage supply line 2568.
, Respectively.

The switch 2570 is in one-to-one correspondence with the comparator 2550, that is, the data line 2
12 are provided in one-to-one correspondence with the comparator 25.
50, the voltage supply lines 2564 and 2568 according to the comparison result.
Is to select one of them. Specifically, the switch 25
70 selects the voltage supply line 2564 as shown by the solid line in the figure if the signal indicating the result of comparison by the comparator 2550 is at the L level, while indicated by the broken line in the figure if the signal is at the H level The voltage supply line 2568 is selected as described above, and the data voltage supplied to each selected voltage supply line is applied to the corresponding data line 212 as a data signal.

<Voltage Waveform of Data Signal> Next, the operation of the X driver 350 will be discussed in order to explain the voltage waveform of the data signal. First, as shown in FIG. 9, when the start pulse DX rises to the H level, the gradation data corresponding to the pixels in the first column, the second column, the third column,. Dpix is supplied in order.

At the timing when the gradation data Dpix corresponding to the pixels in the first column is supplied, the sampling control signal X output from the shift register 2510 is output.
When s1 rises to the H level, the gradation data becomes 1
It is sampled by the register 2520 corresponding to the column. Next, the gradation data Dpi corresponding to the pixels in the second column
When the sampling control signal Xs2 rises to the H level at the timing when x is supplied, the gradation data is sampled by the register 2520 corresponding to the second column. Similarly, the third and fourth rows,.
Each of the gradation data Dpix corresponding to the pixels in the 120th column is sampled by the register 2520 corresponding to the third column, the fourth column,..., The 120th column.

Subsequently, when the latch pulse LP is output (when its logical level rises to H level), the gradation data Dpix sampled by the register 2520 of each column is stored in the latch circuit corresponding to each column. 2530 latches all at once. On the other hand, the counting result C is, as shown in FIG.
(111) set by the rising edge of the counter 254 each time the gradation code pulse GCP rises.
The value is down-counted by 0. Therefore,
In the comparator 2550, the gradation data Dpix latched by the latch circuit 2530 and the counter 2540
Is compared twice for each data line in each of the first half and the second half of the horizontal scanning period defined by the latch pulse LP.

Incidentally, during the horizontal scanning period when the polarity instruction signal POL becomes H level, the exclusive OR signal MX is output.
Becomes H level in the first half period and L level in the latter half period. Therefore, in the first half of the horizontal scanning period, the voltage -V _D /
2 is applied and the voltage + V _D / 2 is applied to the voltage supply line 2568, while the voltage application relationship is reversed in the latter half of the horizontal scanning period.

Here, generally, the latch circuit 25 of the j-th column
Assume that the gradation data Dpix latched by 30 is (000) corresponding to the white of the highest gradation.
In this case, even if the grayscale code pulse GCP is output six times after the reset signal RES is output, the counting result C is
It does not fall below the latched (000). For this reason,
The output signal from the comparator 2550 in the j-th column maintains the L level both in the first half period and the second half period of one horizontal scanning period defined by the latch pulse LP. However, in the first half period and the second half period of the horizontal scanning period, the application relationship of the voltage applied to the voltage supply lines 2564 and 2568 is reversed.
The data signal supplied to Xj, as shown in FIG. 10, the horizontal voltage -V _D / 2 becomes in the first half period of the scanning period, the voltage + V _D / 2 in the second half period of the horizontal scanning period
Becomes

Next, generally, the latch circuit 253 on the j-th column
It is assumed that the grayscale data Dpix latched by 0 is gray, which is an intermediate grayscale, for example, (100). In this case, when the gradation code pulse GCP is output three times after the reset signal RES is output, the counting result C
Becomes less than or equal to (100) latched, and at this time, the output signal of the comparator 2550 in the j-th column transitions from the L level to the H level. Therefore, j
The data signal Xj supplied to the data line 212 in the column is
As shown in FIG. 10, the voltage becomes −V _D / 2 from the time when the reset signal RES is output in the first half of the horizontal scanning period until the time when the grayscale code pulse GCP is output three times. The voltage becomes + V _D / 2 until the reset signal RES is output in the latter half of the scanning period.
Also, during the latter half of the horizontal scanning period, the reset signal RE
When S is output, the output signal from the j-th column comparator 2550 returns to the L level, but at the same time, the application relationship of the voltages applied to the voltage supply lines 2564 and 2568 is reversed, so that the reset signal RES is output. Immediately after
Apparently, the data signal Xj maintains the voltage + V _D / 2. Then, when the gradation code pulse GCP is output three times, the data signal Xj changes to the voltage −V _D / 2. Note that, even when the latched gradation data Dpix corresponds to gray other than (100), transition occurs for the same reason except that the transition timing of the output signal by the comparator 2550 is different.

Further, generally, the j-th column latch circuit 25
It is assumed that the gradation data Dpix latched by 30 is (111) corresponding to the lowest gradation black.
In this case, when the reset signal RES is output,
Immediately, the count result C is latched (111), so that the output signal of the j-th column comparator 2550 is
The H level is maintained in both the first half period and the second half period of one horizontal scanning period defined by the latch pulse LP. However, in the first half period and the second half period of the horizontal scanning period, the application relationship of the voltage applied to the voltage supply lines 2564 and 2568 is reversed.
The data signal Xj supplied to 12, a voltage + V _D / 2 becomes in the first half period of the horizontal scanning period, the voltage -V _D / 2 in the second half period of the horizontal scanning period.

Although the horizontal scanning period in which the polarity designating signal POL is at the H level has been described here, only the exclusive OR signal MX is logically inverted in the horizontal scanning period in which the polarity designating signal POL is at the L level. And the same applies to the others. For this reason, the polarity instruction signal POL becomes L
In the first half of the horizontal scanning period in which the level is set, the voltage + V _D / 2 is applied to the voltage supply line 2564,
68 while the voltage -V _D / 2 is applied to, in the second half period of the horizontal scanning period, the voltage -V _D to the voltage supply line 2564
/ 2 is applied, and the voltage + V _D / 2 is applied to the voltage supply line 2568.
Is only applied. Therefore, as shown in FIG. 10, the data signal Xj in the horizontal scanning period in which the polarity instruction signal POL is at the L level is the logical level of the data signal Xj in the horizontal scanning period in which the polarity instruction signal POL is at the H level. It will be. However, in any horizontal scanning period, the lighting voltage contributing to the black display is commonly shifted backward in time.
Note that the lighting voltage here refers to a voltage of a data signal having a polarity opposite to that of a selection voltage applied in a period when a certain scanning line is selected in a period.

<Power Supply Circuit> Next, the power supply circuit 500 according to the present embodiment will be described. FIG. 11 is a block diagram showing a schematic configuration of the power supply circuit 500. This power supply circuit 500 uses a single power supply 510 (Vcc-GND)
From, generates a selected voltage ± V _S, the voltage Vcc and ground voltage GND, and supplies a ± V _D / 2 used also in the intact non-selection voltage and data voltage.
In the panel 100, the reference voltage of the polarity is an intermediate value of ± V _D / 2, and this voltage corresponds to Vcc / 2 (= VC) in the power supply circuit 500. In the present embodiment, This voltage is not actually generated, but is a virtual voltage. In the power supply circuit 500, the reference of the voltage is not the intermediate voltage Vcc / 2 (= VC) but the ground voltage GND.

Now, referring to FIG.
0 is the target voltage Vref using the voltage (Vcc-GND).
It generates a selection voltage + V _S corresponding to, and outputs via the supply line p1. Next, the inverting circuit 540 includes a capacitor Cp and a clock signal CL having a duty ratio of 50%.
It is provided with double throw switches 542 and 544 interlocked by K, and is configured as follows. That is, the selection terminal a of the switch 542 is connected to the supply line p1, the selection terminal b is connected to the supply line p2 of the voltage Vcc, and the output terminal c is connected to one end of the capacitor Cp.
The selection terminal a of the switch 544 is connected to the supply line n2 to which the ground voltage GND is applied, the selection terminal b is connected to the supply line n1, and the output selection terminal c is connected to the other end of the capacitor Cp. It is connected. Also, supply line n
A backup capacitor Cb2 is interposed between 1 and n2.

Here, in the inverting circuit 540, the switch 5
Terminals 42 and 544 are alternately switched according to the logic level of the clock signal CLK.
For example, according to the logic level of the clock signal CLK,
When the switch 542, 544 has selected the terminal a, respectively, the capacitor Cp, as shown in in FIG. 12, the selection voltage + V _S and high, the ground voltage GND
(= −V _D / 2) is charged at a low level. Next, when the switches 542 and 544 respectively select the terminal b by the transition of the logic level of the clock signal CLK, the high-order side of the capacitor Cp becomes the voltage Vcc (= +
Since the V _D / 2), as shown in in FIG. 12, the voltage of the low side, from the ground voltage GND when selecting the terminal a, is pulled down by variation of the high-potential (+ V _S -Vcc). Therefore, the potential of the supply line n1 connected to the low side of the capacitor Cp is to the intermediate voltage VC based positive electrode side of the selection voltage + V _S voltage is inverted, i.e., the selection voltage -V _S of the negative electrode side .

The switches 542 and 544 are connected to the terminal a.
When the re-selection, capacitor Cp, and a selection voltage + V _S and high are charged to a ground voltage GND as low, hereafter, so that the same operation is repeated. Note that the potential of the supply line n1 is held by the capacitor Cb2 even while the switches 542 and 544 are selecting the terminal a.

On the other hand, the memory (storage means) 522 stores voltage data representing the target voltage Vref in digital value, and is a writable nonvolatile memory such as a PROM.
(Programmable Read Only Memory) and EPROM (E
rasable Programmable ReadOnly Memory), EEPR
OM (Electrically Programmable Read Only Memory)
Are used. It should be noted that signal R / W instructing read / write to memory 522 is connected to an adjusting device as will be described later, and only when write is instructed, logical level (eg, H level) instructing write is applied. ), But in normal use other than in this case, it is always maintained at a logical level (for example, L level) for instructing reading. The timing at which the voltage data is read from the memory 522 is immediately after the entire display device according to the present embodiment is started. Therefore, a latch circuit 523 for continuously holding the read voltage data during the display operation is provided at the output stage of the memory 522.

Next, the selector 524 selects either the latched voltage data or the voltage data directly supplied from the outside according to the selection control signal Sel. In the present embodiment, voltage data is supplied from the outside only when connected to an adjustment device described later, and is not supplied during normal use. The selector 523 determines that the selection control signal Sel is at L level.
When the selection control signal Sel is at the H level, the input terminal B is selected. However, in this embodiment, the logic level of the selection control signal Sel changes only when the adjustment device is connected, and in other cases, the logic level is always set to the L level. On the other hand, the D / A converter 526 is connected to the selector 5
The voltage data selected by 24 is converted into an analog signal, and the converted signal is supplied to the voltage generation circuit 530 as a target voltage Vref. The D / A converter 526 in the present embodiment has a conversion characteristic such that the target voltage Vref increases as the decimal value of the voltage data increases.

<Voltage Generation Circuit> Subsequently, the power supply circuit 500
A detailed configuration of the voltage generation circuit 530 will be described. FIG. 13 is a circuit diagram showing a configuration of this voltage generation circuit 530. In this figure, a latch circuit 532 includes
At the rising edge of the clock signal CK1 supplied from the host device (for example, the control circuit 400), the signal Vcp supplied to the input terminal D is latched, and the latched signal is converted to Vrcp.
Is output from the output terminal Q. AND circuit 5
34 outputs a logical product signal Vg of the signal Vrcp and the clock signal CK1. That is, the AND circuit 5
34 outputs the clock signal CK1 in accordance with the signal Vrcp from the latch circuit 532. Here, for example, as shown in FIG. 14, the clock signal CK1 is a pulse signal having a pulse width of about 0.5 μs and a frequency of about several hundred kHz.

Next, the signal Vg from the AND circuit 534
Are supplied to the gate of the N-channel transistor 536. Here, the source of the transistor 536 is connected to the supply line of the ground voltage GND, and the drain thereof is connected to the inductor L whose one end is connected to the supply line of the voltage Vcc.
Is connected to the other end. Further, the other end of the inductor L is connected to a capacitor Cb1 via a forward diode D1.
Is connected to one end OUT, the difference between the end OUT and the ground voltage GND, are configured to be output as the selected voltage + V _S of the positive electrode side. The other end of the capacitor Cb1 is connected to a supply line for the ground voltage GND.

The one end OUT of the capacitor Cb1 is connected to the ground voltage GND supply line via the resistors R1 and R2. Here, for convenience of explanation, the voltage at the connection point of the resistors R1 and R2, that is, the selection voltage + V _S is changed by the resistor R
Assuming that the voltage divided by R1 and R2 is Vsd, this voltage Vsd is supplied to the negative input terminal of the comparator 428. On the other hand, the positive input terminal of the comparator 428 is
1 is supplied with the target voltage Vref which is analog-converted by the D / A converter 526 in FIG. Therefore, the output signal Vcp of the comparator 428 goes high when the voltage Vsd falls below the target voltage Vref, and goes low when the voltage Vsd exceeds the target voltage Vref. The output signal Vcp is fed back to the input terminal D of the latch circuit 422.

Next, will be described operation of generating the selection voltage + V _S of the voltage generating circuit 530. First, when the transistor 536 is turned on, a voltage Vcc is applied to the inductor L.
Since the on-current ion flows from the gate to the ground, energy is accumulated. On the other hand, when the transistor 426 is turned off, the off current ioff flows. Therefore, the energy accumulated during the on period of the transistor 536 is added in series with the voltage Vcc through the forward direction of the diode D1 and is added to the capacitor Cb1. Will move.

Here, when all the energy stored in the inductor L moves to the capacitor Cb1, the diode D
1 is reverse biased, so one end O of the capacitor Cb1
The current does not flow backward from the UT to the supply line of the voltage Vcc.
Therefore, the selection voltage + V _S increases every time the transistor 536 is turned on and off. In practice, the charging voltage of the capacitor Cb1, since attenuated by charging and discharging to such as resistors and pixel capacitance, such as the scanning lines in the display device, reduces the selection voltage + V _S with time progression, resistance to this R1, The voltage Vsd divided by R2 also decreases. Then, when the voltage Vsd falls below the target voltage Vref, the output signal Vcp of the comparator 538 transitions to the H level. Here, after the signal Vcp transitions to the H level, the clock signal C
When K1 rises, the signal Vrc by the latch circuit 532 is output.
Since p transitions to the H level, the AND circuit 532 opens. Therefore, the clock signal CK1 is supplied to the AND circuit 534.
Is output as the output signal Vg. Therefore, the voltage Vs
When d falls below the target voltage Vref, the transistor 536
Turns on and off at least once, so that the selection voltage + V
_S will rise. That is, when the voltage Vsd falls below the target voltage Vref, so that the control of the direction increasing the selection voltage + V _S is performed.

On the other hand, the selection voltage + V _S rises and the voltage Vs
When d exceeds the target voltage Vref, the comparator 532
Changes to the L level. Here, when the clock signal CK1 rises after the signal Vcp transitions to the L level, the signal Vrcp by the latch circuit 532 transitions to the L level, and the AND circuit 532 closes. For this reason, since the clock signal CK1 is not supplied to the gate of the transistor 426, the selection voltage + V _S gradually decreases due to the discharge of the capacitor Cb1. That is, when the voltage Vsd above than the target voltage Vref, the results in the control of the direction decreasing the selection voltage + V _S is performed.

Therefore, in the voltage generating circuit 530 as a whole, the voltage Vsd is stabilized at a point where the control in both directions is balanced, that is, near the target voltage Vref.
The voltage Vsd is resistance selection voltage + V _S R1, R2
Because it is obtained by dividing the voltage by, Vsd = V _S · R2 /
(R1 + R2) is established, since this is stabilized at the target voltage Vref, the end, the selection voltage V _S of the positive polarity generated by the voltage generating circuit 530, Vref (R1 + R2)
/ R2. The selection voltage + V _S
In order to stabilize the resistance, it is necessary to keep the resistance values of the resistors R1 and R2 high. To this end, the (substantially intrinsic) polysilicon wiring layer formed in the semiconductor IC must This can be realized by using Further, the vertical scale of the voltage Vsd in FIG. 14 is enlarged as compared with other signals for the sake of explanation. In other words, since the comparator 538 operates using the voltage Vcc as a power supply, the input voltage Vsd and the target voltage Vref
Are actually set to be higher than the voltage GND and lower than the voltage Vcc.

<Significance of Selection Voltage and Data Voltage> Next, the characteristics of voltage-transmittance (density) of panel 100 and selection voltage ± V supplied from power supply circuit 500 to Y driver 350 are described.
The relationship between _{S and} ± V _D / 2 supplied to the X driver 250 will be described. The voltage-transmittance characteristic of a general liquid crystal panel is as shown in FIG. 15A in a normally white mode. That is, if the effective value of the voltage applied to the pixel capacitor 118 (the time unit is, for example, one vertical scanning period) is within the range A, the transmittance decreases as the effective voltage value increases. However, if it is not in the range A, the transmittance hardly changes even if the effective voltage value changes. Therefore, when gradation display is performed, the pixel capacitance 11
It is necessary that the effective value of the voltage applied to 8 falls within the range A. Furthermore, in order to obtain high-quality display,
The minimum value Voff of the effective voltage value applied to the pixel capacitor 118
The ratio between the transmittance Tw of the image and the transmittance Tb of the maximum value Von (this is referred to as a contrast ratio) must be increased.

However, even if the characteristics of the voltage-transmittance are the same lot, the characteristics shown in FIGS.
Normally, it differs for each panel 100 as shown in FIG. Therefore, in order to maximize the contrast ratio in each panel 100, the minimum voltage effective value and the maximum voltage effective value are appropriate in accordance with the voltage-transmittance characteristics of the panel 100. Need to be adjusted.

On the other hand, in the above-described four-value driving method (１ ／ H select, 1H inversion), the effective voltage value generally applied to the pixel capacitor 118 in the i-th row and j-th column is the scan line 3 in the i-th row.
12, the selection voltage is applied to the TFD 220
Is substantially determined by the selection voltage when is turned on and the voltage of the data signal applied to the data line 212 in the j-th column when the TFD 220 is turned on. Strictly speaking,
Since the off-resistance of the TFD 220 is not infinite, it is necessary to consider the leakage of the pixel capacitance during the period when the non-selection voltage is applied to the i-th scanning line 312, but this is ignored here.

For this reason, for example, the pixel capacitance 11 in the i-th row and the j-th column
8, the effective value of the voltage is minimized during the period in which the selection voltage of any polarity is applied to the i-th scanning line 312 (the period in which the TFD 220 in the i-th row and the j-th column is turned on). This is the case where the voltage of the data signal Xj applied to the data line 212 in the column has the same polarity as the selection voltage, that is, the data signal Xj has a waveform corresponding to white (off) in FIG. Further, for example, the effective value of the voltage applied to the pixel capacitor 118 in the i-th row and the j-th column is maximized during the period in which the selection voltage of any polarity is applied to the i-th scanning line 312. Data line 212
Is applied when the voltage of the data signal Xj has the opposite polarity to the selection voltage, that is, the data signal Xj has a waveform corresponding to black (ON) in FIG.

In other words, the selection voltage in the scanning signal is irrelevant to the display content and defines the turning on of the TFD 220.
It also defines a reference for the density of the pixel 116 in the i-th row and the j-th column. On the other hand, the voltage of the data signal defines how much the density of the pixel is actually changed from the reference of the density of the pixel 116 in the i-th row and the j-th column. Here, in the present embodiment, since the voltage of the data signal is fixed, the minimum effective voltage value Voff and the maximum effective voltage value Von applied to the pixel capacitance 118 at the i-th row and the j-th column, in other words, gradation Tw and the minimum gradation Tb, hence the contrast ratio will be determined only by the selection voltage ± V _S of the scanning signal.

Therefore, in order to maximize the contrast ratio, the selection voltage ± V _{S is} applied to each panel 100.
Is appropriately set, for example, as shown in FIG. 15 (a). In the present embodiment, first,
It is generated according to the target voltage Vref by the voltage generating circuit 530 of the power supply circuit 500 selects the voltage + V _S (see FIG. 11), the second, inverting circuit generated selection voltage + V _S 5
Selection voltage -V _S by polarity reversal is generated by 40. Here, the target voltage Vref is obtained by converting the voltage data stored in the memory 522 into an analog voltage by the D / A converter 526. Therefore, the power supply circuit 5
00, the memory 522 stores the panel 10 to be connected to.
By writing voltage data according to the voltage-transmittance characteristic of 0, the contrast ratio of the panel 100 can be maximized. Therefore, next, an adjustment device for appropriately setting the selection voltage ± V _S for optimizing the contrast ratio for each panel 100 will be described.

<Adjustment Apparatus> Next, FIG. 16 is a diagram showing a configuration of the adjustment apparatus 600 and a connection state with the panel 100. As shown in this figure, the FPC board 1
The other end of 50 is connected to adjustment device 600. Here, the panel 100 is in a state after being assembled as shown in FIG. 2 and before being incorporated into the display unit of the electronic device, and is controlled by an adjusting device 600 that is a substitute for the control circuit 400. It is configured to be.

Now, referring to FIG.
Is actually a personal computer or the like, and the bus 6
The interface 612 and 614 are provided in addition to a CPU 604 that controls each unit via the O.02, a ROM 606 that stores a basic control program and the like, a RAM 608 that stores programs and various variables described below, and the like. As described above, since the panel 100 is of a transmission type in the present embodiment, the cold cathode tube 180 serving as a light source of the backlight is provided on the back side of the panel 100. On the other hand, the photo sensor 700 is installed on the observation side of the panel 100, and detects the light modulated by the panel 100 out of the light emitted by the cold cathode fluorescent lamp, that is, the density of the pixel by the panel 100. . Then, the photo sensor 700
Is detected by the adjusting device 600 via the interface 612.
The interface 614 is connected to the other end of the FPC board 150 and is used to control the panel 100.

[0073] Following <settings selection voltage>, using the adjustment device 600 described above, the operation for setting the selected voltage ± V _S. This setting operation is performed by the RAM 60
The program is executed in accordance with the application program loaded in the program 8, and the operation is roughly as follows. That is, the application program measures the contrast ratio of the panel 100 while
The voltage data (variable) supplied to the A / A converter 526 is increased stepwise from an initial value to a maximum value.
That is, voltage data for maximizing the contrast ratio of 0 is written in the memory 522. Therefore, the setting operation of the selection voltage by the application program will be described below with reference to the flowchart shown in FIG.

First, when this application program is started, the CPU 602 stores the initial value V in a variable Vdata.
While setting min, the variables Vd, Ctmax and Ct0 are reset (step Sa1). Next, the CPU 602
Is connected to the selection control signal S via the interface 614.
el is set to the H level (step Sa2). Thus, in the power supply circuit (see FIG. 11) 500, the selector 52
At 4, the input terminal B is selected. Subsequently, the CPU 602
Supplies the variable Vdata at the current time as voltage data to the panel 100 via the interface 614 (step Sa3). In this state, the selector 52
4, since the input terminal B is selected, the voltage generation circuit 5
The positive-side selection voltage + V _S by 30 is obtained by setting the variable Vdata to D
A / A converter 526 corresponds to the target voltage Vref converted. Further, the selection voltage −V _S on the negative electrode side by the inverting circuit 540 is obtained by dividing the selection voltage + V _S by the voltage Vcc / 2.
(= VC) as a reference.

Here, in step Sa1, the variable Vda
The initial value Vmin set to ta is the T of the pixel 116 corresponding to the intersection of a certain scanning line 312 and a certain data line 212.
The FD 220 corresponds to the lowest voltage value of the scanning signal that is forcibly turned on regardless of the voltage of the data signal applied to the data line 212. That is, when step Sa3 is executed for the first time, the value of the variable Vdata is
The initial value Vmin is set in step Sa1. When the initial value Vmin is supplied to the D / A converter 526, the voltage + V _S (generated in accordance with the target voltage Vref obtained by converting the initial value Vmin into an analog signal). In order to ensure that the voltage −V _S ) whose polarity has been inverted by the inversion circuit 540 functions as the selection voltage, the initial value Vmin is set in the variable Vdata in step Sa1.

Next, the CPU 602 causes the data signals X1 to 120 to all correspond to the OFF waveform via the interface 614 (step Sa4). In particular,
If it is normally white, the CPU 602 supplies the gradation data Dpix corresponding to white display over all pixels. Thereby, in the panel 100, all the pixels 11
6 are displayed in white. Subsequently, the CPU 602
By taking in the detection signal Vdet from the photo sensor 700 via the interface 612, the pixel density Tw for white display is measured and temporarily stored (step Sa5).

Next, the CPU 602 causes all the data signals X1 to 120 to correspond to the ON waveform via the interface 614 (step Sa6). In particular,
If normally white, the CPU 602 supplies gradation data Dpix corresponding to black display over all pixels. Thereby, in the panel 100, all the pixels 11
6 is displayed in black. Subsequently, the CPU 602
By taking in the detection signal Vdet from the photosensor 700 via the interface 612, the pixel density Tb for black display is measured and temporarily stored (step Sa7).

[0078] Next, CPU 602 is the ratio of the temporarily stored concentrations Tw and concentration Tb, in particular, the contrast in the case where the voltage ± V _S corresponding to the variable Vdata at the present time the selection voltage of the scanning signal The ratio is stored in a variable Ct0 (step Sa8), and it is determined whether the variable Ct0 is larger than a variable Ctmax (step Sa9). Here, if the variable Ct0 is larger than the variable Ctmax, the CPU 6
02 sets the variable Ct0 to the variable Ctmax,
The current variable Vdata is set as a variable Vt (step Sa10). More specifically, the contrast ratio when the current variable Vdata is supplied to the panel 100 indicates that one of the past variables Vdata is
, The current variable Vdata (corresponding to the improved contrast ratio) is temporarily stored in the variable Vd, and for comparison in the future, the current variable Vdata is stored in the variable Vd. The variable Ct0 indicating the contrast ratio is temporarily stored in the variable Ctmax. That is, the variable Vdata is set to the initial value V
The maximum value of the contrast ratio when stepwise changed from min is stored, and the variable Vd stores the variable Vdata that maximizes the contrast ratio. However, when step Sa8 is executed for the first time without going through step Sa12 described later, the contrast ratio when variable Vdata is the initial value Vmin is stored in variable Ctmax, and variable Vdata is stored in variable Vd. Initial value Vm
in will be stored. Note that the variable Ct0 is the variable Ctm
If it is equal to or less than ax, the CPU 602
Step Sa10 is skipped in order to respect data.

Then, the CPU 602 determines whether or not the current variable Vdata is equal to a preset upper limit value max (step Sa11). Here, if the variable Vdata is not the upper limit value Vmax, the CPU 602 determines that the variable Vdata
Is incremented by "1" in decimal notation (step Sa12), and the processing procedure returns to step Sa3. Thus, steps Sa3 to Sa11 are executed for the variable Vdata incremented by “1”. On the other hand, if the variable Vdata is the upper limit value Vmax, the CPU
602, via interface 614, signal R /
W is set to the H level, and the variable Vd is stored in the memory 522.
(Step Sa13), and the application program is terminated. By this step Sa13, the memory 522 stores the initial value Vmin to the upper limit value Vmax.
The variable that maximizes the contrast ratio of the panel 100 is written out of the variables Vdata that have been changed stepwise. After that, the panel 100 is disconnected from the adjustment device 600 and is incorporated as a display unit of the electronic device.

When the variable Vdata (Vd) for maximizing the contrast ratio is stored in the memory 522,
Thereafter, in panel 100, this variable is set to power on (startup).
It is read as voltage data each time it is, while the voltage + V _S is generated according to the target voltage Vref the voltage data and analog conversion, by polarity inversion voltage -V _S is generated to thereby inverting circuit 540 You. Then, these voltages ± V _S is supplied to the Y driver 350, it will be used as the selection voltage in the scanning signal Y1～Y160. Therefore, when variable Vdata (Vd) is stored in memory 522 by adjustment device 600,
No voltage adjustment is required. In addition, the variable Vdata (Vd) stored in the memory 522 is set individually for the panel 100 and maximizes the contrast ratio of the panel 100.
The display quality of 0 is always maintained in an optimized state.

<Application Examples and Others of Display Device> In the above-described embodiment, the voltage +
After generating the V _S, but which was supplied as a voltage -V _S and polarity reversal, on the contrary, after generating the voltage -V _S, which may be supplied as a polarity reversal to the voltage + V _S a. Also,
In the embodiment, the voltage data read from the memory 522 and the target voltage Vref obtained by converting the voltage data from the memory 522 are fixed after the adjustment. However, with the provision of the temperature sensor, the voltage data read from the memory 522 Temperature compensation may be performed by increasing or decreasing according to a digital value as a detection result of the sensor (or increasing or decreasing the target voltage Vref according to an analog value as a detection result of the temperature sensor). On the other hand, the power supply circuit 500 according to the embodiment
Is shown as one IC chip in FIG. 2, but it is actually difficult to chip the inductor L and the like, so that it is mounted on the FPC board 150 as a separate component. Therefore, except for the parts that are mounted as separate components, it is possible to enjoy the merit of reducing the number of components by adopting a configuration on one chip as much as possible. Further, in the embodiment, in order to reduce the number of generated voltages, the scanning lines 31 are used.
The second non-selection voltage and the data voltage to the data line 212 are also used. However, it is needless to say that they may be separate.

Further, in the embodiment, the case where the gradation data Dpix is set to 3 bits and 8 gradations are displayed has been described. However, the present invention is not limited to this. And 2 bits or 4
A gradation display with more than bits may be used. Furthermore, R
One pixel may be constituted by three pixels of (red) G (green) and B (blue) to perform color display. In addition, in the embodiment, the transmission type is used, but the reflection type may be used, or a transflective type using both of them may be used.

On the other hand, in the embodiment, the normally white mode in which white display is performed in a state where no voltage is applied to the pixel capacitance has been described. However, the normally black mode in which black display is performed in the same state may be adopted. Further, in the embodiment, when the selection voltage is applied, the lighting voltage contributing to the black display is configured to be applied temporally rearward, but is configured to be applied temporally forward. Alternatively, the configuration may be such that it is dispersed over time. In addition, in an embodiment, one scan line 312 is selected 1
In the horizontal scanning period, the application period of the data voltage ± V _D / 2 is adjusted according to the display color of the pixel and the polarity of the selection voltage to the scanning line to obtain a data signal.
A voltage corresponding to the display color of the pixel and the polarity of the selection voltage may be used as the data signal. That is, instead of pulse width modulation,
The gradation display may be performed by voltage modulation. further,
In the embodiment, the writing polarity of the liquid crystal capacitor is inverted every vertical scanning period. However, the present invention is not limited to this. For example, the writing polarity may be inverted in a period of two vertical scanning periods or more.

In the panel 100 described above, T
The FD 220 is connected to the data line 212 and the pixel capacitance 118 is connected to the scanning line 312. On the contrary, the TFD 220 is connected to the scanning line 312 and the pixel capacitance 118 is connected to the data line 212. May be connected to the respective sides. Further, the TFD 220 is an example of a two-terminal switching element.
In addition to a device using a varistor, an MSI (Metal Semi-Insulator), or the like, a device in which two of these devices are connected in series or parallel in the opposite direction can be used as the switching device.

Further, in the embodiment, the case where the liquid crystal is of the TN type or the STN type has been described.
N-type (Bi-stable Twisted Nematic) type, ferroelectric type and other bistable types with memory properties, polymer dispersed type,
A dye (guest) having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of a molecule is dissolved in a liquid crystal (host) having a fixed molecular arrangement, and the dye molecules are arranged in parallel with the liquid crystal molecule. Alternatively, a guest-host type liquid crystal may be used. In addition, the liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. Also, when no voltage is applied, the liquid crystal molecules are arranged horizontally with respect to both substrates,
Parallel (horizontal) alignment (homogeneous alignment) in which liquid crystal molecules are aligned perpendicular to both substrates when voltage is applied
It is good also as composition of. As described above, in the present invention, it is possible to use various types of liquid crystals and alignment systems.

<Electronic Equipment> Next, some electronic equipment using the display device according to the above-described embodiment will be described.

<Part 1: Mobile Personal Computer> First, an example in which the above-described display device is applied to a display unit of a mobile personal computer will be described. FIG. 18 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1100
Has a main body 1104 having a keyboard 1102 and a panel 100 used as a display unit. Note that a backlight for ensuring visibility in a dark place is provided on the back surface of the panel 100, but is not shown in the appearance, and is not shown.

<2: Mobile Phone> Next, an example in which the above-described display device is applied to a display unit of a mobile phone will be described. FIG. 19 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1200 includes the above-described panel 100 in addition to a plurality of operation buttons 1202, an earpiece 1204, and a mouthpiece 1206. Note that a backlight (not shown) is provided on the back surface of the panel 100 in order to ensure visibility in a dark place.
However, in order to extend the standby time, the panel 100 is of a reflective type that does not require the backlight to be constantly turned on.
Alternatively, it is desirable to use a transflective type that transmits some light and reflects some light.

<Part 3: Digital Still Camera> Further, a digital still camera using the above-described display device as a finder will be described. FIG. 20 is a perspective view showing the back of the digital still camera. While a normal silver halide camera exposes a film with an optical image of a subject, a digital still camera 1300 generates an image signal by photoelectrically converting an optical image of the subject by an image sensor such as a CCD (Charge Coupled Device). Is what you do.

Here, the back of the case 2202 of the digital still camera 1300 is attached to the panel 10 described above.
0 is provided, and display is performed based on an image pickup signal by a CCD. For this reason, the panel 100
It will function as a viewfinder that displays the subject. Note that, also in the digital still camera 1300, a backlight for ensuring visibility in a dark place is provided on the back of the panel 100 (not shown).

A light receiving unit 1304 including an optical lens and a CCD is provided on the front side (the rear side in FIG. 19) of the case 1302. Here, the photographer checks the subject image displayed on panel 100,
When the shutter button 1306 is pressed, the imaging signal of the CCD at that time is transferred and stored in the memory of the circuit board 1308. Note that this digital still camera 13
In 00, a video signal output terminal 1312 and an input / output terminal 1314 for data communication are provided on the side surface of the case 1302 for external display.

<Summary of Electronic Equipment> In addition to the electronic equipment described with reference to FIGS. 18, 19 and 20, a liquid crystal television, a viewfinder type / monitor direct-view type video tape recorder, Examples include a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device having a touch panel. It goes without saying that the display device according to the embodiment is applicable to these various electronic devices.

[0093]

As described above, according to the present invention, it is possible to eliminate the need for voltage adjustment when a display device is incorporated in an electronic device, thereby preventing the process from becoming complicated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a configuration of a panel in the display device.

FIG. 3 is a partial cross-sectional view showing a configuration when the panel is broken in the X direction.

FIG. 4 is a partial perspective view showing a configuration when the panel is broken in a Y direction.

FIG. 5 is a partially cutaway perspective view showing a pixel configuration of the panel.

FIG. 6 is a block diagram showing a configuration of a Y driver in the display device.

FIG. 7 is a timing chart for explaining the operation of the Y driver.

FIG. 8 is a block diagram showing a configuration of an X driver in the display device.

FIG. 9 is a timing chart for explaining the operation of the X driver.

FIG. 10 is a timing chart for explaining the operation of the X driver.

FIG. 11 is a block diagram showing a configuration of a power supply circuit in the display device.

FIG. 12 is a diagram illustrating an operation of an inversion circuit in the power supply circuit.

FIG. 13 is a circuit diagram showing a configuration of a voltage forming circuit in the power supply circuit.

FIG. 14 is a timing chart for explaining the operation of the voltage forming circuit.

FIG. 15 is a diagram for explaining the relationship between the effective voltage value applied to the pixel capacitance and the optical density passing through the pixel capacitance in the display device.

FIG. 16 is a diagram showing a connection between a voltage data writing device and a display device in the display device.

FIG. 17 is a flowchart showing an operation of writing (writing) of voltage data by the writing device.

FIG. 18 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the display device is applied.

FIG. 19 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the display device is applied.

FIG. 20 is a perspective view showing a configuration of a digital still camera as an example of an electronic apparatus to which the display device is applied.

[Explanation of symbols]

 100 liquid crystal panel 105 liquid crystal 116 pixel 118 pixel capacitance 200 element substrate 212 data line 220 TFD 234 pixel electrode 250 X driver (data line drive circuit) 300 ... counter substrate 312 ... scanning line 350 ... Y driver (scanning line drive circuit) 500 ... power supply circuit 522 ... memory 530 ... voltage generation circuit 540 ... inversion circuit 600 ... adjustment device 1100 ... personal computer 1200 …… Mobile phone 1300 …… Digital still camera

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680G (72) Inventor Atsuya Tsuda 3-5-5 Yamato, Suwa City, Nagano Prefecture No. Seiko Epson Corporation F-term (reference) 2H093 NA16 NA32 NC02 NC09 NC11 NC28 5C006 AA01 AA02 AA21 AC24 AF01 BB16 BC11 BC16 BC20 BF01 BF27 BF42 FA20 5C080 AA10 BB05 DD28 FF11 GG02 GG07 GG04 JJ04 KK04 JJ04 KK03 JJ04 KK04 JJ04 KK03

Claims (8)

[Claims] 1. A pixel capacitor whose optical density changes according to an applied voltage, and a switching element that is turned on when the applied voltage exceeds a threshold value are connected in series between a scanning line and a data line. A display device including a pixel, wherein for one scanning line, a selection voltage for turning on a switching element of a pixel belonging to the one scanning line regardless of a voltage of a data line is applied to another scanning line. And a scanning line driving circuit for selecting and supplying a non-selection voltage for setting a switching element of a pixel belonging to the other scanning line to a non-conducting state regardless of the voltage of the data line; And the lighting voltage when the pixel capacitance of the pixel corresponding to the scanning line to which the selection voltage is supplied is to be turned on, and the non-lighting voltage when the pixel capacitance is to be turned off,
A data line driving circuit for supplying the one data line, a storage unit for storing voltage data in advance, and generating a voltage corresponding to the voltage data stored in the storage unit, and driving the voltage to the scanning line. A display device, comprising: a voltage generation circuit that supplies the selection voltage to a circuit. 2. The display device according to claim 1, wherein the storage unit is formed on an IC chip integrated with a part or all of the power generation circuit. 3. An inverting circuit for inverting the polarity of the voltage generated by the voltage generating circuit based on an intermediate value between the lighting voltage and the non-lighting voltage, wherein the scanning line driving circuit is configured to output the voltage generated by the voltage generating circuit or 2. The display device according to claim 1, wherein one of the voltages by the inverting circuit is alternately selected every one or more vertical scanning periods as the selection voltage to be supplied to the one scanning line. 4. An electronic apparatus comprising the display device according to claim 1. 5. A pixel capacitor whose optical density changes according to an applied voltage, and a switching element that is turned on when the applied voltage exceeds a threshold value, are connected in series between the scanning line and the data line. For one scanning line, a selection voltage for turning on a switching element of a pixel belonging to the one scanning line regardless of a voltage of a data line is provided, and for another scanning line, A non-selection voltage for setting the switching element of the pixel belonging to the other scanning line to a non-conduction state regardless of the voltage of the data line is selected and supplied, respectively, while one data line and the scanning line supplied with the selection voltage are provided. When the pixel capacitance of the pixel corresponding to and is to be turned on, the lighting voltage is used.
A power supply circuit that generates at least a voltage selected as the selection voltage for a display device that supplies the one data line, a storage unit that stores voltage data in advance, and a voltage that is stored in the storage unit. A power supply circuit for a display device, comprising: a voltage generation circuit that generates a voltage corresponding to data and supplies the voltage to the scan line driving circuit as the selection voltage. 6. A series connection between a scanning line and a data line, a pixel capacitor whose optical density changes according to an applied voltage, and a switching element which is turned on when the applied voltage becomes higher than a threshold value. A driving circuit of a display device for driving the pixels, wherein for one scanning line, a selection voltage for turning on a switching element of a pixel belonging to the one scanning line regardless of a voltage of a data line; A scanning line driving circuit for selecting and supplying a non-selection voltage for setting a switching element of a pixel belonging to the other scanning line to a non-conduction state regardless of a voltage of a data line, A lighting voltage when the pixel capacitance of a pixel corresponding to one data line and the scanning line to which the selection voltage is supplied is to be in the on display state, and a non-lighting voltage when the pixel capacitance is to be in the off display state,
A data line driving circuit for supplying the one data line, a storage unit for storing voltage data in advance, and generating a voltage corresponding to the voltage data stored in the storage unit, and driving the voltage to the scanning line. A driving circuit for a display device, comprising: a voltage generating circuit that supplies the selection voltage to a circuit. 7. A pixel element provided corresponding to the intersection of a scanning line and a data line, and having a optical density that changes according to an applied voltage, and a switching element that becomes conductive when the applied voltage exceeds a threshold value. And a method of driving a display device that drives pixels connected in series, wherein a voltage corresponding to voltage data stored in advance is generated, and switching of pixels belonging to the one scanning line is performed for one scanning line. As the selection voltage for turning on the element, the generated voltage is selected and supplied, and the pixel capacitance of the pixel corresponding to one data line and the scanning line to which the selection voltage is supplied should be turned on. In this case, the lighting voltage is used.
A driving method for a display device, wherein the driving method supplies the data to the one data line. 8. A method according to claim 1, wherein said voltage data is stored in correspondence with a selection voltage at which a ratio between an optical density of a pixel capacitor in an on-display state and an optical density of a pixel capacitor in an off-display state is maximized. Characteristic driving method of a display device.