JP2002359642A - Stm mapping device and stm mapping method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to insert idle frames and conduct packet read processing at a faster speed by suppressing the increase of circuit scale. SOLUTION: A packet data arrangement control circuit 1 is provided with FIFO memories 19-11-19-1M-19-N1-19-NM that store data bytes in M-byte width resulting from parallel processing applied to variable length packets in the unit of M sets without a gap by each logical channel in a state that pad bytes between user packet frames of the variable length packet are eliminated. An updated storage byte number Q is updated and calculated according to expression of Q=Q+W-R newly based on a written data byte number W stored in all the FIFO memories of the logical channel, a read data byte number R read therefrom, and a stored byte number Q.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an STS (Synchronous
ous Transport Signal) frame or STM (Synchronou
ST that performs a mapping process for storing a data frame and an idle frame (Idle Frame) in a predetermined physical channel in a payload of a s Transfer Module) frame.
The present invention relates to an M mapping circuit and an STM mapping method.

[0002]

2. Description of the Related Art The traffic volume of information communication is required to increase. Due to an increase in traffic volume, the transmission speed of a communication line tends to be higher. The transmission speed is limited by a signal processing speed such as an LSI processing speed and a data transfer speed between devices. In order to increase the speed, a technique of processing received signals by developing them in parallel has been adopted. For example, when a signal is received from a communication line having a transmission rate of 2.488 Gbps, the received signal is transmitted in 64 bits.
If it is expanded in parallel to a signal of 38.88 Mbps in a book,
The received signal can be handled at a speed that can be sufficiently processed.

[0003] A fixed-length packet has a large overhead such as a header, and the transmission efficiency is reduced. A technique for increasing the transmission efficiency by making the transmission frame a variable length is known from WO 96-26582. PPP
When processing variable-length packets having different data lengths for each packet, such as (Point to Point Protocol), the transmission device converts the variable-length packets to ATM (Asynchronous Tras).
(nsfer Mode) Switching processing is performed by dividing into small packets of fixed length such as cells.

[0004] A processing technique has been proposed and known in which variable length packets are handled as they are without being divided into fixed length packets by standardization work such as T1X1 to reduce overhead and improve transmission efficiency. Such processing techniques include GFP (Generic Framing Procedure), SD
Processing techniques such as L (Simple Data Link) are known.

FIG. 13 shows a GFP packet format. FIG. 13A shows a GFP frame that stores a user packet and a control packet. In this specification, this GFP frame is called a user packet frame. Such a packet format is stored in the payload area of the SDH frame and transferred between the devices. The user data (User Data) area 101 accommodates variable length data, and its packet length is PLI (PDU Le).
ngth Indicator) area. Core header
The length of the (Header) portion is not included in the PLI value and is defined as a fixed length of 4 bytes. FIG.
3A illustrates an idle frame 103 that is inserted in the user data area 101 and inserted to fill a space between one adjacent user packet frame and another user packet frame. The length of the idle frame is 4 bytes, and its data pattern is “0”.
000000h "or" B6AB31E0h ".

[0006] Among communication devices that handle variable-length packet frames, in order to reduce the amount of memory in the device, S
When extracting a GFP frame or an SDL frame from a TM frame, in the process of discarding the idle frame and storing it again in the STM frame at the output side, a processing mode in which an idle frame is inserted between GFP frames is often adopted. .

FIGS. 14 (a) and 14 (b) and FIGS.
(B) shows an array of variable length data. FIG.
(A), (b) and FIGS. 15 (a), (b) correspond to 1 in FIG.
They are connected by dotted lines. 14 (a) and 14 (b)
Shows a GFP frame sequence extracted from an STM frame by a device that processes a signal in parallel with a 4-byte width (32-bit width). It is assumed that the data sequence advances in the direction of the arrow in the figure. The first user packet frame is formed of bytes p1-1 to p1-25, and the number of bytes is 25. The second user packet frame is formed of bytes p2-1 to p2-26, and the number of bytes is 26. The third user packet frame is formed from bytes p3-1 to p3-23, and the number of bytes is 23. Between the first user packet frame and the second user packet frame,
Two idle frames (total of 8 bytes) are inserted, and three idle frames (total of 12 bytes) are inserted between the second user packet frame 2 and the third user packet frame. These bytes are rearranged inside the device as shown in FIGS. 15A and 15B, and a signal SOP (Start of P) indicating the head of a user packet is displayed.
a) and a signal EOP (Endof) indicating the end of the user packet.
Packet), and performs switching processing in these signal formats.

[0008] The type of a user packet frame is distinguished for each destination of a user packet signal by its payload header, and such a type is called a logical channel. When the first user packet frame to the third user packet frame shown in FIG. 14A and FIG. 15A have different payload headers, this data signal sequence is formed by three logical channels. When the first to third user packet frames have the same payload header, this data signal sequence is formed by one logical channel. Next, by rearranging the bytes of the user packet frames shown in FIGS. 14A and 15A as shown in FIGS. 14B and 15B, the head of each user packet is obtained. The first byte of a signal sequence in which byte data is expanded in parallel (Fig. 1
4 (a) and the byte of the row indicated by Byte 0 in FIG. 15 (a), respectively, and the beginning of the user packet becomes clear, which facilitates subsequent processing. For example,
When a predetermined fixed-length bit pattern is inserted at the head of the user packet, byte 0 (Byte 0)
, The bit pattern can be easily detected. Further, 4-byte data processed at a time by parallel expansion (Byte in FIG. 15A)
Since 0 to Byte3) does not include data for a plurality of user packets, processing operations such as switching processing are facilitated.

A pad byte (Pad Byte) is inserted and added to the end of the user packet frame, and the length of each user packet frame is converted to an integral multiple of the number of signals to be expanded in parallel. Such conversion has a role of adjusting the data width, and is configured by a predetermined repeating pattern of “0” and “1” or a pattern of all “0”, and the pad byte itself has a logical value. It is not meant to have any meaning. Also, the pad byte length is not included in the PLI value.

After the switching process is performed in such a signal format, a process of storing the GFP frame in the STM frame again is performed, and the user packet is transmitted to the transmission path. When there is a time interval between a user packet frame of a GFP frame and another user packet frame, an idle frame is inserted in frame units (4 byte units). Pad bytes are removed.

FIG. 16 illustrates a configuration example of a transmission frame. STS-n is a SONET (Synchronous Opti
cal Network). STM-n is an SDH (Synchronous Digital Hie)
(rarchy). As shown in FIG. 16, the STS transmission frame and the STM
Of the transmission frame, the SOH (Section Over Hea)
d) Area 103 and AUPTR (Administrative Unit Poi)
nter) area 104 is provided, followed by a payload area 105. For example, STM-1
6 is 48 AU (Administrative Unit) -3 (5
1.84 Mbps), and if the AU-3 is defined as one physical channel, the payload area 105
Stores data for a maximum of 48 physical channels. In the payload area 105, byte data of the physical channel is stored in the order of the arrows shown in FIG. Note that each row in FIG. 16 is composed of 8 bits (1 byte), and data of one physical channel is transmitted one byte at a time on the transmission path with one clock. In the conventional STM frame payload, a processing unit in which unit frames such as VC-3 and VC-4 are sequentially stored is a technical term representing the present invention. This is called a logical channel, which is a packet type that is distinguished for each destination of the packet header.

FIG. 17 shows an STM mapping circuit assumed to further improve the technique described in Japanese Patent Application No. 2001-093570 to perform queue length management. Such a circuit is provided with a technique for performing a mapping process for storing data in a transmission frame while allocating data to a predetermined logical channel in byte units. The STM mapping circuit detects the packet length of the input user packet data, and is an M-bit byte indicating whether the data is valid byte data for each byte developed in parallel or not (an inserted pad byte). A packet length detection circuit 111 for generating validity information, a routing circuit 112 for generating routing information for controlling routing processing by an M × M switch 113 described later,
M for every N logical channels (N is a positive integer of 48 or less)
Mx to distribute byte data to M output ports
An M switch 113 and N packet filter circuits 114-1 to 114-N which receive packet data input simultaneously with the user packet data and processed on the own logical channel based on a channel number signal indicating a mapping destination of the user packet data. And M × N packet memories 115-11 to 111 composed of M FIFO (First-in First-out) memories per channel for temporarily storing the packet data distributed by the M × M switch 113.
15-NM and the packet data stored in the packet memory 115.
-11 to 115-NM, a memory write control circuit 116-1 to 116-N, a channel control memory 117 for storing which logical channel is assigned to a physical channel of the STM frame, and a channel control memory 117.
And the logical channel information signal 119 for outputting packet data output from the memory read control circuits 118-1 to 118-N from the channel control memory 117. M × M switches 120-1 to 120-N that perform switching in byte units based on the above, and an idle frame generation circuit 121-1 that monitors the number of bytes stored in the packet memory for each logical channel and generates an idle frame if 0. To 121-N and the selector circuit 1
22-1 to 122-N and M × M switches 120-1 to
Selector circuits 123-1 to 123- that selectively output the output of 120-N in byte units based on the logical channel information signal 119 output from the channel control memory 117.
N.

The routing circuit 112 receives the packet data, byte validity information, channel information signal, SOP signal, and EOP signal output from the packet length detection circuit 111. The packet length detection circuit 111 outputs routing information, a logical channel number, the number of write bytes, a routing last port number, SOP, and EOP. The M × M switch 113 removes pad bytes from the packet frame for each logical channel, and stores the packet memory 11 of the logical channel X (X is an integer of 1 or more and N or less).
5-X1 to 115-XM, 115-X1, 115-X2,
.. 115-X3... 115-XM. The packet memories 115-X1 to 115-XM can read from the same logical channel in byte units from 0 to M bytes in one clock in order to allocate an arbitrary logical channel to the physical channel of the STM frame. In this case, each byte is composed of an independent FIFO memory.

The channel control memory 117 stores logical channel numbers 1 to N for storing the physical channels of the STM frame with the number of physical channels as one cycle. Memory read control circuit 1 for each logical channel
23-1 to 123-N are 115-X1, 115-X2,
... Data is read out one byte at a time in the order of 115-X3. Packet memory 115-X1-1
The total number of bytes stored in the packet memories 115-X1 to 115-XM is calculated for each logical channel for each logical channel from the number of writes and the number of reads of the 15-XM, and if 0, the idle frame generation circuit 121-X An idle frame is generated, selectively output by the selector circuit 122-X, and selectively output by the selector circuits 123-1 to 123-M.
The byte signal for each logical channel is multiplexed. The select signals in the selector circuits 123-1 to 123-M selectively output the logical channels 1 to N according to the channel information of the corresponding byte using the logical channel information signal.

As shown in FIGS. 18 and 19, the idle frame generation circuits 121-1 to 121-N having a queue length management circuit have packet memories 115-1 to 115-N.
The number of bytes of the idle frame is calculated by calculating the number of bytes for each logical channel stored in the idle frame, and if the number of bytes is 0, it is determined whether the transmission of the 4-byte idle frame has not been completed halfway. It is determined whether to output from. Also, in the next one clock, the number of bytes set as the output byte for the own logical channel in the channel control memory is identified. If the number of stored bytes is small, how many bytes should be read from the packet memory? Is determined, and how many bytes are to be used as idle frames.

The idle frame insertion circuits 121-1 to 121-N of the proposed STM mapping circuit are
It is required that the processing speed be further increased without increasing the circuit scale. The circuit added to perform a series of processes continuously at each clock does not become complicated,
When realizing high-speed processing with digital logic circuits, there is no limitation on the number of logic stages that can be processed by one clock and the operating speed, and a technology has been established that can suppress an increase in circuit scale when increasing the number of parallel expansions. Desired.

It is required that the processing of inserting an idle frame and reading a packet be speeded up. Further, in order to speed up the insertion of the idle frame and the reading of the packet, it is desired to be able to suppress an increase in the size of the circuit for inserting the idle frame and reading the packet.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to provide an STM mapping apparatus which can speed up the processing of inserting an idle frame and reading out a packet. Another object of the present invention is to provide an STM mapping apparatus capable of suppressing an increase in the size of a circuit for inserting an idle frame and reading a packet in order to speed up insertion of an idle frame and reading of a packet. To provide.

[0019]

Means for solving the problem are described as follows. The technical items appearing in the expression are appended with numbers, symbols, and the like in parentheses (). The numbers, symbols, and the like are technical items that constitute at least one embodiment or a plurality of the embodiments of the present invention, in particular, the embodiments or the examples. Corresponds to the reference numerals, reference symbols, and the like assigned to the technical matters expressed in the drawings corresponding to the above. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or the examples.

The STM mapping apparatus according to the present invention comprises a packet memory (19-1 to 19-N) for storing data bytes obtained by expanding a variable-length packet for each clock, and a packet memory (19-11 to 19) for storing data bytes. -N
M) for each clock. Packet memory (19-11 to 19-
NM) includes M FIFO memories (19-11 to 19-NM) each formed independently for each logical channel indicating the type of a variable-length packet. The control circuit includes a queue length management circuit (23-1 to 23-N) that outputs a determination signal indicating at each clock that the number of data storage bytes for each logical channel is less than a threshold, and a FIFO.
A generation circuit for generating an M-byte idle frame to be written to a FIFO memory (19-11 to 19-NM) having a byte number next to the byte number of the data byte last stored in the memory (19-11 to 19-NM) (24-1 to
24-N) and selector circuits (25-1 to 25-N) for selectively outputting the M-byte idle frame to the packet memory based on the determination signal.

When the number of bytes of data stored is managed and the amount of memory is equal to or less than the appropriate amount, an idle frame is written in units of M bytes. High-speed writing and reading are safely controlled while suppressing an increase in scale, and the advantage of controlling the writing order can be more effectively utilized. Writing idle frames to the FIFO memory without gaps between successive variable-length packets suppresses an increase in circuit size.

Queue length management circuit (23-1 to 23-N)
The management of the appropriate amount of the
The number of write bytes W of M data bytes held in the FO memory (19-11 to 19-1M) and the FIFO
Based on the read byte count R of the M data bytes read from the O memory (19-11 to 19-1M) and the storage byte count Q, the data storage byte count is newly calculated by Q = Q + WR. Is calculated every clock. Data bytes are subtracted every clock in units of M bytes, and the accumulated amount is managed in a time range of one clock. Such management ensures its security.

Queue length management circuit (23-1 to 23-N)
Indicates that the number of data storage bytes is less than the set threshold, and
If the input state of the logical channel is a section state between variable length packets, a select signal IDL = 1 is output. If the input state of the logical channel is in the middle of a user packet frame, a select signal IDL = 0 is output. The queue length management circuits (23-1 to 23-N) include a selector circuit (2
5-1 to 25-N). The selector circuits (25-1 to 25-N) store the idle frame based on the select signal IDL = 1 in the packet memory (19-1).
To 19-N). If the select signal IDL = 1 is output, M is added to the number of stored data bytes, and the queue length is dynamically and correctly managed.

The selector circuits (25-1 to 25-N)
A user packet frame signal having a width of M bytes and byte validity information indicating which byte of the M bytes is a valid user packet frame based on the select signal IDL, and generation circuits (24-1 to 24-N) Selectively output the idle frame signal and the byte validity information that are output.

Queue length management circuit (23-1 to 23-N)
Performs a magnitude comparison between the number Q of update storage bytes and the set threshold Qbp, outputs a back pressure signal BP [X] = 0 for each logical channel if Q ≦ Qbp, and outputs a back pressure signal BP [X] = 0 for Q> Qbp. Back pressure signal BP
[X] = 1 is output. The function of the queue length management circuits (23-1 to 23-N) for managing the distribution and amount of data bytes can be used as it is for back pressure control such as control timing of a preceding or subsequent circuit. .

Queue length management circuit (23-1 to 23-N)
Is the number of update storage bytes Q and the maximum memory length Qma
x, and if Q ≦ Qmax, a memory overflow alarm signal OFALM for each logical channel
[X] = 0 is output, and if Q> Qmax, a memory overflow alarm signal OFALM for each logical channel is output.
[X] = 1 is output, and the size of the updated accumulated data byte number Q is compared with 0. If Q ≧ 0, the memory underflow alarm signal UFALM for each logical channel is output.
[X] = 0 is output, and if Q <0, the memory underflow alarm signal UFALM [X] =
Outputs 1. The function of the queue length management circuits (23-1 to 23-N) for managing the distribution and amount of data bytes can be used for security management as it is. The queue length management circuits (23-1 to 23-N) determine whether the memory underflow alarm signal UFALM [X] is set to 0 or 1 based on the number Q of updated accumulated bytes, and select signal IDL. Signal is set to 0 or 1 by the EOP signal and S
The determination is made in parallel based on the OP signal.

The STM mapping apparatus according to the present invention
Memory area formed by byte width (19-1 to 19-
N: FIG. 8), a first step of writing data bytes of a variable length packet without gaps, a second step of counting the number Q of data bytes written in the memory area, and a step of counting the number Q of data bytes when the number Q is less than a set threshold. A third step of writing an M-byte idle frame in the memory area without any gap between the preceding and succeeding variable length packets. The number Q is a number calculated by Q = Q + WR based on the number R of data bytes written to the memory area and the number of data bytes read from the memory. An M byte wide data byte is read and written every clock, and the number Q is calculated every clock. The set threshold value is represented by Qbp. If Q ≦ Qbp, a back pressure signal BP [X] = 0 is output for each logical channel. If Q> Qbp, a back pressure signal BP [X] = 1 is output for each logical channel. Is added.

1 byte width × M FIFO memories holding M byte wide (M is a multiple of 4 and a power of 2) data bytes obtained by parallelizing one variable length user packet frame for each logical channel By controlling the reading of the packet memories (19-1 to 19-N) which are formed and hold the packets in the FIFO memory without gaps in a state where the pad bytes between the user packet frames are removed, in a predetermined order. Packet memory (19-1)
-19-N), the data bytes of an arbitrary logical channel are mapped to the physical channels set in the STM frame, and the packet data is output.

For each logical channel, the queue length management circuits (23-1 to 23-N) monitor the number of stored bytes, and the number of stored bytes is smaller than the set threshold value Qidl, and the logical channel is one of the logical channels. During the period between the user packet frame and the next user packet frame, not during the reception of the user packet frame, the idle frame insertion signal IDL = 1 is generated, and the user packet frame and the idle frame generation circuit (24-1) are generated. ~ 24-N)
Is selected by the selector circuits (25-1 to 25-N) based on the signal IDL, and the packet memory (19-1 to 21-N) is selected by the memory write control circuits (21-1 to 21-N). 19-N). Furthermore, since high-speed processing can be performed, the number of parallel expansions does not need to be increased, and an increase in the number of circuits can be suppressed.

Queue length management circuit (23-1 to 23-N)
Means that the number of stored bytes Q for each channel is equal to the set threshold Qidl
It is determined whether the SOP signal is less than
The number of processing stages can be reduced only by determining whether or not a signal is between user packet frames from a signal, so that the circuit can be reduced in size and speed. A method of writing empty cells from the entrance side of a memory is disclosed in Japanese Patent Application Laid-Open No. H11-55267.
This is a method of inserting an empty cell in a fixed-length packet such as an ATM, and the first byte of the empty cell does not shift to a different byte number in the memory.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
The embodiment of the M mapping device is exemplified as an STM mapping device that maps packet data to STS-48, and a packet data distribution control circuit is provided together with a packet data input circuit and a packet data output circuit. As shown in FIG. 1, the packet data array control circuit 1 that executes control for physically arranging the data bytes of the packet data in parallel is composed of N packet data array control circuits 1-1 to 1-N. It is configured. The packet data input circuit 2 is inputly connected in parallel to the packet data array control circuits 1-1 to 1-N. Packet data array control circuits 1-1 to 1
-N is connected in parallel to the packet data output circuit 3 in output.

The packet data input circuit 2 includes a packet length detection circuit 4, a routing circuit 5, and an input M × M switch 6. The user packet frame data sequence 7 is input to the packet length detection circuit 4. M is
A multiple of 4 and a power of 2 (example: 4, 8, 1
6,...). The input user packet frame data sequence 7 includes a user packet frame sequence 9, a logical channel signal 11, an SOP 12, and an EOP 13, which are input to the packet length detection circuit 4.

The packet length detection circuit 4 calculates each user packet frame length of the user packet frame sequence 7 from the PLI area of the core header portion, and each byte of the parallel-developed input signal sequence 7 is a valid user packet frame. Or byte validity information 1 indicating whether it is a pad byte instead of a user packet frame
4 is generated and output. The byte validity information 14 is composed of M bits. The user packet frame 9 having the M-byte width is output from the packet length detection circuit 4 together with the logical channel signal 11, the SOP 12, the EOP 13, and the byte validity information 14, and is input to the routing circuit 5.

The routing circuit 5 includes an M × M switch 6
Generates routing information 15 for controlling the routing process, and further generates and outputs the number of write bytes 16 and the RT (routing) final port number 17.
The user packet frame sequence 9, the byte validity information 14, and the routing information 15 are
The input M × M switch 6 is input together with OP12, EOP13, and the number of write bytes 16. The input side M × M switch 6 rearranges the user packet frames 9 based on the routing information 15.

N packet data array control circuit 1-1
To 1-N respectively correspond to the packet filter circuit 18-.
1 to 18-N. Packet filter circuit 18
-1 to 18-N determine the logical channel number of the logical channel to which the user packet frame belongs based on the payload header portion of each user packet frame 9, and perform packet data 9-NM processing on the own logical channel.
Can be captured.

Packet data array control circuits 1-1 to 1--1
N is M × N channels formed from M independent (First-in First-out) memories that temporarily store an M-byte-wide user packet frame (M-byte-wide data) 9 and an idle frame. Packet Memory 19-1M
~ 19-NM. The one-channel packet memory 19-1 includes eight memory elements 19-11 to 19-1M corresponding to eight bytes.

The packet data array control circuit 1 includes memory write control circuits 21-1 to 21-N. The memory write control circuits 21-1 to 21-N execute control to write each data byte of a user packet frame and an idle frame to the packet memories 19-11 to 19-NM. The packet data array control circuit 1 includes a memory read control circuit 22-1. The memory read control circuit 22-1 includes packet memories 19-11 to 19-
The control for reading the user packet frame and the idle frame from the NM is executed.

The packet data array control circuit 1 includes queue length management circuits 23-1 to 23-N. The queue length management circuits 23-1 to 23-N include a packet memory 19-
The total number Q of data bytes of the user packet frame and the idle frame for each logical channel stored in each of the 11-19-NM is calculated for each logical channel for each clock, and the total number Q of bytes for each logical channel is calculated. Is less than or equal to the threshold Qidl, and the input user packet frame sequence to the logical channel is not in the middle of receiving one user packet frame, but in the state between the user packet frame and the next user packet frame. For example, the idle frame insertion signal IDL of the logical channel is output as IDL = 1. And
M is added to the total number of bytes Q of the logical channel, and this is set as a new total number of bytes Q.

The packet data array control circuit 1 includes idle frame generation circuits 24-1 to 24-N.
The packet filter circuits 18-1 to 18-N are respectively connected to the idle frame generation circuits 24-1 to 24-N and to the queue length management circuits 23-1 to 23-N. Idle frame generation circuit 2
4-1 to 24-N indicate, for each logical channel, the next byte number based on the routing last port number 17, which is the byte number detected as the last data byte when routing the last user data that has arrived last time. , An M-byte-wide idle frame is generated by shifting the bytes so that the first byte of the idle frame is stored in the physical position of the idle frame. Further, the idle frame generation circuit outputs an M bit width signal of all "1" as byte validity information.

The packet data arrangement control circuit 1 includes frame type selection selector circuits 25-1 to 25-N. The packet filter circuits 18-1 to 18-N are connected to the frame type selection selector circuits 25-1 to 25-N together with the idle frame generation circuits 24-1 to 24-N. Selector circuit for frame type selection 25-1
To 25-N are packet filter circuits 18-1 to 18-.
N and the idle frame output signals from the idle frame generation circuits 24-1 to 24-N, respectively.
Or selectively output based on 0). Similarly, regarding the byte validity information having the M-bit width, the packet filter circuit 18 based on the idle frame insertion signal IDL.
-1 to 18-N and signals output from the idle frame generation circuits 24-1 to 24-N are selectively output. Thus, the frame type selection selector circuit 25
User packet frames or idle frames selectively output by -1 to 25-N and byte validity information are input to the memory write control circuits 21-1 to 21-N.

A channel control memory 26 is provided. The channel control memory 26 stores which logical channel is allocated to the physical channel of the STM frame, and transmits a logical channel information signal 27 to the memory read control circuits 22-1 to 22-N. The packet data array control circuit 1 includes output-side M × M switches 28-1 to 28-N
It has. Output side M × M switches 28-1 to 28-
N switches data bytes stored in the packet memories 19-11 to 19-NM in byte units based on the logical channel information signal 27 output from the channel control memory 28.

Output side M × M switches 28-1 to 28-N
Are connected in parallel to the M selector circuits 29-1 to 29-M in terms of output. Selector circuits 29-1 to 29-
M selectively outputs data bytes output from the output side M × M switches 28-1 to 28-N in byte units based on the logical channel information signal 27 output from the channel control memory 26.

An M-byte user packet frame is input to the packet length detection circuit 4. The user packet frame is accompanied by a logical channel number (signal) 11, and user packets of different logical channels are multiplexed every clock even if one user packet of the same logical channel is not always continuous. Is also good.

The packet length detection circuit 4 has an M-bit data bit indicating whether the M data bytes forming the M width of user packet data of each logical channel are valid data or invalid data (pad byte). Byte validity information 14
Has been generated. The header part of each arriving user packet frame is detected.
The byte length of the entire user packet is obtained from the LI value (see FIG. 13), and validity / invalidity can be determined from the value. The routing circuit 5 generates, based on the byte validity information 14, routing information 15 for rearranging the data bytes from the 0th byte to the M−1th byte into the 0th to M−1th bytes.

FIG. 2 shows the routing circuit 5 shown in FIG. 1 in detail, and 8 is exemplarily used as the signal byte width M. The routing circuit 5 counts the number of valid data based on the byte validity information 14 corresponding to each data byte for each byte row (the 0th row to the 7th row). −
7 is provided. The routing circuit 5 includes a routing result memory 32. The routing result memory 32 stores logical channels 1 to N in order to perform time-division processing of N logical channels by one routing circuit 5.
Holds the last byte corresponding signal indicating in which byte in the M ports the last data has been written.

The routing result memory 32 is bidirectionally connected to the memory control circuit 33. Memory control circuit 3
3 reads and outputs the last routing result of the logical channel N from the routing result memory 32 based on the channel number 11 input simultaneously with the user packet frame. Effective byte count circuit 31-1
To 31-7 are an adder 35 together with the memory control circuit 33.
-0 to 35-7. Adders 35-0 to 35
-7 adds the output signal 34 of the memory control circuit 33 and the output signal of the effective byte count circuit. The valid byte count circuit 31-7 at the last stage adds all the valid bytes from byte 0 to byte 7, counts the total valid bytes, and outputs the total valid bytes.

The total number of valid bytes is calculated by the adder 35-7.
Is added to the output signal 34 output from the memory control circuit 33. The added value output by the adders 38-1 to 38-8 is the routing information 3 corresponding to byte 0 to byte 7.
6-0 to 36-7. Last stage adder 3
5-7 indicates the added value as the routing final port number 1
7 is also output. When the sum exceeds M (= 8), M is subtracted from the sum and a value in the range of 0 to M-1 is output. Effective byte count circuit 31-7
Is output as the number of write bytes 16. The routing circuit 5, as described above,
Byte width user packet frame 9, SOP signal 1
2, EOP signal 13, routing last port number 1
7, the number of write bytes 16, the logical channel number 11, and the routing information 36-0 to 36-7 for each byte are output.

Based on the routing information 36-0 to 36-7 of the byte 0 to the byte M-1, the input M × M switch 6 adds the data byte of the input byte 0 to the byte M-1 of the user packet frame 9. The byte validity information and the number of write bytes 16 are rearranged into output bytes 0 to M-1. The rearrangement is performed such that the user packet frame data of the same logical channel is not FIFO-spaced with the user packet frame of the logical channel that arrived earlier.
It is performed so that it is stored in the file. Such rearrangement can also be realized by a known combination of 2 → 1 selector circuits or a known banyan switch.

Packet filter circuits 18-1 to 18-N
Is formed as a circuit that monitors the channel number signal 11 output from the input side M × M switch 6 and takes in the user packet frame 9 if the channel number signal 11 is its own logical channel number.

Packet memories 19-11 to 19-NM
Is a FIFO separated by M ports for each logical channel
(First-in First-out) memory, which stores M data bytes sequentially and outputs a maximum of M data bytes per clock. One FIFO has a width of one byte.

Memory write control circuits 21-1 to 21-N
Is a circuit for writing a user packet frame or an idle frame to the packet memories 19-11 to 19-NM, and in a certain logical channel, byte validity information = 1
Write for the byte. The channel control memory 26 is a memory for setting which logical channel is mapped to a physical channel constituted by VC-3 or VC-4 of the STM frame.

FIG. 3 illustrates the channel control memory 26 where M = 8. In the channel control memory 26, the logical CHs (channels) 1 to CH48 are divided into eight divisions of the logical channels 1 to 8 to form a correspondence relationship corresponding to the physical channels. Memory areas are provided in order from the lower left to the upper right for each of eight channels. As illustrated in FIG. 3, eight physical CH1 to physical CH8 are assigned to logical CH1, and five physical CH9
Physical CH13 is allocated to logical CH2, three physical CH14 to physical CH16 are allocated to logical CH3, eight physical CH17 to physical CH24 are allocated to logical CH4, and four physical CH25 to physical CH28 are allocated to logical CH5. And four physical CHs 29 to C
H32 is allocated to the logical CH6 and includes 12 physical CHs.
33 to physical CH44 are allocated to logical CH7, and four physical CH45 to physical CH48 are allocated to logical CH8.

From the channel control memory 26, logical channel information signals 27 for M (= 8) physical channels to be processed for each clock are output.
Is a binary number representing a logical channel number assigned to eight physical channels, for example, 8 bits × 8 signals of 6
Output in 4-bit width.

Memory read control circuits 22-1 to 22-N
Calculates the number of physical channels assigned to the own logical channel in one clock based on the logical channel information signal 27 output from the channel control memory 26, and obtains data bytes (user packet frame or idle frame) for the number of physical channels. To the packet memories 19-11 to 1
9-NM to 19-X1, 19-X2, 19-X3 ...
・ Read one byte at a time in the order of 19-XM. The byte number of the memory last read last time is memorized, and the data is read following the previously read data. After reading up to byte M-1, return to byte 0. Also,
The number of read bytes for each logical channel is output.

Output side M × M switches 28-1 to 28-N
Is based on a logical channel information signal 27 output from the channel control memory 26,
The user packet frame or the idle frame read out at 1 to 22-N is switched in byte units. Switching is performed using the position of the own logical channel in the logical channel information signal 27 output from the channel control memory 26 as an output port. The routing information for controlling the switching is self-generated in a table. The routing information includes the first byte numbers 0 to 7 of the packet memory from which reading is started this time and the logical channel information signal 2
7 and its own channel output position. For example, the table is stored in advance for each logical channel, and the table is searched for the head byte number and the output position of the own logical channel to obtain routing information.

FIGS. 4 and 5 illustrate such a routing table 81 with M = 4. FIG. 5 is connected by an alternate long and short dash line. Routing table 8 in FIGS.
1 has six columns from left to right. 6
The three columns are the output position of the own channel in the logical channel information signal 27 input from the channel control memory 26, the head memory number, the routing information for byte 0 of input port 0, and the routing information for byte 1 of input port 1. Information, routing information for byte 2 of input port 2, and routing information for byte 3 of input port 3.

The own CH output position can be obtained by comparing and checking the logical channel information signal and the own CH number. If the logical channel is 1, the logical channel information signal = ｛CH
1, CH1, CH2, CH3} have their own CH output positions of “1”.
100 "and if the logical channel is 2, its own C
The H output position is “0010”, and if the logical channel is 3, its own CH output position is “0001”. If the logical channel is 4, its own CH output position is “00”.
00 ".

The routing information is a 2-bit binary number. When the routing information is "00", switching is performed so that the packet is routed to the output port 0. When the routing information is "01", the switching is performed to the output port 1. Switching is performed so that routing is performed. If the routing information is “10”, switching is performed so that routing is performed to the output port 2. If the routing information is “11”, routing is performed to the output port 3. Switching is performed.

As an example, logical channel information signal = ｛C
H1, CH1, CH1, CH1}, and the case where the head memory number is 3 is considered next. The own CH output position of the logical channel 1 is 1111. If the head memory number is 3, switching is performed so that the data of byte 0 is output to the corresponding output port 1 according to the routing information “01”. Similarly, switching is performed so that the data of byte 1 is output to the corresponding output port 2 according to the routing information “10”, and the data of byte 2 is output to the corresponding output port 3 according to the routing information “11”. Is switched to byte 3
Is switched according to the routing information "00" so as to be output to the corresponding output port 0.

In the channels other than the logical channel 1, the own CH output position becomes 0000 and switching is performed so that the input port matches the output port. However, since the own byte number is 0, nothing is read from each packet memory, Is switched as 0.

As described above, the packet memories 19-11 to 19-1
9-NM, the output M × M switch 28−
The data bytes rearranged in the order of the output logical channels by 1-28-N are selected by the selector circuits 29-1 to 29-M.
And selectively multiplex the byte signals for each logical channel. A logical channel information signal 27 is used as a select signal, and logical channels 1 to N are selectively output according to channel information of a corresponding byte. Assuming that the number of logical channels N = 48, the physical channels 1 to 48 of the channel control memory
By setting 48 in order, logical channels 1 to 48 are sequentially mapped in the payload of the STM frame, and a payload portion of a 2.4 Gbps frame of VC-3 × 48 channels is generated.

Here, the queue length management circuits 23-1 to 23-23
−N calculates the number of bytes Q stored in the packet memory of each logical channel from the number of write bytes W and the number of read bytes R for each logical channel, and determines whether or not to insert an idle frame based on the size. Do. These processes are always performed every clock.

FIG. 6 shows a processing flow of the queue length management circuits 23-1 to 23-N provided for each logical channel. A byte type discrimination signal indicating whether the packet is in the middle of a user packet or between user packets for each logical channel,
It is defined as follows and represented by PSTAT. PSTAT = 0: The logical channel has completed reception of a user packet frame, and is in a state of a period between the next user packet frame and the logical channel. PSTAT = 1: The logical channel is in the process of receiving a certain user packet frame.

The idle frame insertion threshold is represented by Qidl. An idle frame insertion signal for inserting an idle frame is defined as follows and is represented by IDL. IDL = 0: No idle frame is inserted. IDL = 1: An idle frame is inserted.

The byte type discrimination signal PSTAT, the idle frame insertion threshold value Qidl, and the idle frame insertion signal IDL are initialized. Idle frame insertion threshold Q
idl is set variably (step A1). From the logical channel packet filter to the queue length management circuit,
The number of write bytes W of the logical channel is input for each clock. The number R of read bytes is input from the memory read control circuit to the queue length management circuit for each of the same clocks (step A2). Number of write bytes W
Is M, and W = 0 when there is no user packet frame to be written to the logical channel. Similarly, the maximum value of the number of read bytes R is M, and R = 0 is input when data is not read from the logical channel. W is added to Q and R is subtracted, and the number Q of data bytes stored in the packet memory of the logical channel is calculated as the number Q of updated storage bytes (step A3): Q = Q + WR

If PSTAT = 0 at that time, or if SOP = 0 (a state in which SOP = 1 is not received) and the number of data bytes Q is less than the threshold value Qidl (Yes in step A9) ), The number of data bytes Q is M
The number of bytes M of the idle frame corresponding to the byte width is added, IDL = 1 is set, and a selection signal for inserting the idle frame is output from the selector circuit (step A).
11).

On the other hand, if No (the byte is in the middle of the user packet or Q ≧ Qidl) in step A9, the data byte number Q is maintained as it is,
No idle frame is inserted as IDL = 0 (step A10). At this time, if SOP = 1 (Yes in step A4), PSTAT = 1 is set (step A8), and if EOP = 1 (Y in step A5).
es), PSTAT = 0 is set (step A7),
If SOP = 1 and EOP = 1 are not satisfied (No in step A5), the byte type determination signal PSTAT holds the PSTAT of the previous clock (step A6).

FIG. 7 shows an idle frame insertion circuit 24-
1 to 24-N are illustrated, and a case where M = 8 is illustrated. Based on the routing last port number, the idle frame formed from M consecutive idle bytes following the byte next to the byte number of the packet memory where the last data is stored in the logical channel is tightly packed. An idle frame pattern is generated from the idle frame generation circuit and output to the selector circuit.

The selector circuits 25-1 to 25-N operate only when the idle frame insertion signal IDL output from the queue length management circuits 23-1 to 23-N is "1". -N selects an 8-byte wide idle frame output, and if IDL = 0, selects and outputs 8-byte wide user packet data output by the packet filter circuit. Similarly, the selector circuits 25-1 to 25-N include a queue length management circuit 23-
Idle frame insertion signal ID output from 1 to 23-N
Only when L is 1, the idle frame generation circuit 2
8-bit width All "1" output by 4-1 to 24-N
Is selected, and if IDL = 0, 8-bit byte validity information output by the packet filter circuit is selected and output.

The queue length management circuits 23-1 to 23-N, the idle frame generation circuits 24-1 to 24-N, and the selector circuits 25-1 to 25-N reduce the number of bytes Q stored in the packet memory to Q < If Qidl, idle frames are inserted only between user packet frames and stored in the packet memory. The memory write control circuit
The packet frame and the idle frame are stored in the packet memory without distinction.

FIGS. 8 (a), (b), (c) and FIG.
(D) and (e) show how a user packet frame and an idle frame are stored in a packet memory, and the case where M = 8 is illustrated. FIG. 8 (a)
Indicates a state where the first user packet frame (P1 to P27: 27 bytes) and the second user packet frame (P2-1 to P2-36: 36 bytes) of the same logical channel arrive, and pad bytes are removed. It is still added without being added. FIG. 8B shows the accumulation state of the first user packet frame and the second user packet frame stored in the packet memory after the pad bytes have been removed. In this case, the Q value is equal to or greater than Qidl. FIG.
(C) shows a state in which the byte data of the user packet frame has been read from the packet memory and the Q value has become less than Qidl. The second user packet frame is formed of 36 bytes from P2-1 to P2-36, and the routing final port number is 6. Therefore, the idle frame generation circuit calculates "A"
B31E0B6AB31E0B6h "is generated.
Is the idle frame “AB31” thus generated.
E0B6AB31E0B6h "is selected by the selector circuit and sequentially written from byte 0 to byte 7 of the packet memory. When the Q value becomes equal to or more than Qidl by such writing, the idle frame insertion operation is stopped. I do.

By generating M bytes of idle frames, the difference in the number of accumulated bytes for each of bytes 0 to 7 does not change. In other words, even after the idle frame is inserted, the state of the last routing port number = 6 continues unchanged, and the next arriving user packet frame is packed without gaps by using the routing result memory 32 of the routing circuit 5 as it is. You can get in. Even if an idle frame is inserted, the routing result memory 32
And there is no need to provide a control signal or the like to the routing circuit 5. FIG. 9 (b) shows a further 8
This shows a state in which an 8-byte idle frame is further inserted when byte data of a user packet frame of bytes is read.

FIGS. 11 and 12 show the operation of reading data from the packet memory. FIGS. 11 and 12 are connected by an alternate long and short dash line. This is because M ×
3 shows output signals of M switches 28-1 to 28-N. FIG.
The three idle bytes {B6, AB, 31} of logical channel 1 in the idle frame temporally preceding the two idle frames in (b) are the time (or time width).
At time T + T + 2 and T + 3, which are output from the packet memory at T and time T + 1 and are controlled by the channel control memory, the remaining 12 idle bytes of the two idle frames of FIG. 10 idle frame bytes {E0, B6, AB, 31, E
0, B6, AB, 31, E0, B6} are read out.

According to such a reading method, the memory read control circuits 22-1 to 22-N and the output side M × M switches 28-1 to 28-N can discriminate neither user packet frames nor idle frames. It is only necessary to map data to the physical channel to which the own logical channel is allocated, and a complicated processing circuit required on the memory read side in the conventional example is unnecessary.

The STM mapping apparatus according to the present invention is further provided with three functions of packet memory back pressure control, memory overflow monitoring, and memory underflow monitoring by managing the number of stored bytes. The back pressure control is a control to be executed for a memory of a circuit in a preceding stage of the STM mapping circuit. When the BP signal = 1 is detected, the reading from the memory is stopped. Reading from the memory is resumed. Such control of reading suspension and resuming reading can avoid a memory overflow of the STM mapping circuit. On the other hand, the monitoring of the memory overflow and the monitoring of the memory underflow further enable the monitoring of the circuit failure.

The queue length management circuits 23-1 to 23-N calculate the number of data bytes stored in the packet memories 19-11 to 19-NM for each logical channel, and calculate the idle frame insertion signal IDL based on the calculated value. = 1, a function of outputting a back pressure signal BP [N: 1], a memory overflow alarm OFALM [N: 1], and a function of outputting a memory underflow alarm UFALM [N: 1].

Idle frame generation circuits 24-1 to 24-24
-N is, as described above, based on the routing last port number in which the last byte of the previously arriving user packet frame is routed and the byte number is indicated.
M / 4 idle frames of M bytes in width are generated such that the first byte of the idle frame is stored in the next byte number.

FIG. 10 shows a processing flow of the queue length management circuit provided for each logical channel. A byte type discrimination signal indicating whether the state at that time is in the process of receiving one user packet frame for each logical channel or in a section between a certain user packet frame and the next user packet frame is PSTAT
(0: between two user packet frames, 1: during reception of a user packet frame), an externally set idle frame insertion threshold is expressed by Qidl, and an idle frame insertion signal is IDL (0: not inserted,
1: Insert), the number of accumulated data bytes is represented by Q, and the maximum number of accumulated bytes (maximum memory length) is Qma
x, and the back pressure generation threshold is represented by Qbp.

First, a byte type discrimination signal PSTAT, an idle frame insertion threshold value Qidl, an idle frame insertion signal IDL, a memory overflow alarm OFAL
Initialization of M [X] (X is a logical channel number: any integer from 1 to N) is performed. An idle frame insertion threshold value Qidl is set (step A13). The number of write bytes W and the number of read bytes R of the logical channel are input for each clock (step A14).

W is added to Q and R is subtracted to calculate the number of data bytes Q stored in the packet memory of the logical channel (step A15: Q = Q + W−).
R). If Q> Qmax (Ye in step A16)
s) OFALM [X] = 1 is output assuming that a memory overflow has occurred (step A1)
7). If Q ≦ Qmax (N in step A16)
o), no memory overflow has occurred and OFA
LM [X] = 0 is output (step A18).

If Q> Qbp (Y in step A19)
es), the back pressure signal BP [X] = 1 is output (step A21). If Q ≦ Qbp, the back pressure control is not performed, and BP [X] = 0 is output (step A20). On the other hand, if Q <0 (Yes in step A32), it is determined that a memory underflow has occurred, and UFALM [X] = 1 is output (step A34). If Q ≧ 0 (No in step A32), no memory underflow has occurred and UFALM [X] = 0 is output (step A32).
33).

PSTAT = 0 or SOP = 0 (SO
If P = 1 is not received), and Q is less than the threshold value Qidl (Yes in step A29), an M byte width of the idle frame is added to the Q, and
As IDL = 1, a selection signal for inserting an idle frame is output (step A31). On the other hand, if No in step A29 (during reception of the user packet frame or Q ≧ Qidl), Q is left as it is, IDL = 0, and no idle frame is inserted (step A30). At that time, if SOP = 1 (Yes in A23), PSTAT = 1 is set (Step A27), and if EOP = 1 (Yes in Step A24), PSTAT = 0 is set (Step A2).
6) If SOP is not 1 and EOP is not 1 (No in step A24), the PSTAT is held at the PSTAT in the previous clock (step A25).

Since the processing part shown in step A35 and the processing part shown in step A28 can be processed in parallel, the number of logic stages does not increase so much, and the generation of back pressure signal, monitoring of memory underflow, memory Overflow monitoring may be performed.

[0084]

According to the present invention, the STM mapping apparatus comprises:
The processing of inserting an idle frame and reading data can be sped up while suppressing an increase in circuit scale. In order to increase the speed, it is possible to suppress an increase in the scale of a circuit for inserting an idle frame and reading data.

More specifically, when a variable-length packet having a different length for each user packet frame such as a GFP frame or an SDL frame is stored in an STM frame, the circuit has a simple configuration, and the circuit scale can be reduced. Speed improvement is possible. In the case where idle frames are packed without gaps between user packet frames, if the number of data storage bytes for each logical channel is less than the threshold value, the data By adopting a configuration to write an idle frame from the memory of the next byte number to which the packet is routed, complicated processing on the memory read side, which was conventionally required, is not required, and the circuit scale is reduced.
Further, the number of processing stages is reduced, and high-speed processing can be supported.
Therefore, the STM mapping device according to the present invention can
A higher-speed line can be accommodated by a line card or a switch card such as an STM / Packet hybrid switch equipped with a mapping circuit.

Further, high-speed processing is possible, and it is difficult to increase the number of parallel expansions of the main signal when a line having the same speed as that of the conventional one is handled in the communication apparatus. The increase can be suppressed more effectively.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of an STM mapping device according to the present invention.

FIG. 2 is a circuit block diagram illustrating routing.

FIG. 3 is a table showing a correspondence relationship between a physical channel and a logical channel;

FIG. 4 is a table showing a part of a correspondence relationship between an output position of a channel and an input port;

FIG. 5 is a table showing a series of other parts in FIG. 4;

FIG. 6 is a flowchart showing an operation flow of the STM mapping device according to the present invention.

FIG. 7 is a table showing the correspondence between routing information and ports.

FIGS. 8A, 8B, and 8C are logical tables showing a part of an array for storing byte data having a width of 8 bytes.

9 (d) and 9 (e) are logical tables showing a series of other parts in FIG.

FIG. 10 is a flowchart showing another operation flow of the STM mapping device according to the present invention.

FIG. 11 is a table showing a part of correspondence between logical channels and data;

FIG. 12 is a table showing a series of other parts in FIG. 11;

FIGS. 13A and 13B are formats respectively showing a user packet frame and a part of data thereof. FIG.

FIGS. 14A and 14B are logical tables showing a part of an array of byte data having a width of 8 bytes.

FIGS. 15A and 15B are diagrams corresponding to FIGS.
(B) is a logical table showing another part of the array.

FIG. 16 is a format showing a relationship between a logical channel and a physical channel of packet data.

FIG. 17 is a circuit block diagram showing a technique proposed as a premise of the present invention.

FIG. 18 is a table showing a part of an arrangement relationship between logical channels and data according to the technology proposed on the premise.

FIG. 19 is a table showing another part of the arrangement relationship in FIG. 18;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Packet data arrangement control circuit 2 ... Packet data input circuit 3 ... Packet data output circuit (19-11 to 19-1M) to (19-N1 to 19-N)
M) FIFO memories 21-1 to 21-N memory write control circuits 23-1 to 23-N queue length management circuits 24-1 to 24-N idle frame generation circuits 25-1 to 25-N selector circuit

Claims (16)

[Claims] 1. A packet memory for storing data bytes obtained by expanding a variable-length packet for each clock, and a memory control circuit for allocating the data bytes to the packet memory for each clock, the packet memory comprising: The control circuit comprises M independent FIFO memory units formed for each logical channel representing the type of the variable-length packet, one byte at a time, wherein the number of data storage bytes for each logical channel is less than a threshold value. A queue length management circuit that outputs a discrimination signal indicating each clock, a generation circuit that generates an idle frame to be written to a FIFO memory having a byte number next to a byte number of a data byte stored last in the FIFO memory, A selector for selectively outputting the idle frame to the packet memory based on a determination signal An STM mapping device comprising a data circuit. 2. The STM mapping apparatus according to claim 1, wherein said idle frame is written in said FIFO memory without a gap between successive variable length packets. 3. The queue length management circuit according to claim 1, wherein the number of write bytes W of the data bytes stored in the FIFO memory having a width of M bytes for each of the logical channels and the FIFO.
Based on the number of read bytes R of the data bytes read from the memory and the number of accumulated bytes Q, Q = Q + W−
3. The STM mapping apparatus according to claim 1, wherein the number of data storage bytes is calculated for each clock by using R. 4. The queue length management circuit according to claim 1, wherein the number of data storage bytes is less than the set threshold value and the input state of the logical channel is a section state between the variable length packets, the select signal IDL = 1. And outputs a select signal IDL = 0 if the input state of the logical channel is in the middle of a user packet frame. The control circuit further includes a selector circuit, and the selector circuit further includes a select signal IDL = 1. 4. The STM mapping apparatus according to claim 3, wherein the idle frame is output to the packet memory based on the following. 5. When the select signal IDL = 1 is output, M is added to the data storage byte number.
Or the STM mapping device of 4. 6. The selector circuit, based on the select signal IDL, a user packet frame signal having a width of M bytes and byte validity information indicating which byte of the M bytes is a valid user packet frame; 5. The STM mapping device according to claim 3, wherein the idle circuit signal and the byte validity information output by the generation circuit are selectively output. 7. The queue length management circuit compares the number of update storage bytes Q with a set threshold value Qbp, and determines that Q ≦ Q
BP, the back pressure signal BP [X] = 0 is output for each logical channel, and if Q> Qbp, the back pressure signal BP [X] = 1 is output for each logical channel. The STM mapping device according to claim 1, wherein 8. The queue length management circuit compares the number of updated accumulated bytes Q with a maximum memory length value Qmax, and if Q ≦ Qmax, a memory overflow alarm signal OFALM [X] = for each logical channel. 0, and if Q> Qmax, outputs a memory overflow alarm signal OFALM [X] = 1 for each logical channel, and further compares the updated accumulated data byte number Q with 0 to determine whether Q ≧ 0. The memory underflow alarm signal UFALM [X] = 0 is output for each logical channel if Q <0, and the memory underflow alarm signal UFALM [X] = 1 for each logical channel is output if Q <0. STM mapping device. 9. The queue length management circuit judges whether the memory underflow alarm signal UFALM [X] is set to 0 or 1 based on the number Q of updated accumulated bytes, and outputs a select signal IDL. 9. The STM mapping apparatus according to claim 7, wherein whether to set to 0 or 1 is determined in parallel based on the EOP signal and the SOP signal. 10. M FIFOs formed for each logical channel representing the type of a variable-length packet and each byte is independent.
A packet memory including a plurality of units in units of memory; and a control circuit for executing control for inputting a plurality of data bytes to the packet memory per clock, wherein the control circuit stores data for each logical channel. An STM mapping apparatus for executing control for inputting an idle frame in an M-byte width unit following the data byte without a gap based on the number of bytes. 11. A first step of writing data bytes of a variable-length packet in a memory area formed with a width of M bytes without gaps, and a second step of counting the number Q of data bytes written in the memory area. And a third step of writing an idle frame in units of M bytes between the variable length packets before and after if the number Q is less than a set threshold value in the memory area without any gap.
Mapping method. 12. The STM according to claim 11, wherein said number Q is a number calculated by Q = Q + WR based on the number R of data bytes written to said memory area and the number of data bytes read from said memory. Mapping method. 13. The STM mapping method according to claim 12, wherein said data byte having a width of M bytes is read and written every clock, and said number Q is calculated every clock. 14. The setting threshold value is represented by Qbp, and Q ≦ Qbp.
If so, the back pressure signal BP for each logical channel
14. The method according to claim 11, further comprising a fifth step of outputting [X] = 0 and outputting a back pressure signal BP [X] = 1 for each logical channel if Q> Qbp. STM mapping method. 15. The maximum value of the memory holding the data bytes in the first step is represented by Qmax, wherein Q ≦ Qm
ax, the memory overflow alarm signal OFALM [X] = 0 is output for each logical channel, and Q> Qma
If x, a memory overflow alarm signal OFALM [X] = 1 for each logical channel is output, and the size of the updated accumulated data byte number Q and 0 is compared, and Q ≧
If 0, a memory underflow alarm signal UFALM [X] = 0 for each logical channel is output; if Q <0, a memory underflow alarm signal UFALM [X] = 1 for each logical channel is output. 14. The STM mapping method according to claim 11, further comprising: 16. The STM mapping according to claim 14, further comprising a seventh step of determining whether said memory underflow alarm signal UFALM [X] is set to 0 or 1 based on said updated accumulated byte number Q. Method.