JP2002359393A - Semiconductor relay - Google Patents

Semiconductor relay

Info

Publication number
JP2002359393A
JP2002359393A JP2001164196A JP2001164196A JP2002359393A JP 2002359393 A JP2002359393 A JP 2002359393A JP 2001164196 A JP2001164196 A JP 2001164196A JP 2001164196 A JP2001164196 A JP 2001164196A JP 2002359393 A JP2002359393 A JP 2002359393A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor relay
mosfets
led
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001164196A
Other languages
Japanese (ja)
Inventor
Kazunari Kuzuhara
一功 葛原
Yasushi Tanaka
恭史 田中
Sadayuki Sumi
貞幸 角
Shigenari Takami
茂成 高見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2001164196A priority Critical patent/JP2002359393A/en
Publication of JP2002359393A publication Critical patent/JP2002359393A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Electronic Switches (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor relay which can be improved in high-frequency characteristic and reduced in size and, at the same time, rationalized in manufacturing process. SOLUTION: In the semiconductor relay, two MOSFETs 6 are mounted on a BGA substrate 5, electrically connected to a substrate 1 mounted with an LED 2 and a photovoltaic element 3 through metallic projections 7, and connected to a mother substrate by BGA mounting. In addition, the need of metallic wires for connecting the MOSFETs 6 to each other is eliminated and the wiring for the MOSFETs 6 can be constituted thickly and shortly by electrically connecting the MOSFETs 6 to the outside through filled-up through holes 8 formed through the BGA substrate 5 immediately below the mounting sections of the MOSFETs 6 and electrodes 9 and solder balls 10 provided on the rear surface of the BGA substrate 1. Consequently, the influence of L-components in wiring routes and the deterioration of signals can be reduced. In addition, since no lead frame is used, impedance unmatching can be reduced significantly.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、光結合によるアイ
ソレーションを用いた半導体リレーに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor relay using isolation by optical coupling.

【０００２】[0002]

【従来の技術】従来より、電気的アイソレーションに優
れた光結合型の半導体リレーが、種々提案され、また種
々の用途に採用されている。2. Description of the Related Art Hitherto, various optically coupled semiconductor relays having excellent electrical isolation have been proposed and employed for various applications.

【０００３】図４は、従来例に係る半導体リレーの回路
図である。図５は、従来例に係る半導体リレーの全体構
成を示す概略断面図である。受光素子である光起電力素
子３とスイッチ素子であるＭＯＳＦＥＴ６とが銀ペース
ト等でリードフレーム２０ａ上にダイボンディングさ
れ、更にワイヤボンディングされている。ここで、光起
電力素子３とは、図９における、フォトダイオードアレ
イ１７、駆動用のＭＯＳＦＥＴ１８及び抵抗Ｒが１チッ
プ化された素子のことである。FIG. 4 is a circuit diagram of a conventional semiconductor relay. FIG. 5 is a schematic sectional view showing the entire configuration of a semiconductor relay according to a conventional example. The photovoltaic element 3 as a light receiving element and the MOSFET 6 as a switch element are die-bonded on a lead frame 20a with silver paste or the like, and further wire-bonded. Here, the photovoltaic element 3 is an element in FIG. 9 in which the photodiode array 17, the driving MOSFET 18 and the resistor R are integrated into one chip.

【０００４】一方、発光素子である発光ダイオード（Ｌ
ＥＤ:Light Emitting Diode）２が銀ペースト等でリー
ドフレーム２０ｂ上に、ダイボンディングされ、更にワ
イヤボンディングされており、リードフレーム２０ａ，
２０ｂをＬＥＤ２と光起電力素子３とが対向するように
配置されている。On the other hand, a light emitting diode (L
An ED (Light Emitting Diode) 2 is die-bonded on the lead frame 20b with a silver paste or the like, and is further wire-bonded.
20b is arranged so that the LED 2 and the photovoltaic element 3 face each other.

【０００５】そして、ＬＥＤ２と光起電力素子３との間
には、光を透過するカップリング樹脂１１が充填され、
全体を封止樹脂１２から成るパッケージによりモールド
されている。この時、パッケージからは、リードフレー
ム２０ａ，２０ｂの一端が突出する構成となっている。[0005] The space between the LED 2 and the photovoltaic element 3 is filled with a coupling resin 11 that transmits light.
The whole is molded by a package made of a sealing resin 12. At this time, one end of the lead frames 20a and 20b protrudes from the package.

【０００６】また、ＭＯＳＦＥＴを１チップのみ実装す
ると、ＭＯＳＦＥＴのダイオード特性により直流用のみ
にしか使用できないが、図５に示すように２個のＭＯＳ
ＦＥＴ６a、６bを実装すると、直流・交流の両方に使用
可能となる。If only one MOSFET is mounted, it can be used only for direct current due to the diode characteristics of the MOSFET. However, as shown in FIG.
When the FETs 6a and 6b are mounted, they can be used for both DC and AC.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、図５に
示すような構造では、ＭＯＳＦＥＴの裏面電極はリード
フレームに搭載され、そのリードフレームがパッケージ
外部に出て、折り曲げられて基板に搭載されることにな
る。また、ＭＯＳＦＥＴ間はリードフレームにそれぞれ
ワイヤボンディングする。その為、一方のＭＯＳＦＥＴ
からもう一方のＭＯＳＦＥＴへ高周波の電流が流れる時
に、リードフレームの長さや、折曲げ部の影響でインピ
ーダンス不整合が起こり、立ち上がり特性が劣化する。
また、金属ワイヤのＬ成分によりインピーダンスが高く
なり電流が流れにくくなるという問題を生じていた。However, in the structure shown in FIG. 5, the back electrode of the MOSFET is mounted on a lead frame, and the lead frame goes out of the package, is bent, and is mounted on the substrate. become. Wire bonding is performed between the MOSFETs on the lead frame. Therefore, one MOSFET
When a high-frequency current flows from the other MOSFET to the other MOSFET, impedance mismatch occurs due to the influence of the length of the lead frame and the bent portion, and the rising characteristics deteriorate.
In addition, there has been a problem that the impedance is increased due to the L component of the metal wire, making it difficult for a current to flow.

【０００８】本発明は、かかる事由に鑑み、なされたも
ので、本発明の目的は、上記したような高周波特性の改
善と同時に、一層の小型化及び製造工程の合理化が可能
な半導体リレーを提供することにある。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor relay capable of improving the high-frequency characteristics as described above, and further reducing the size and streamlining the manufacturing process. Is to do.

【０００９】[0009]

【課題を解決するための手段】上記課題を解決するため
に、請求項１記載の半導体リレーの発明にあっては、少
なくとも、ＬＥＤと、光起電力素子とを搭載した第１の
基板と、少なくとも、複数のＭＯＳＦＥＴを搭載した第
２の基板を有する半導体リレーであって、前記ＭＯＳＦ
ＥＴ上の電極に金属突起を形成し、これらの金属突起を
介して前記複数のＭＯＳＦＥＴと前記第１の基板を電気
的に接続するとともに、前記第１の基板と前記第２の基
板を金属ワイヤにて別途電気的に接続して成ることを特
徴とするものである。According to a first aspect of the present invention, there is provided a semiconductor relay having at least a first substrate on which an LED and a photovoltaic element are mounted. At least a semiconductor relay having a second substrate on which a plurality of MOSFETs are mounted, wherein the MOSF
Metal projections are formed on electrodes on the ET, and the plurality of MOSFETs and the first substrate are electrically connected via the metal projections, and the first substrate and the second substrate are connected by metal wires. And are electrically connected separately.

【００１０】請求項２記載の発明にあっては、請求項１
記載の半導体リレーにおいて、前記ＬＥＤを前記第１の
基板に形成された凹部に埋没するように実装すると共
に、前記光起電力素子を、該ＬＥＤに正対せしめ、且
つ、前記第１の基板に電気的に接続したことを特徴とす
るものである。According to the second aspect of the present invention, the first aspect is provided.
In the semiconductor relay according to the above, the LED is mounted so as to be buried in a concave portion formed in the first substrate, and the photovoltaic element is directly opposed to the LED, and the LED is mounted on the first substrate. It is characterized by being electrically connected.

【００１１】請求項３記載の発明にあっては、請求項１
または請求項２記載の半導体リレーにおいて、前記第２
の基板が、ＢＧＡ基板であって、該ＢＧＡ基板の前記Ｍ
ＯＳＦＥＴ搭載部の裏面にハンダボールを形成した電極
を設け、該電極と導通した埋込スルーホールを介して前
記ＭＯＳＦＥＴと前記ハンダボールとを電気的に接続し
たことを特徴とするものである。According to the third aspect of the present invention, there is provided the first aspect.
Or the semiconductor relay according to claim 2, wherein
Is a BGA substrate, and the M
An electrode on which a solder ball is formed is provided on the back surface of the OSFET mounting portion, and the MOSFET and the solder ball are electrically connected through a buried through hole that is electrically connected to the electrode.

【００１２】[0012]

【発明の実施の形態】以下、本発明の実施形態を図面に
基づき説明する。なお、本発明の半導体リレーは、下記
の実施形態にのみ限定されるものではなく、本発明の要
旨を逸脱しない範囲内において種々変更を加え得ること
は勿論である。Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the semiconductor relay of the present invention is not limited to only the following embodiment, and it is needless to say that various changes can be made without departing from the gist of the present invention.

【００１３】[第１の実施形態]図１は本発明の半導体リ
レーの実施形態の要部の基本構成を示すもので、(a)は
上面からの模式図、(b)は(a)におけるＡ1-Ｂ1線に沿っ
て切断した場合の概略を示す断面模式図である。基板１
上に、少なくとも、ＬＥＤ２と、光起電力素子（受光素
子）３とを搭載し、これらの各素子の表面電極（図示せ
ず）と基板１とを金属ワイヤ４にて接続する一方、ＢＧ
Ａ(Ball Grid Array)基板５上に２個のＭＯＳＦＥＴ６
を搭載し、該ＭＯＳＦＥＴ６上の電極（図示せず）に金
属突起７を形成し、これらの金属突起７を介して該ＭＯ
ＳＦＥＴ６と前記基板１を電気的に接続する。更に、基
板１とＢＧＡ基板５とが金属ワイヤ４aにて別途電気的
に接続されている。一方、ＭＯＳＦＥＴ６の搭載部のＢ
ＧＡ基板５の真下に埋込スルーホール８が形成されてお
り、さらにＢＧＡ基板５の裏面部に電極９を介しハンダ
ボール１０が形成されている。また、ＬＥＤ２と光起電
力素子３とはカップリング樹脂１１により平面カップリ
ングされ、ＢＧＡ基板５の前記第１の基板を搭載した面
上の上記総ての構成要素(即ち、ＢＧＡ基板５の裏面部
の電極９及びハンダボール１０を除いた上記総ての構成
要素)は、封止樹脂１２により封止されている。即ち、
本実施形態においては、２個のＭＯＳＦＥＴ相互間の金
属ワイヤ接続が無く、ＭＯＳＦＥＴ上６の電極上の金属
突起７を介してＭＯＳＦＥＴ６と前記基板１が直接、電
気的に接続される構成を有することにより、その配線を
太く短く構成することが可能となるため、配線経路中の
Ｌ成分の影響を小さくし、信号の劣化を低減することが
できる。また、リードフレームが不要なＢＧＡ実装によ
り、母基板(図示せず)に接続されるため、ＭＯＳＦＥＴ
６から外部への電気的接続を、全体として、短く構成す
ることが可能で、配線の曲折も低減され、リードフレー
ムを使用しないため、インピーダンス不整合を大幅に低
減することが可能となる。[First Embodiment] FIG. 1 shows a basic configuration of a main part of a semiconductor relay according to an embodiment of the present invention. FIG. 1 (a) is a schematic view from the top, and FIG. FIG. 3 is a schematic cross-sectional view schematically showing a case where the semiconductor device is cut along a line A 1 -B 1 . Substrate 1
At least an LED 2 and a photovoltaic element (light receiving element) 3 are mounted thereon, and a surface electrode (not shown) of each of these elements is connected to the substrate 1 by a metal wire 4 while a BG is connected.
A (Ball Grid Array) substrate 5 with two MOSFETs 6
Is mounted, and a metal projection 7 is formed on an electrode (not shown) on the MOSFET 6.
The SFET 6 and the substrate 1 are electrically connected. Further, the substrate 1 and the BGA substrate 5 are separately electrically connected by metal wires 4a. On the other hand, B
A buried through hole 8 is formed directly below the GA substrate 5, and a solder ball 10 is formed on the back surface of the BGA substrate 5 via an electrode 9. The LED 2 and the photovoltaic element 3 are planarly coupled by a coupling resin 11, and all the components on the surface of the BGA substrate 5 on which the first substrate is mounted (that is, the back surface of the BGA substrate 5) All of the above components except for the electrodes 9 and the solder balls 10) are sealed with a sealing resin 12. That is,
In this embodiment, there is no metal wire connection between the two MOSFETs, and the MOSFET 6 and the substrate 1 are directly electrically connected via the metal protrusions 7 on the electrodes of the MOSFET 6. Accordingly, the wiring can be configured to be thick and short, so that the influence of the L component in the wiring path can be reduced, and the deterioration of the signal can be reduced. Also, since the lead frame is connected to the motherboard (not shown) by unnecessary BGA mounting, MOSFET
The electrical connection from 6 to the outside can be shortened as a whole, the bending of wiring can be reduced, and the use of a lead frame can greatly reduce impedance mismatching.

【００１４】[第２の実施形態]図２は本発明の半導体リ
レーの上記と異なる実施形態の要部の基本構成を示すも
ので、(a)は上面からの模式図、(b)は(a)におけるＡ2-
Ｂ2線に沿って切断した場合の概略を示す断面模式図で
ある。本実施形態においては、ＭＩＤ(Molded Intercon
nection Device) の製造技術を応用して、第１の実施形
態において、基板１aにＬＥＤ２を埋没するように実装
する凹部１３aを形成し、ＬＥＤ２を光起電力素子３と
正対するように前記凹部１３aの底面に搭載し、光起電
力素子３を基板１に金属突起１４を介して電気的に接続
する構成を有するものである。即ち、本実施形態におい
ては、ＬＥＤ２と光起電力素子３が正対する構成を有す
るので、両者間の光伝達効率が良好となるため、消費電
力の低減や、ＬＥＤ２と光起電力素子３のサイズの小型
化が可能となり、延いては、半導体リレーの小型化に寄
与し得るというものである。[Second Embodiment] FIGS. 2A and 2B show a basic configuration of a main part of a semiconductor relay according to a second embodiment of the present invention which is different from the above. FIG. 2A is a schematic view from the top, and FIG. A 2- in a)
FIG. 4 is a schematic cross-sectional view schematically showing a case where the semiconductor device is cut along a line B 2 . In the present embodiment, the MID (Molded Intercon
In the first embodiment, a recess 13a for mounting the LED 2 so as to be buried is formed in the substrate 1a by applying the manufacturing technology of the “nection device”, and the recess 13a is positioned so that the LED 2 faces the photovoltaic element 3 directly. And a structure in which the photovoltaic element 3 is electrically connected to the substrate 1 via the metal projection 14. That is, in the present embodiment, since the LED 2 and the photovoltaic element 3 have a configuration facing each other, the light transmission efficiency between them becomes good, so that the power consumption can be reduced and the size of the LED 2 and the photovoltaic element 3 can be reduced. It is possible to reduce the size of the semiconductor relay, which can contribute to the miniaturization of the semiconductor relay.

【００１５】[第３の実施形態]図３は本発明の半導体リ
レーの更に上記と異なる実施形態の要部の基本構成を示
すもので、(a)は上面からの模式図、(b)は(a)における
Ａ3-Ｂ3線に沿って切断した場合の概略を示す断面模式
図である。本実施形態においては、第１の実施形態にお
いて、基板１を基板を積層することにより作成し、該積
層基板１bの上部の一部を刳り貫き、これに、ＬＥＤ２
を埋没するように実装する凹部１３bを形成し、ＬＥＤ
２を光起電力素子３と正対するように前記凹部１３bの
底面に搭載すると共に、光起電力素子３を基板１に金属
突起１４を介して電気的に接続する構成を有するもので
ある。即ち、本実施形態においても、第３の実施形態と
同様に、ＬＥＤ２と光起電力素子３が正対する構成を有
するので、両者間の光伝達効率が良好となるため、消費
電力の低減や、ＬＥＤ２と光起電力素子３のサイズの小
型化が可能となり、半導体リレーの小型化に寄与し得る
ものであるが、本実施形態の半導体リレーにおいては、
これに加えて、例えば、上記第３の実施形態と比較し
て、基板１を基板を積層することにより作成する積層基
板で構成するため、基板１の製作、加工が容易であり、
半導体リレーの製造工程の短縮と製造コスト低減に寄与
し得るものである。[Third Embodiment] FIGS. 3A and 3B show a basic configuration of a main part of a semiconductor relay according to a third embodiment of the present invention, which is different from the above. FIG. FIG. 3A is a schematic cross-sectional view schematically showing a case of cutting along the line A 3 -B 3 in FIG. In the present embodiment, in the first embodiment, the substrate 1 is formed by laminating the substrates, and a part of the upper part of the laminated substrate 1b is hollowed out.
Is formed so as to bury the LED, and the LED is formed.
2 is mounted on the bottom surface of the concave portion 13 b so as to face the photovoltaic element 3, and the photovoltaic element 3 is electrically connected to the substrate 1 via the metal protrusion 14. That is, also in the present embodiment, similarly to the third embodiment, since the LED 2 and the photovoltaic element 3 have a configuration facing each other, the light transmission efficiency between them is improved, so that the power consumption can be reduced. The size of the LED 2 and the photovoltaic element 3 can be reduced, which can contribute to downsizing of the semiconductor relay. In the semiconductor relay of the present embodiment,
In addition to this, for example, as compared with the third embodiment, the substrate 1 is constituted by a laminated substrate formed by laminating the substrates, so that the production and processing of the substrate 1 are easy,
This can contribute to shortening of the manufacturing process of the semiconductor relay and reduction of the manufacturing cost.

【００１６】[0016]

【発明の効果】以上のように、請求項１記載の半導体リ
レーの発明にあっては、少なくとも、ＬＥＤと、光起電
力素子とを搭載した第１の基板と、少なくとも、複数の
ＭＯＳＦＥＴを搭載した第２の基板を有する半導体リレ
ーであって、前記ＭＯＳＦＥＴ上の電極に金属突起を形
成し、これらの金属突起を介して前記複数のＭＯＳＦＥ
Ｔと前記第１の基板を電気的に接続するとともに、前記
第１の基板と前記第２の基板を金属ワイヤにて別途電気
的に接続して成ることを特徴とするため、２個のＭＯＳ
ＦＥＴ相互間の金属ワイヤ接続を無く、その配線を太く
短く構成することが可能となるため、配線経路中のＬ成
分の影響が小さくし、信号の劣化を低減することができ
るという優れた効果を奏し得る。As described above, according to the first aspect of the present invention, at least a first substrate on which an LED and a photovoltaic element are mounted, and at least a plurality of MOSFETs are mounted. A metal relay formed on an electrode on the MOSFET, and the plurality of MOSFEs formed through the metal projection.
T is electrically connected to the first substrate, and the first substrate and the second substrate are electrically connected separately by metal wires.
Since there is no metal wire connection between the FETs and the wiring can be made thick and short, the excellent effect of reducing the influence of the L component in the wiring path and reducing signal degradation can be obtained. I can play.

【００１７】請求項２記載の発明にあっては、請求項１
記載の半導体リレーにおいて、前記ＬＥＤを前記第１の
基板に形成された凹部に埋没するように実装すると共
に、前記光起電力素子を、該ＬＥＤに正対せしめ、且
つ、前記第１の基板に電気的に接続したことを特徴とす
るので、ＬＥＤと光起電力素子との光伝達効率が良好と
なり、消費電力の低減や、ＬＥＤと光起電力素子の小型
化が可能となり、延いては、半導体リレーの小型化に寄
与し得るという優れた効果を奏し得る。According to the second aspect of the present invention, the first aspect is provided.
In the semiconductor relay according to the above, the LED is mounted so as to be buried in a concave portion formed in the first substrate, and the photovoltaic element is directly opposed to the LED, and the LED is mounted on the first substrate. Since it is characterized by being electrically connected, the light transmission efficiency between the LED and the photovoltaic element is improved, the power consumption can be reduced, and the LED and the photovoltaic element can be downsized. An excellent effect of contributing to miniaturization of the semiconductor relay can be obtained.

【００１８】請求項３記載の発明にあっては、請求項１
または請求項２記載の半導体リレーにおいて、前記第２
の基板が、ＢＧＡ基板であって、該ＢＧＡ基板の前記Ｍ
ＯＳＦＥＴ搭載部の裏面にハンダボールを形成した電極
を設け、該電極と導通した埋込スルーホールを介して前
記ＭＯＳＦＥＴと前記ハンダボールとを電気的に接続し
たことを特徴とするので、リードフレームが不要なＢＧ
Ａ実装により、母基板(図示せず)に接続されるため、Ｍ
ＯＳＦＥＴから外部への電気的接続を、全体として、短
く構成することが可能で、配線の曲折も低減され、イン
ピーダンス不整合を大幅に低減できるという優れた効果
を奏し得る。According to the third aspect of the present invention, there is provided the first aspect.
Or the semiconductor relay according to claim 2, wherein
Is a BGA substrate, and the M
An electrode in which a solder ball is formed on the back surface of the OSFET mounting portion is provided, and the MOSFET and the solder ball are electrically connected through a buried through hole that is electrically connected to the electrode. Unnecessary BG
A is connected to the mother board (not shown) by A mounting,
The electrical connection from the OSFET to the outside can be shortened as a whole, and the bending of the wiring can be reduced, and an excellent effect that the impedance mismatch can be greatly reduced can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体リレーの実施形態の要部の基本
構成を示すもので、(a)は上面からの模式図、(b)は(a)
におけるＡ1-Ｂ1線に沿って切断した場合の概略を示す
断面模式図である。FIG. 1 shows a basic configuration of a main part of an embodiment of a semiconductor relay of the present invention, wherein (a) is a schematic view from the top, and (b) is (a).
FIG. 2 is a schematic cross-sectional view schematically showing a case of cutting along the line A 1 -B 1 in FIG.

【図２】本発明の半導体リレーの上記と異なる実施形態
の要部の基本構成を示すもので、(a)は上面からの模式
図、(b)は(a)におけるＡ2-Ｂ2線に沿って切断した場合
の概略を示す断面模式図である。FIGS. 2A and 2B show a basic configuration of a main part of an embodiment different from the above of the semiconductor relay of the present invention, wherein FIG. 2A is a schematic view from the top, and FIG. 2B is a line A 2 -B 2 in FIG. FIG. 3 is a schematic cross-sectional view schematically illustrating a case where the semiconductor device is cut along the line A.

【図３】本発明の半導体リレーの更に上記と異なる実施
形態の要部の基本構成を示すもので、(a)は上面からの
模式図、(b)は(a)におけるＡ3-Ｂ3線に沿って切断した
場合の概略を示す断面模式図である。3A and 3B show a basic configuration of a main part of a semiconductor relay according to another embodiment of the present invention, in which FIG. 3A is a schematic view from the top, and FIG. 3B is a schematic view of A 3 -B 3 in FIG. FIG. 3 is a schematic cross-sectional view schematically illustrating a case where the semiconductor device is cut along a line.

【図４】従来例に係る半導体リレーの回路図である。FIG. 4 is a circuit diagram of a semiconductor relay according to a conventional example.

【図５】従来例に係る半導体リレーの全体構成を示す概
略断面図である。FIG. 5 is a schematic sectional view showing the entire configuration of a semiconductor relay according to a conventional example.

【符号の説明】[Explanation of symbols]

１ 基板 ２ ＬＥＤ ３ 光起電力素子 ４ 金属ワイヤ ５ ＢＧＡ基板 ６ ＭＯＳＦＥＴ ７ 金属突起 ８ 埋込スルーホール ９ 電極 １０ ハンダボール １１ カップリング樹脂 １２ 封止樹脂 １３ 凹部 １４ 金属突起 １５ 回路パターン １６ リレー入力端子 １７ フォトダイオードアレイ １８ 駆動用ＭＯＳＦＥＴ １９ リレー出力端子 ２０ リードフレーム REFERENCE SIGNS LIST 1 substrate 2 LED 3 photovoltaic element 4 metal wire 5 BGA substrate 6 MOSFET 7 metal protrusion 8 buried through hole 9 electrode 10 solder ball 11 coupling resin 12 sealing resin 13 recess 14 metal protrusion 15 circuit pattern 16 relay input terminal 17 Photodiode array 18 Driving MOSFET 19 Relay output terminal 20 Lead frame

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０３Ｋ 17/78 Ｈ０１Ｌ 21/88 Ｔ (72)発明者 角 貞幸 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 高見 茂成 大阪府門真市大字門真1048番地松下電工株 式会社内 Ｆターム(参考） 5F033 HH07 HH14 MM30 VV07 XX27 XX33 XX34 5F089 AA06 AB01 AB03 AC02 AC11 CA20 EA04 FA10 5J050 AA02 AA37 AA47 AA49 BB21 DD01 DD08 FF04 FF10 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification FI FI Theme Court ゛ (Reference) H03K 17/78 H01L 21/88 T (72) Inventor Sadayuki Kado 1048 Kazuma Kajima, Kadoma City, Osaka Matsushita Electric Works, Ltd. (72) Inventor Shigenari Takami 1048, Kazuma, Kadoma, Osaka Pref. Matsushita Electric Works Co., Ltd.F-term (reference) AA47 AA49 BB21 DD01 DD08 FF04 FF10

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 少なくとも、ＬＥＤと、光起電力素子と
を搭載した第１の基板と、少なくとも、複数のＭＯＳＦ
ＥＴを搭載した第２の基板を有する半導体リレーであっ
て、前記ＭＯＳＦＥＴ上の電極に金属突起を形成し、こ
れらの金属突起を介して前記複数のＭＯＳＦＥＴと前記
第１の基板を電気的に接続するとともに、前記第１の基
板と前記第２の基板を金属ワイヤにて別途電気的に接続
して成ることを特徴とする半導体リレー。1. A first substrate on which at least an LED and a photovoltaic element are mounted, and at least a plurality of MOSFs
A semiconductor relay having a second substrate on which an ET is mounted, wherein a metal projection is formed on an electrode on the MOSFET, and the plurality of MOSFETs and the first substrate are electrically connected via the metal projection. A semiconductor relay, wherein the first substrate and the second substrate are separately electrically connected by metal wires. 【請求項２】 前記ＬＥＤを前記第１の基板に形成され
た凹部に埋没するように実装すると共に、前記光起電力
素子を、該ＬＥＤに正対せしめ、且つ、前記第１の基板
に電気的に接続したことを特徴とする請求項１記載の半
導体リレー。2. The LED is mounted so as to be buried in a recess formed in the first substrate, and the photovoltaic element is directly opposed to the LED, and the LED is electrically connected to the first substrate. 2. The semiconductor relay according to claim 1, wherein the semiconductor relay is electrically connected. 【請求項３】 前記第２の基板が、ＢＧＡ基板であっ
て、該ＢＧＡ基板の前記ＭＯＳＦＥＴ搭載部の裏面にハ
ンダボールを形成した電極を設け、該電極と導通した埋
込スルーホールを介して前記ＭＯＳＦＥＴと前記ハンダ
ボールとを電気的に接続したことを特徴とする請求項１
または請求項２記載の半導体リレー。3. The second substrate is a BGA substrate, and an electrode on which a solder ball is formed is provided on the back surface of the MOSFET mounting portion of the BGA substrate. 2. The semiconductor device according to claim 1, wherein the MOSFET and the solder ball are electrically connected.
Or a semiconductor relay according to claim 2.
JP2001164196A 2001-05-31 2001-05-31 Semiconductor relay Pending JP2002359393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001164196A JP2002359393A (en) 2001-05-31 2001-05-31 Semiconductor relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001164196A JP2002359393A (en) 2001-05-31 2001-05-31 Semiconductor relay

Publications (1)

Publication Number Publication Date
JP2002359393A true JP2002359393A (en) 2002-12-13

Family

ID=19007047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001164196A Pending JP2002359393A (en) 2001-05-31 2001-05-31 Semiconductor relay

Country Status (1)

Country Link
JP (1) JP2002359393A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129888A (en) * 2003-10-03 2005-05-19 Matsushita Electric Works Ltd Sensor device and sensor system, and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129888A (en) * 2003-10-03 2005-05-19 Matsushita Electric Works Ltd Sensor device and sensor system, and manufacturing method therefor
JP4539155B2 (en) * 2003-10-03 2010-09-08 パナソニック電工株式会社 Manufacturing method of sensor system

Similar Documents

Publication Publication Date Title
JP7240148B2 (en) optical coupler
JP2005051130A (en) Leadless package semiconductor device and method for manufacturing the same
JP2006351859A (en) Manufacturing method of optical coupling
JP2000232235A (en) Semiconductor device
US6588946B1 (en) Optical coupling device
JP4908669B2 (en) Chip light emitting device
JP2002359392A (en) Semiconductor relay
JP2002359393A (en) Semiconductor relay
JP3242476B2 (en) Optical semiconductor device
US20230420909A1 (en) Semiconductor light-emitting device
JP4237542B2 (en) Semiconductor device
JPH11204688A (en) Semiconductor package and manufacture thereof
US20080296520A1 (en) Optical coupling device
JP2004103654A (en) Optically coupled semiconductor device and its manufacturing method
JP2002026246A (en) Semiconductor device
JP6329596B2 (en) Semiconductor device
JP2001102518A (en) Power semiconductor device
JPH1070306A (en) Optically coupled relay device
JP4353935B2 (en) Leadless package semiconductor device
JPH09283544A (en) Semiconductor device
JP2004228402A (en) Semiconductor device
JPH0645636A (en) Photodetection and light-emitting element and photodetection and light-emitting device utilizing it
JPH10284755A (en) Photocoupler
JP2000269376A (en) Semiconductor device
JP4608810B2 (en) Surface mount semiconductor device