JP2002359262A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor

Info

Publication number
JP2002359262A
JP2002359262A JP2001164499A JP2001164499A JP2002359262A JP 2002359262 A JP2002359262 A JP 2002359262A JP 2001164499 A JP2001164499 A JP 2001164499A JP 2001164499 A JP2001164499 A JP 2001164499A JP 2002359262 A JP2002359262 A JP 2002359262A
Authority
JP
Japan
Prior art keywords
film substrate
lead wiring
semiconductor element
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001164499A
Other languages
Japanese (ja)
Other versions
JP4562950B2 (en
Inventor
Junichi Ueno
順一 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001164499A priority Critical patent/JP4562950B2/en
Publication of JP2002359262A publication Critical patent/JP2002359262A/en
Application granted granted Critical
Publication of JP4562950B2 publication Critical patent/JP4562950B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To solve the problem of the nonconformity of cracks occuring near a bump electrode, which electrically connects lead wiring and the electrode of a semiconductor element due to the difference of the thermal expansion coefficients of respective materials, when sealing resin whose one end is heated drops to room temperature, in a process where a part between a film base material in which lead wiring is formed on a surface and the semiconductor element is sealed by encapsulating resin. SOLUTION: Lead wiring 9 and the film base material 8 are separated by heating them. When the temperature of sealing resin 12 heated in the sealing process drops to the room temperature, stress caused near a bump electrode 16 is absorbed, in a part which is detached from the film base material 8 of lead wiring 9. Thus, the nonconformity of cracks in a protective film 15 is prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はフィルム状の基板上
に半導体素子を搭載した半導体装置に関するものであ
り、特に、基板に形成された配線が可動する半導体装置
およびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element mounted on a film-like substrate, and more particularly to a semiconductor device in which wiring formed on a substrate is movable and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来より、LSIなどの半導体製品は低
価格化、軽量化、薄型化、小型化の実現のために高密度
実装が要求され続けている。
2. Description of the Related Art Conventionally, semiconductor products such as LSIs have been required to be mounted at a high density in order to realize a reduction in price, weight, thickness and thickness.

【0003】一般に、半導体素子の高密度実装を実現す
る半導体装置として、TCP(Tape Carrie
r Package)と称する半導体装置があるが、そ
の中でもデバイスホールや折り曲げスリットが無く、半
導体チップの電極と接続されるリード配線がテープ基材
に密着しているものがCOF(Chip On Fil
m)である。COFはデバイスホールが無く、リード配
線がフィルム基材に密着しているためにリード配線を薄
くすることが出来る。これにより従来のデバイスホール
があるTCPと比較するとリード配線のエッチングが容
易となり、より微細な導体パターンを形成することがで
きる。現在、45[μm]ピッチのCOFテープが業界で
出現されつつあり、さらなるファイン化が要望されてい
る。
[0003] Generally, TCP (Tape Carrier) is used as a semiconductor device for realizing high-density mounting of semiconductor elements.
There is a semiconductor device called “r Package”. Among them, a device without a device hole or a bending slit and a lead wire connected to an electrode of a semiconductor chip is in close contact with a tape base material is a COF (Chip On Fil).
m). The COF has no device hole and the lead wiring is in close contact with the film substrate, so that the lead wiring can be made thinner. As a result, as compared with the conventional TCP having a device hole, the etching of the lead wiring becomes easier, and a finer conductor pattern can be formed. At present, COF tapes having a pitch of 45 [μm] are emerging in the industry, and further refinement is required.

【0004】以下、図面を参照しながら従来の半導体装
置およびその製造方法について説明する。
Hereinafter, a conventional semiconductor device and a method of manufacturing the same will be described with reference to the drawings.

【0005】まず、従来の半導体装置について説明す
る。
[0005] First, a conventional semiconductor device will be described.

【0006】図4(a)は、従来の半導体装置を示す平
面図であり、図4(b)は図4(a)のA−A1箇所に
おける断面図である。
FIG. 4A is a plan view showing a conventional semiconductor device, and FIG. 4B is a cross-sectional view taken along a line AA1 in FIG. 4A.

【0007】図4(a)および図4(b)に示すよう
に、フィルム基板1は絶縁、可撓の性質を有し、ポリイ
ミドなどの樹脂で形成されたフィルム基材2と、銅など
の金属箔で形成されたリード配線3とで構成されてい
る。リード配線3において半導体素子4の突起電極(図
示せず)と接続する部分でソルダーレジスト5に覆われ
ていない領域をインナーリード3a、インナーリード3
aより外へフィルム基材2上に延長されたリード配線3
のうち、外部回路と接続される領域をアウターリード3
bと呼ぶ。リード配線3には通常メッキが施されてい
る。半導体素子4の電極には、半導体素子4に形成され
ている電極とインナーリード3aとを接続するために必
要な突起電極6が形成されている。突起電極6の高さは
さまざまであり、突起電極6が形成されていない構成も
ある。インナーリード3a周辺の領域は半導体素子4の
表面保護や半導体装置自身の強度確保のために封止樹脂
7で覆われている。
As shown in FIGS. 4A and 4B, a film substrate 1 has insulating and flexible properties, and a film substrate 2 made of a resin such as polyimide and a film substrate 2 made of copper or the like. And a lead wiring 3 formed of a metal foil. Regions of the lead wiring 3 that are connected to the protruding electrodes (not shown) of the semiconductor element 4 and that are not covered with the solder resist 5 are defined as inner leads 3a and inner leads 3
lead wiring 3 extended on film substrate 2 out of a
Of the outer leads 3
Called b. The lead wiring 3 is usually plated. On the electrode of the semiconductor element 4, a protruding electrode 6 necessary for connecting the electrode formed on the semiconductor element 4 and the inner lead 3a is formed. The height of the protruding electrode 6 varies, and there is a configuration in which the protruding electrode 6 is not formed. The area around the inner leads 3a is covered with a sealing resin 7 to protect the surface of the semiconductor element 4 and secure the strength of the semiconductor device itself.

【0008】次に、従来の半導体装置の製造方法につい
て説明する。
Next, a conventional method for manufacturing a semiconductor device will be described.

【0009】なお、前記した半導体装置の構成要件と同
一の構成要件には同一の符号を付す。
The same components as those of the semiconductor device described above are denoted by the same reference numerals.

【0010】図5および図6は、従来の半導体装置の製
造方法の各工程を示した断面図である。
FIGS. 5 and 6 are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

【0011】図5(a)に示すように、フィルム基材2
上に形成されたインナーリード3aと半導体素子4の電
極に形成された突起電極6とを位置合わせする。ここ
で、インナーリード3aの表面にはスズや金などによっ
てメッキが施されている。フィルム基材2の厚みは、3
8[μm]または25[μm]である。また、突起電極6の
高さは、10〜20[μm]である。
[0011] As shown in FIG.
The inner lead 3a formed above and the protruding electrode 6 formed on the electrode of the semiconductor element 4 are aligned. Here, the surface of the inner lead 3a is plated with tin, gold, or the like. The thickness of the film substrate 2 is 3
It is 8 [μm] or 25 [μm]. The height of the protruding electrode 6 is 10 to 20 [μm].

【0012】次に、図5(b)に示すように、半導体素
子4の裏面をステージ8の上面に載置し、フィルム基材
2の上面からボンディングツール9によって押圧する。
ここで、半導体素子4に形成された突起電極6とフィル
ム基板1のインナーリード3aを所定の位置に合わせて
熱圧着方式により接合するが、熱圧着方式とは、インナ
ーリード3aに施されたメッキ材と突起電極とを共晶融
合あるいは固相拡散させるために必要な温度(300〜
400[℃])で、荷重を加えながら接合する方式であ
る。
Next, as shown in FIG. 5B, the back surface of the semiconductor element 4 is placed on the upper surface of the stage 8 and pressed by the bonding tool 9 from the upper surface of the film substrate 2.
Here, the projecting electrode 6 formed on the semiconductor element 4 and the inner lead 3a of the film substrate 1 are joined to each other by a thermocompression bonding method in a predetermined position, and the thermocompression bonding method refers to plating performed on the inner lead 3a. Temperature required for eutectic fusion or solid phase diffusion between the material and the protruding electrode (300 to
400 [° C.]) and joining while applying a load.

【0013】次に、図5(c)に示すように、インナー
リード3aと突起電極6との接合部分と半導体素子4の
回路が存在する表面部分を保護し、半導体装置全体の機
械強度を確保するために封止樹脂7をフィルム基板1と
半導体素子4との隙間に樹脂供給ノズル10を使用して
注入する。封止後に捺印、検査を行ないCOF製品が完
成する。
Next, as shown in FIG. 5C, the joint between the inner lead 3a and the protruding electrode 6 and the surface where the circuit of the semiconductor element 4 exists are protected, and the mechanical strength of the entire semiconductor device is secured. For this purpose, a sealing resin 7 is injected into a gap between the film substrate 1 and the semiconductor element 4 using a resin supply nozzle 10. After sealing, stamping and inspection are performed to complete the COF product.

【0014】[0014]

【発明が解決しようとする課題】前記従来の半導体装置
の製造方法の封止工程では、大きい応力が突起電極の周
辺部分に発生することが分かっている。この応力は、図
5に示したように、インナーリード3aと突起電極6を
接合する際に発生する。応力発生原因は、封止工程にお
ける温度変化に伴うCOF構成材料の収縮率が材質によ
って異なるためである。すなわち、フィルム基材2の熱
膨張係数が半導体素子4の主材料であるシリコンの熱膨
張係数よりも大きい値を持つことに起因する。この収縮
率の差により、リード配線3と半導体素子4の電極との
接合部分である突起電極6には、せん断応力が発生す
る。この応力が、ある限界値を越えると突起電極6の周
辺に位置する半導体素子4の回路を機械的に破壊する不
具合が生じる。
It is known that in the sealing step of the conventional method for manufacturing a semiconductor device, a large stress is generated in the peripheral portion of the bump electrode. This stress is generated when the inner lead 3a and the bump electrode 6 are joined as shown in FIG. The cause of the stress is that the shrinkage rate of the COF constituent material according to the temperature change in the sealing step differs depending on the material. That is, this is because the thermal expansion coefficient of the film substrate 2 has a value larger than that of silicon which is a main material of the semiconductor element 4. Due to this difference in shrinkage, a shear stress is generated in the protruding electrode 6, which is a joint between the lead wiring 3 and the electrode of the semiconductor element 4. If the stress exceeds a certain limit value, a problem occurs that a circuit of the semiconductor element 4 located around the bump electrode 6 is mechanically broken.

【0015】図6は、従来の半導体装置の製造工程にお
ける不具合発生の状態を示した断面図である。
FIG. 6 is a cross-sectional view showing a state of occurrence of a defect in a conventional semiconductor device manufacturing process.

【0016】図6(a)に示すような従来の半導体装置
の製造方法の各工程における応力発生から不具合発生の
メカニズムについて説明する。A部は、以下の図面に示
す拡大する部分である。
A description will be given of the mechanism from the occurrence of stress to the occurrence of failure in each step of the conventional method for manufacturing a semiconductor device as shown in FIG. Part A is an enlarged part shown in the following drawings.

【0017】図6(b)に示すように、図6(a)のA
部では、温度降下に伴うフィルム基板1の収縮により半
導体素子4の中心線へ向かう方向(矢印11が示す方
向)にテープ収縮応力が働く。
As shown in FIG. 6B, A in FIG.
In the portion, the tape contraction stress acts in the direction toward the center line of the semiconductor element 4 (the direction indicated by the arrow 11) due to the contraction of the film substrate 1 due to the temperature drop.

【0018】このテープ収縮応力により、まず保護層1
2にインナーリード3aの先端側と対向する側にある金
属突起6の端部を起点とするクラック13が生じる。こ
の部分は保護層12の厚みが他の部分より薄くなってい
るため機械的に弱い部分であり、クラック13が発生し
やすい。
Due to the tape shrinkage stress, first, the protective layer 1
2, a crack 13 originating from the end of the metal projection 6 on the side facing the tip end of the inner lead 3a. This portion is a mechanically weak portion because the thickness of the protective layer 12 is thinner than other portions, and the crack 13 is easily generated.

【0019】次に、図6(c)に示すように、クラック
13は金属電極14の側面に沿う形で成長する。
Next, as shown in FIG. 6C, the crack 13 grows along the side surface of the metal electrode 14.

【0020】次に、図6(d)に示すように、金属電極
14とシリコン基板15の接合面の剥離へと進行する。
Next, as shown in FIG. 6D, the process proceeds to the separation of the bonding surface between the metal electrode 14 and the silicon substrate 15.

【0021】本発明は、前記従来の課題を解決する半導
体装置およびその製造方法であり、リード配線をフィル
ム基材から分離させて、封止工程において発生する応力
をリード配線で吸収する半導体装置およびその製造方法
を提供するものである。
The present invention is directed to a semiconductor device and a method of manufacturing the same which solve the above-mentioned conventional problems. The present invention relates to a semiconductor device in which a lead wiring is separated from a film base material and a stress generated in a sealing step is absorbed by the lead wiring. An object of the present invention is to provide a manufacturing method thereof.

【0022】[0022]

【課題を解決するための手段】前記従来の課題を解決す
るための本発明の半導体装置は、フィルム基材の表面に
形成されたリード配線と半導体素子の電極とが突起電極
を介して電気的に接続され、前記フィルム基材と前記半
導体素子の間に封止樹脂が充填され、前記突起電極が接
続される前記リード配線の前記フィルム基材側の面は、
前記フィルム基材の表面から分離している。
According to a semiconductor device of the present invention for solving the above-mentioned conventional problems, a lead wiring formed on a surface of a film substrate and an electrode of a semiconductor element are electrically connected to each other via a protruding electrode. The sealing material is filled between the film base and the semiconductor element, and the surface of the lead wiring to which the protruding electrode is connected is on the film base side.
It is separated from the surface of the film substrate.

【0023】また、リード配線のフィルム基板の表面か
ら離れている部分は、半導体素子が対向する範囲内にあ
る。
Further, the portion of the lead wiring away from the surface of the film substrate is within a range where the semiconductor element faces.

【0024】また、フィルム基板の表面と、前記フィル
ム基板の表面から離れたリード配線の前記フィルム側の
面との間の距離は、1〜20[μm]である。
The distance between the surface of the film substrate and the film-side surface of the lead wiring remote from the surface of the film substrate is 1 to 20 [μm].

【0025】このように、リード配線とフィルム基板が
分離することによって、半導体素子とフィルム基板との
間が封止樹脂によって封止される工程において、半導体
素子、フィルム基板、封止樹脂およびリード配線のそれ
ぞれの熱膨張係数が異なることに起因した応力を、フィ
ルム基板から離れて分離して可動のリード配線が吸収す
ることにより、突起電極と半導体素子の電極との境界部
における剥離や、半導体素子のクラックといった不具合
を防ぐことができる。
As described above, in the step of separating the semiconductor element and the film substrate with the sealing resin by separating the lead wiring and the film substrate, the semiconductor element, the film substrate, the sealing resin and the lead wiring are formed. The movable lead wiring separates and separates the stress caused by the different thermal expansion coefficients from the film substrate and absorbs the stress at the boundary between the protruding electrode and the electrode of the semiconductor element. Defects such as cracks can be prevented.

【0026】また、本発明の半導体装置の製造方法は、
フィルム基板の表面に形成されたリード配線と半導体素
子の電極とを突起電極を介して熱圧着するとともに、前
記フィルム基板の表面と、前記リード配線の前記突起電
極が熱圧着される部分の裏面側とを分離させる工程と、
前記半導体素子と前記フィルム基板との間に封止樹脂を
注入して硬化させる工程とからなる。
Further, a method of manufacturing a semiconductor device according to the present invention
The lead wiring formed on the surface of the film substrate and the electrode of the semiconductor element are thermocompressed via the protruding electrode, and the front surface of the film substrate and the back side of the portion where the protruding electrode of the lead wiring is thermocompressed. And a step of separating the
Injecting and curing a sealing resin between the semiconductor element and the film substrate.

【0027】また、フィルム基材の表面に形成されたリ
ード配線と半導体素子の電極とを突起電極を介して熱圧
着するとともに、前記フィルム基材の表面と、前記リー
ド配線の前記突起電極が熱圧着される部分の裏面側とを
分離させる工程は、前記リード配線と前記半導体素子の
電極とを突起電極を介して熱圧着する第1の工程と、前
記熱圧着のための圧力を開放し、前記フィルム基材の表
面から、前記リード配線の前記突起電極が熱圧着された
部分の裏面側を分離させる第2の工程とからなる。
In addition, the lead wire formed on the surface of the film substrate and the electrode of the semiconductor element are thermocompression-bonded via the protruding electrode, and the surface of the film substrate and the protruding electrode of the lead wire are thermally bonded. The step of separating the back side of the portion to be press-bonded is a first step of thermo-compression bonding the lead wiring and the electrode of the semiconductor element via a protruding electrode, and releasing the pressure for the thermo-compression bonding, A second step of separating a back surface side of a portion of the lead wiring to which the protruding electrode is thermocompression-bonded from a surface of the film substrate.

【0028】また、フィルム基板の表面に形成されたリ
ード配線と半導体素子の電極とを突起電極を介して熱圧
着するとともに、前記フィルム基板の表面と前記リード
配線とを分離させる工程では、前記熱圧着時の温度が4
00〜500[℃]であり、前記熱圧着の時間が1〜5
[s]である。
In the step of thermocompression-bonding the lead wiring formed on the surface of the film substrate and the electrode of the semiconductor element via the protruding electrode, and separating the surface of the film substrate and the lead wiring, Temperature during crimping is 4
00 to 500 [° C.], and the thermocompression bonding time is 1 to 5
[s].

【0029】このような半導体装置の製造方法により、
リード配線の突起電極が接続される部分の裏面側がフィ
ルム基板から離れた状態で、半導体素子とフィルム基板
との間に封止樹脂を注入して封止するので、半導体素
子、フィルム基板、封止樹脂およびリード配線のそれぞ
れの熱膨張係数が異なることに起因した応力を、フィル
ム基板から離れて分離して可動のリード配線が吸収する
ことにより、突起電極と半導体素子の電極との境界部に
おける剥離や、半導体素子のクラックといった不具合を
防ぐことができる。
According to such a method of manufacturing a semiconductor device,
Since the sealing resin is injected and sealed between the semiconductor element and the film substrate in a state where the back surface of the portion where the protruding electrode of the lead wiring is connected is away from the film substrate, the semiconductor element, the film substrate, and the sealing are formed. Separation at the boundary between the protruding electrode and the electrode of the semiconductor element by absorbing the stress caused by the different thermal expansion coefficients of the resin and the lead wiring away from the film substrate and absorbing the stress by the movable lead wiring. In addition, problems such as cracks in the semiconductor element can be prevented.

【0030】また、半導体素子とフィルム基板との間に
注入する封止樹脂は、液状の樹脂のみからなる。
The sealing resin injected between the semiconductor element and the film substrate is made of only a liquid resin.

【0031】このように、封止樹脂として、固体のフィ
ラーを含まない樹脂を用いることにより、リード配線と
フィルム基板との間に封止樹脂が流入するので、封止工
程の後に、半導体素子とフィルム基板との間において封
止樹脂が浸透しない部分が発生せず、半導体素子とフィ
ルム基板との間における亀裂や剥離といった不具合の発
生を防止できる。
As described above, by using a resin containing no solid filler as the sealing resin, the sealing resin flows between the lead wiring and the film substrate. A portion where the sealing resin does not penetrate between the film substrate and the film substrate does not occur, and it is possible to prevent defects such as cracks and peeling between the semiconductor element and the film substrate.

【0032】[0032]

【発明の実施の形態】以下、本発明の半導体装置および
その製造方法の一実施形態について図面を参照しながら
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

【0033】まず、本実施形態の半導体装置について説
明する。
First, the semiconductor device of this embodiment will be described.

【0034】図1は、本実施形態の半導体装置を示した
平面図であり、図2は図1のA−A1箇所における断面
図である。
FIG. 1 is a plan view showing a semiconductor device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along a line AA1 in FIG.

【0035】図1に示すように、ポリイミドからなるフ
ィルム基材8に複数本のリード配線9が形成されてフィ
ルム基板10が構成され、半導体素子11の電極に形成
された突起電極とリード配線9とが電気的に接続されて
いる。半導体素子11とフィルム基板10との間には封
止樹脂12が注入され、封止されている。また、半導体
素子11近傍のリード配線9の表面にはソルダーレジス
ト13が形成され、リード配線9が他の導電部材とショ
ートすることを防止している。
As shown in FIG. 1, a film substrate 10 is formed by forming a plurality of lead wires 9 on a film base 8 made of polyimide, and the protruding electrodes formed on the electrodes of the semiconductor element 11 and the lead wires 9 are formed. And are electrically connected. A sealing resin 12 is injected and sealed between the semiconductor element 11 and the film substrate 10. Further, a solder resist 13 is formed on the surface of the lead wiring 9 near the semiconductor element 11 to prevent the lead wiring 9 from short-circuiting with another conductive member.

【0036】次に、半導体素子の電極とリード配線とが
突起電極を介して電気的に接続された部分を詳細に説明
する。
Next, a portion where the electrode of the semiconductor element is electrically connected to the lead wiring via the protruding electrode will be described in detail.

【0037】図2に示すように、半導体素子11の電極
14の周囲には、ポリイミド膜からなる保護膜15が形
成されている。一端がフィルム基材8の表面から分離
し、他端がフィルム基材8の表面に形成されたリード配
線9の一端と、半導体素子11の電極に形成された突起
電極16とが電気的に接続されている。リード配線9が
フィルム基材8から分離する部分は、半導体素子11が
対向する範囲内である。
As shown in FIG. 2, a protective film 15 made of a polyimide film is formed around the electrode 14 of the semiconductor element 11. One end is separated from the surface of the film base 8, and the other end is electrically connected to one end of the lead wire 9 formed on the surface of the film base 8 and the protruding electrode 16 formed on the electrode of the semiconductor element 11. Have been. The portion where the lead wiring 9 is separated from the film substrate 8 is within a range where the semiconductor element 11 faces.

【0038】また、リード配線9とフィルム基板10と
の間には、フィラーを含まない樹脂からなる封止樹脂1
2が充填され、封止されている。フィルム基材8とリー
ド配線9との密着面では、ニッケルまたはクロムからな
る金属層を介している。本実施形態で、封止樹脂12と
して、フィラーを含まない樹脂を用いたのは、フィルム
基材8から分離するリード配線9は、なだらかに形成さ
れており、リード配線9とフィルム基材8との分離部分
においては、非常に微小な隙間であることから、封止樹
脂12はこの微小な隙間に入り込むフィラーを含まない
樹脂が望ましいからである。ここで、フィルム基材8の
表面とリード配線9のフィルム基材8側の面との距離
は、1〜20[μm]である。
A sealing resin 1 made of a resin containing no filler is provided between the lead wiring 9 and the film substrate 10.
2 are filled and sealed. The contact surface between the film substrate 8 and the lead wiring 9 is provided with a metal layer made of nickel or chromium. In this embodiment, the reason why the resin containing no filler is used as the sealing resin 12 is that the lead wiring 9 separating from the film base material 8 is formed smoothly, and the lead wiring 9 and the film base material 8 Is a very small gap in the separation portion, so that the sealing resin 12 is desirably a resin containing no filler that enters the minute gap. Here, the distance between the surface of the film substrate 8 and the surface of the lead wiring 9 on the film substrate 8 side is 1 to 20 [μm].

【0039】発明者らの実験によれば、フィルム基材と
リード配線のフィルム基材側の面との距離が1[μm]よ
りも小さい場合は、リード配線がフィルム基板の表面に
対して自由に可動することが困難である。また、フィル
ム基材とリード配線のフィルム基材側の面との距離が2
0[μm]よりも大きい場合は、封止工程において、リー
ド配線に対する封止樹脂の流動の抵抗が大きくなり、リ
ード配線が不安定になるという問題が発生する。
According to the experiments by the inventors, when the distance between the film substrate and the surface of the lead wiring on the film substrate side is smaller than 1 [μm], the lead wiring is free with respect to the surface of the film substrate. It is difficult to move. In addition, the distance between the film substrate and the surface of the lead wiring on the film substrate side is 2 mm.
If it is larger than 0 [μm], in the sealing step, the flow resistance of the sealing resin to the lead wiring becomes large, which causes a problem that the lead wiring becomes unstable.

【0040】以上、本実施形態の半導体装置は、リード
配線の突起電極が接続する部分をフィルム基材から分離
することによって、封止工程において発生する応力をリ
ード配線で吸収することができ、突起電極近傍の半導体
素子表面の保護膜におけるクラック等の不具合を防止で
きる。
As described above, according to the semiconductor device of the present embodiment, the stress generated in the sealing step can be absorbed by the lead wiring by separating the portion of the lead wiring to which the projecting electrode is connected from the film substrate. Problems such as cracks in the protective film on the surface of the semiconductor element near the electrodes can be prevented.

【0041】次に、本実施形態の半導体装置の製造方法
について説明する。
Next, a method of manufacturing the semiconductor device of the present embodiment will be described.

【0042】なお、前記した半導体装置の構成要件と同
一の構成要件には同一の符号を付し、同一の内容につい
ては省略する。
The same components as those of the semiconductor device described above are denoted by the same reference numerals, and the same contents are omitted.

【0043】図3は、本実施形態の半導体装置の製造方
法の各工程を示した断面図である。
FIG. 3 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the present embodiment.

【0044】まず、図3(a)に示すように、表面にリ
ード配線9が形成されたフィルム基板10と、電極に突
起電極16が形成された半導体素子11とを用意し、リ
ード配線9と突起電極16とを位置合わせする。なお、
リード配線9の表面には、他の導電部材とのショートを
防止するために、ソルダーレジスト13が形成されてい
る。
First, as shown in FIG. 3A, a film substrate 10 having lead wires 9 formed on the surface and a semiconductor element 11 having projecting electrodes 16 formed on the electrodes are prepared. The projection electrode 16 is positioned. In addition,
A solder resist 13 is formed on the surface of the lead wiring 9 in order to prevent a short circuit with another conductive member.

【0045】次に、図3(b)に示すように、半導体素
子11の裏面を第1のツール18上に載置し、フィルム
基板10の裏面から第2のツール19により400〜5
00[℃]に加熱しながら加圧することにより、半導体素
子11の電極に形成された突起電極16とフィルム基材
8の表面に形成されたリード配線9とを熱圧着する。こ
こで、加熱されることにより、フィルム基材8とリード
配線9との界面の密着力は低下している。
Next, as shown in FIG. 3B, the back surface of the semiconductor element 11 is placed on the first tool 18, and 400 to 5 mm from the back surface of the film substrate 10 by the second tool 19.
By applying pressure while heating to 00 [° C.], the protruding electrodes 16 formed on the electrodes of the semiconductor element 11 and the lead wires 9 formed on the surface of the film base 8 are thermocompression bonded. Here, due to the heating, the adhesion at the interface between the film substrate 8 and the lead wiring 9 is reduced.

【0046】次に、図3(c)に示すように、第1のツ
ール18と第2のツール19により与えていた圧力を開
放し、また、温度を室温に低下させることで、フィルム
基材8が収縮して応力が発生し、リード配線9とフィル
ム基材8とが分離する。ここで、突起電極16とリード
配線9との接合部の加熱温度は、本実施形態では、40
0〜500[℃]に設定したが、リード配線9とフィルム
基材8が分離する温度は、400〜500[℃]の限定さ
れるものではなく、フィルム基材8の材料およびリード
配線9の材料に依存する。
Next, as shown in FIG. 3C, the pressure applied by the first tool 18 and the second tool 19 is released, and the temperature is lowered to room temperature, whereby the film substrate 8 shrinks to generate stress, and the lead wiring 9 and the film substrate 8 are separated. Here, the heating temperature of the junction between the protruding electrode 16 and the lead wiring 9 is 40 in the present embodiment.
Although set at 0 to 500 [° C.], the temperature at which the lead wiring 9 and the film base material 8 are separated is not limited to 400 to 500 [° C.]. Depends on the material.

【0047】次に、図3(d)に示すように、半導体素
子11とフィルム基板10との間に封止樹脂12を注入
し、加熱することにより封止樹脂12を硬化させた後、
室温に冷却する。
Next, as shown in FIG. 3D, a sealing resin 12 is injected between the semiconductor element 11 and the film substrate 10, and the sealing resin 12 is cured by heating.
Cool to room temperature.

【0048】なお、本実施形態では、フィルム基材8の
線膨張係数が10〜15[ppm/℃]、厚さ40[μm]
程度であり、半導体素子11の形状が、長辺10〜20
[mm]、短辺0.5〜3[mm]である。
In this embodiment, the film substrate 8 has a coefficient of linear expansion of 10 to 15 ppm / ° C. and a thickness of 40 μm.
And the shape of the semiconductor element 11 is 10 to 20
[mm] and the short side is 0.5 to 3 [mm].

【0049】以上、本実施形態の半導体装置の製造方法
は、リード配線の突起電極が接続する部分をフィルム基
材から分離することによって、封止工程において発生す
る応力をリード配線で吸収することができ、突起電極近
傍の半導体素子表面の保護膜におけるクラック等の不具
合を防止できる。
As described above, according to the method of manufacturing a semiconductor device of the present embodiment, the stress generated in the sealing step can be absorbed by the lead wiring by separating the portion of the lead wiring to which the projecting electrode is connected from the film base material. This can prevent defects such as cracks in the protective film on the surface of the semiconductor element near the protruding electrodes.

【0050】[0050]

【発明の効果】本発明では、半導体素子の電極に形成さ
れた突起電極と電気的に接続するリード配線が、フィル
ム基材の表面から分離しているために、半導体素子とフ
ィルム基材との間を封止する封止工程において発生する
応力を、フィルム基材から分離したリード配線によって
吸収することができ、突起電極近傍の接続部におけるク
ラック等の不具合の発生を防止できる。
According to the present invention, since the lead wiring electrically connected to the protruding electrode formed on the electrode of the semiconductor element is separated from the surface of the film base, the semiconductor element and the film base are separated. The stress generated in the sealing step of sealing the gap can be absorbed by the lead wiring separated from the film base material, and the occurrence of a defect such as a crack in the connection portion near the protruding electrode can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の半導体装置を示す平面図FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施形態の半導体装置を示す断面図FIG. 2 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図3】本発明の一実施形態の半導体装置の製造方法の
各工程を示す断面図
FIG. 3 is a sectional view showing each step of a method for manufacturing a semiconductor device according to one embodiment of the present invention

【図4】従来の半導体装置を示す図FIG. 4 is a diagram showing a conventional semiconductor device.

【図5】従来の半導体装置の製造方法の各工程を示す断
面図
FIG. 5 is a sectional view showing each step of a conventional method for manufacturing a semiconductor device.

【図6】従来の半導体装置の製造方法の各工程を示す断
面図
FIG. 6 is a sectional view showing each step of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 フィルム基板 2 フィルム基材 3 リード配線 4 半導体素子 5 ソルダーレジスト 6 突起電極 7 封止樹脂 8 フィルム基材 9 リード配線 10 フィルム基板 11 半導体素子 12 封止樹脂 13 ソルダーレジスト 14 電極 15 保護膜 16 突起電極 DESCRIPTION OF SYMBOLS 1 Film board 2 Film base 3 Lead wiring 4 Semiconductor element 5 Solder resist 6 Protruding electrode 7 Sealing resin 8 Film base 9 Lead wiring 10 Film substrate 11 Semiconductor element 12 Sealing resin 13 Solder resist 14 Electrode 15 Protective film 16 Projection electrode

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 フィルム基材の表面に形成されたリード
配線と半導体素子の電極とが突起電極を介して電気的に
接続され、前記フィルム基材と前記半導体素子の間に封
止樹脂が充填され、前記突起電極が接続される前記リー
ド配線の前記フィルム基材側の面は、前記フィルム基材
の表面から分離していることを特徴とする半導体装置。
1. A lead wire formed on the surface of a film substrate and an electrode of a semiconductor element are electrically connected via a protruding electrode, and a sealing resin is filled between the film substrate and the semiconductor element. A semiconductor device, wherein a surface of the lead wiring to which the protruding electrode is connected on the film substrate side is separated from a surface of the film substrate.
【請求項2】 リード配線のフィルム基材の表面から離
れている部分は、半導体素子に対向する範囲内にあるこ
とを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a portion of the lead wiring away from the surface of the film substrate is within a range facing the semiconductor element.
【請求項3】 フィルム基材の表面と、前記フィルム基
材の表面から離れたリード配線の前記フィルム基材側の
面との間の距離は、1〜20[μm]であることを特徴と
する請求項1に記載の半導体装置。
3. The distance between the surface of the film substrate and the surface of the lead wiring remote from the surface of the film substrate on the film substrate side is 1 to 20 [μm]. The semiconductor device according to claim 1.
【請求項4】 フィルム基材の表面に形成されたリード
配線と半導体素子の電極とを突起電極を介して熱圧着す
るとともに、前記フィルム基材の表面と、前記リード配
線の前記突起電極が熱圧着される部分の裏面側とを分離
させる工程と、前記半導体素子と前記フィルム基材との
間に封止樹脂を注入して硬化させる工程とからなる半導
体装置の製造方法。
4. A lead wire formed on a surface of a film substrate and an electrode of a semiconductor element are thermocompression-bonded via a protruding electrode, and the surface of the film substrate and the protruding electrode of the lead wire are thermally bonded. A method of manufacturing a semiconductor device, comprising: a step of separating a back surface side of a portion to be press-bonded; and a step of injecting and curing a sealing resin between the semiconductor element and the film substrate.
【請求項5】 フィルム基材の表面に形成されたリード
配線と半導体素子の電極とを突起電極を介して熱圧着す
るとともに、前記フィルム基材の表面と、前記リード配
線の前記突起電極が熱圧着される部分の裏面側とを分離
させる工程は、前記リード配線と前記半導体素子の電極
とを突起電極を介して熱圧着する第1の工程と、前記熱
圧着のための圧力を開放し、前記フィルム基材の表面か
ら、前記リード配線の前記突起電極が熱圧着された部分
の裏面側を分離させる第2の工程とからなることを特徴
とする請求項4に記載の半導体装置の製造方法。
5. A thermo-compression bonding between a lead wiring formed on a surface of a film base and an electrode of a semiconductor element via a protruding electrode, and the surface of the film base and the protruding electrode of the lead wiring are heat-bonded. The step of separating the back surface side of the portion to be crimped is a first step of thermocompression bonding the lead wiring and the electrode of the semiconductor element via a protruding electrode, and releasing the pressure for the thermocompression bonding, 5. The method according to claim 4, further comprising: a second step of separating a back surface of a portion of the lead wiring on which the protruding electrode is thermocompression-bonded from a surface of the film base. 6. .
【請求項6】 フィルム基材の表面に形成されたリード
配線と半導体素子の電極とを突起電極を介して熱圧着す
るとともに、前記フィルム基材の表面と前記リード配線
とを分離させる工程では、前記熱圧着時の温度が400
〜500[℃]であり、前記熱圧着の時間が1〜5[s]で
あることを特徴とする請求項4に記載の半導体装置の製
造方法。
6. The step of thermocompression bonding a lead wiring formed on a surface of a film substrate and an electrode of a semiconductor element via a protruding electrode, and separating the surface of the film substrate from the lead wiring. The temperature during the thermocompression bonding is 400
5. The method according to claim 4, wherein the temperature is approximately 500 ° C., and the time of the thermocompression bonding is approximately 1 to 5 seconds. 6.
【請求項7】 半導体素子とフィルム基板との間に注入
する封止樹脂は、液状の樹脂のみからなることを特徴と
する請求項4に記載の半導体装置の製造方法。
7. The method for manufacturing a semiconductor device according to claim 4, wherein the sealing resin injected between the semiconductor element and the film substrate comprises only a liquid resin.
JP2001164499A 2001-05-31 2001-05-31 Semiconductor device and manufacturing method thereof Expired - Lifetime JP4562950B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2000294598A (en) * 1999-04-08 2000-10-20 Casio Comput Co Ltd Semiconductor device and its manufacture
JP2000302841A (en) * 1999-02-18 2000-10-31 Three Bond Co Ltd Epoxy resin composition
JP2001019745A (en) * 1999-07-07 2001-01-23 Sumitomo Bakelite Co Ltd Semiconductor device and its production
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JPH0465136A (en) * 1990-07-05 1992-03-02 Fujitsu Ltd Semiconductor device
JPH09252063A (en) * 1996-03-14 1997-09-22 Hitachi Ltd Lead frame, semiconductor integrated circuit device using the frame and manufacture thereof
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Publication number Priority date Publication date Assignee Title
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