JP2002358774A - Magnetic memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory cell structure in which the tolerance of a magnetization inversion current can be extended in order to more improve mass production yield, storage capacity, an access time, or the like of a magnetic memory device than heretofore. SOLUTION: In the magnetic memory device, which is provided with magneto resistive storage elements 1 arranged in a matrix shape and write lines 20, 30 arranged for every row and column and reverses a magnetizing direction of each storage element 1 selectively by a current magnetic field generated by the write lines 20, 30, in at least either of write lines 20, 30 for every row or column, its current path can be switched by main lines 21, 31 arranged adacently to the storage elements 1 and bypass lines 22, 32 arranged apart from the storage elements 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a magnetic memory device used as a memory device for storing information.

[0002]

2. Description of the Related Art Recently, an MRAM (Magnetic Ran) has been used as one of magnetic memory devices used as a memory device.
dom Access Memory) (eg, Wang
et al., IEEE Trans. Magn. 33 (1997), 4498). MRA
M is Giant Magnetoresistive (GM)
R) Effect type or Tunnel Magnetore
A SIStive (TMR) effect type storage element is used to store information by using the reversal of the magnetization direction in the storage element.

A storage element used in an MRAM is a GMR.
Both the effect type and the TMR effect type are formed by laminating a free layer and a fixed layer made of a soft magnetic material and a non-magnetic layer interposed between them, and the electric resistance of the element depends on the direction of magnetization of the free layer. In a different manner, the magnetization direction of the fixed layer facing the free layer is fixed directly or indirectly by an antiferromagnetic material or the like. FIG. 16 is a specific example of the resistance-current characteristics of the storage element. Here, when the magnetization states of the free layer and the fixed layer are antiparallel (opposite to each other), the resistance values at both ends of the element are in the high state, and this is set to “0”.
Is defined as the magnetization state. When the magnetization states of the free layer and the fixed layer are parallel (in the same direction), the resistance values at both ends of the element are in a low state, which is defined as a magnetization state representing “1”.

Writing of information to such a storage element is performed by applying a magnetic field exceeding the magnetic field Hc required for the magnetization reversal of the free layer to the storage element. For that, M
As shown in FIG. 17, for example, a RAM includes a word line 2 and a bit line 3 which are substantially orthogonal to each other, in addition to a GMR effect type or TMR effect type storage element 1, and is sandwiched between them from above and below. The storage element 1 is arranged in such a state as to be located in these intersection regions. When the current magnetic field induced by the current flowing through the word line 2 and the bit line 3 exceeds the magnetic field Hc required for the magnetization reversal of the storage element 1, the magnetization direction of the free layer of the storage element 1 is reversed. become. The positive / negative current that induces a magnetic field exceeding Hc is referred to as a magnetization reversal current.
Here, for convenience of description, a conductor for inducing a magnetic field mainly in the easy axis direction of the storage element 1 is replaced with the bit line 3,
A conductor for inducing a magnetic field in the direction of the hard axis is a word line 2.

On the other hand, reading of information from the storage element 1 is performed by using the magnetoresistance effect in the storage element 1. That is, information is read from the storage element 1 by utilizing the fact that the element electric resistance changes depending on the direction of magnetization of the free layer. Therefore, in MRAM,
For example, as shown in FIG. 18, one diode or transistor 4 is provided corresponding to one storage element 1, and one memory cell 5 is configured by these. One end of the storage element 1 is connected to a bit line 3 which is shared with a sense line for selecting the storage element 1 from which information is to be read, and the other end is a logic for selecting an element when reading information. It is connected to a circuit (not shown), which enables information reading using the magnetoresistance effect. That is, when the read permission line R / W is set to the high state according to the instruction from the logic circuit, the diode or the transistor 4 is set to the on state, the terminal voltage of the storage element 1 is sent to the sense amplifier 6, and the storage element 1 The state of the magnetization direction is read.

By the way, in an MRAM, as shown in FIG. 19, for example, memory cells 5 are usually arranged in a matrix, thereby achieving memory integration.
The word lines 2 and the bit lines 3 are arranged for each column and each row of each memory cell 5 in a matrix. A word line current pulse and a bit line current pulse for inducing a magnetic field exceeding Hc are supplied to the word line 2 and the bit line 3 from different current sources. At this time, the polarity of the bit line current pulse is determined by the state of the data bit in the storage element 1. Further, between the word line 2 and the current source, switch circuits SW01, SW02, SW03,... For selectively supplying a word line current pulse on a specific column address are provided. Further, between the bit line 3 and the current source, there are provided switch circuits SW10, SW20, SW30... For selectively flowing a bit line current pulse on a specific row address. The column address selection signal (WL Select)
A row address selection signal (BL Select) is synthesized based on an address signal externally supplied to the MRAM.

With such a configuration, in the MRAM,
Even if the memory cells 5 are arranged in a matrix, the storage element 1 to which information is to be written can be specified. In other words, if a magnetic field is applied to all of the memory cells 5 arranged in a matrix, the magnetization state may be changed up to the storage element 1 whose magnetization state is not desired to be changed. Bit line 3 of a specific row
By applying the word line current pulse and the bit line current pulse only to the memory cell 1, the storage element 1 located at the intersection of the word line 2 and the bit line 3 can be subjected to information writing. This is because when a magnetic field is applied in the direction of the easy axis, the magnetization direction is reversed at a certain critical value to the direction of the applied magnetic field, but when the magnetic field is applied not only in the direction of the easy axis but also in the direction of the hard axis. Is based on the fact that the absolute value of the reversal magnetic field decreases.

Since the word line 2 and the bit line 3 are substantially perpendicular to each other, the magnetization reversal current at this time depends on the combination of the current magnetic fields induced by the currents flowing through them, for example, PtMn / CoFe / Ru / CoFe. /
With a film configuration such as Al ₂ O ₃ / CoFe / Ta, 0.13
In the case of the storage element 1 having a size of μm × 0.26 μm, an asteroid (star) distribution as shown in FIG. 20 is obtained. In this case, if the bit information “0” is realized, the bit information belongs to a region outside the asteroid curve in the drawing (a region hatched to the lower right in the first quadrant and the second quadrant in the drawing). The combination of the magnetization reversal currents may be applied to the word line 2 and the bit line 3. If the bit information “1” is to be realized, the bit information belongs to a region outside and below the asteroid curve in the drawing (a region hatched to the right in the third and fourth quadrants in the drawing). The combined magnetization reversal current
What is necessary is just to apply to the word line 2 and the bit line 3. At this time, the reason why the magnetization reversal current is limited to the hatched area in the drawing and is not spread over the entire quadrant except inside the asteroid curve is that the storage element 1 in the memory cell 5 adjacent to the information writing target and the information This is for preventing the magnetization state of the storage element 1 or the like in another memory cell 5 on the same column or the same row as the writing target from being changed.

[0009]

However, the magnetization reversal current for reversing the magnetization direction of the storage element 1 depends on, for example, the magnetic material constants of the storage element 1 and variations in the element shape, as shown in FIG. Take a value distributed in a certain range (see a dot area in the figure). Therefore, when determining the combination of the word line current pulse and the bit line current pulse, it is necessary to reflect the expected variation of the magnetization reversal current and the like. That is, the magnetization reversal current must be set so as to be located in a region outside the asteroid curve shown in FIG. 20 to some extent.

On the other hand, since the memory cells 5 are arranged in a matrix, the magnetization reversal current is generated, for example, in order to avoid the magnetization reversal of the adjacent element due to the interaction due to the leakage current magnetic field, the magnetostatic interaction and the like. As shown in FIG.
A certain crosstalk margin is required (see the grid pattern area in the figure). That is, in order to reliably prevent the magnetization reversal of the adjacent element, the magnetization reversal current must not only be spread over the entire quadrant except the inside of the asteroid curve, but also have a more constant crosstalk margin.

In consideration of these restrictions, the magnetization reversal current can be used only in a very limited range in practice. For example, if the range that can be actually set in the first quadrant of FIG. 20 is shown, as in a hatched area shown in FIG.
Only a small area is relevant.

The range of such a magnetization reversal current, that is, the combination range of the word line current pulse and the bit line current pulse allowed for the word line 2 and the bit line 3 is as follows.
It is desirable to be as wide as possible. For example, an MRAM
If the variation of the magnetization reversal current within the MRAM reaches 50% or more, the upper limit and the lower limit of the allowable magnetization reversal current coincide, and the MRAM becomes a completely defective product. Even when the variation of the magnetization reversal current is 50% or less, if the allowable range of the magnetization reversal current disappears by securing the crosstalk margin, the MRAM is still defective. In order to reduce the crosstalk margin, it is conceivable to increase the interval between the memory cells 5, but there is a problem that the storage capacity per area decreases.
The access time of the MRAM tends to be inversely proportional to the magnetization reversal current. However, if the allowable magnetization reversal current range is narrow, the degree of freedom of increasing the magnetization reversal current and improving the access time is lost.

As described above, in order to improve the mass production yield, storage capacity, access time, and the like in the magnetic memory device represented by the MRAM as compared with the prior art, the range of the allowable magnetization reversal current is expanded as much as possible. There is a need for a simple memory cell structure.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has a magnetoresistive effect type storage element arranged in a matrix, and each row and column of the storage element. In a magnetic memory device comprising a write line arranged in a row and selectively inverting the magnetization direction of each storage element by a current magnetic field generated by the write line, a write line for each row and a write line for each column At least one of
A main line arranged close to the storage element, and a bypass line arranged farther from the storage element than the main line, so that a current path can be switched between the main line and the bypass line. It is characterized by having been done.

According to the magnetic memory device having the above configuration, even when the same current is applied to the write line, the current is stored when the current path is set to the main line and when the current path is set to the bypass line. Due to the difference in the distance from the element, the magnitude of the current magnetic field that reaches the storage element differs. Therefore, even if the storage elements are arranged in a matrix,
If the current path is switched between the storage element for reversing the magnetization direction and another storage element, the range of the allowable magnetization reversal current is expanded as compared with the case where the switching is not performed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A magnetic memory device according to the present invention will be described below with reference to the drawings.

First, an MRAM (magnetic memory device) according to the first embodiment of the present invention will be described. As shown in FIG. 1, the MRAM described in this embodiment includes a word line 20 and a bit line 30 that are substantially orthogonal to each other, in addition to the storage element 1 that is substantially the same as the conventional one. However, unlike the conventional one, the word line 20 is provided with a main line 21 arranged close to the storage element 1, a word line 20 arranged farther from the storage element 1 than the main line 21, and And an insulated bypass line 22. Also, the bit line 30
Similarly, a main line 31 and a bypass line 32 are provided. The storage element 1 is connected to the main line 21 of the word line 20.
And the main line 31 of the bit line 30 are arranged so as to be sandwiched from above and below, and to be located in the intersection area between them.

Further, the word line 20 and the bit line 30
, Line path select signal lines 41 and 42 are provided along the bypass lines 22 and 32, respectively. The line path select signal lines 41 and 42 are connected to the main lines 21 and 31 and the bypass lines 22 and 3 as described later.
2 is a signal line for supplying a control signal for instructing a current path switching between the control circuit 2 and the control circuit 2.

As shown in FIG. 2, one memory cell 50 is provided with one diode or transistor 4 corresponding to one storage element 1 in substantially the same manner as in the prior art. However, as described above, since each of the word line 20 and the bit line 30 is composed of two systems of the main lines 21 and 31 and the bypass lines 22 and 32, the memory cell 5
0, the current path is divided into the main lines 21 and 31 and the bypass line 2
Switch circuits SW1 to SW4 are provided correspondingly to enable switching between the circuits 2 and 32. The current paths of the word line 20 and the bit line 30 are selectively switched to one of the main lines 21 and 31 and the bypass lines 22 and 32 by the switch circuits SW1 to SW4. Note that among the switch circuits SW1 to SW4, the switch circuit SW provided corresponding to the word line 20 is provided.
1, SW2 is connected to a line path select signal line 42 along the bit line 30. The switch circuits SW3 and SW4 provided corresponding to the bit lines 30 are connected to the word lines 20.
Are connected to a line path select signal line 41 along the line.

As shown in FIG. 3, each of the switch circuits SW1 to SW4 may be configured using an n-channel MOS transistor, a p-channel MOS transistor, and an inverter. In this case, control signals from the line path select signal lines 41 and 42 are supplied to the On / Off terminals, and the main lines 21 and 31 and the bypass lines 22 and 32 are connected to the other terminals, respectively. In addition,
Each of the switch circuits SW1 to SW4 may be configured using, for example, a thyristor element instead of a MOS transistor.

As shown in FIG. 4, the memory cells 50 including the switch circuits SW1 to SW4 are arranged in a matrix as in the conventional case. The word lines 20 and the bit lines 30 are also arranged for each column and each row of each memory cell 50. Furthermore, these word lines 20
Since line path select signal lines 41 and 42 are provided along bit line 30 and bit line 30, respectively, line path select signal lines 41 and 42 are also provided for each column and row of memory cell 50. Have been.

Each of the line path select signal lines 41 and 42 is supplied with a control signal to the switch circuits SW1 to SW4.
A control signal (BL P
athSelect signal) as the word line 20
A column address selection signal (WL Select) for specifying the column (Column) is used, thereby switching the switch circuits SW3 and SW4 provided corresponding to the bit line 30. On the other hand, as a control signal (WL Path Select signal) to be applied to the line path select signal line 42, a row address selection signal (BL Select) for specifying the row of the bit line 30 to which current is applied is used. To switch the switch circuits SW1 and SW2 provided corresponding to the word line 20.

In the MRAM configured as described above, each switch circuit is switched according to the state (High / Low) of the control signal (BL Path Select signal, WL Path Select signal) applied to each line path select signal line 41, 42. SW1 to SW4 are switched. Therefore, the current paths in the word line 20 and the bit line 30 are also selectively switched to one of the main lines 21 and 31 and the bypass lines 22 and 32 in accordance with the switching of the switch circuits SW1 to SW4.

At this time, the distance to the storage element 1 is different between the main lines 21 and 31 and the bypass lines 22 and 32. The distance from the storage element 1 directly affects the magnitude of the current magnetic field that reaches the storage element 1. That is, even when the same current is applied, when the current paths are set to the main lines 21 and 31 (hereinafter referred to as “Path A”) and when the current paths are set to the bypass lines 22 and 32 (hereinafter referred to as “Path B”). In the former case, the current magnetic field that reaches the storage element 1 is larger than in the latter case. This means that Path
This means that the asteroid characteristics (the magnitude of the asteroid curve) are different between A and Path B.

For example, PtMn / CoFe / Ru / Co
With a film configuration of Fe / Al ₂ O ₃ / CoFe / Ta,
For a storage element 1 having a size of 0.13 μm × 0.26 μm, main lines 21 and 31 adjacent to the storage element 1 and bypass lines 22 and 32 separated from the main lines 21 and 31 by about 230 nm. FIG. 5 shows an example of the measurement of the asteroid curve in the case where each was formed. According to the example in the figure, the area of the asteroid curve in the case of Path B is several times as large as that in the case of Path A.

Therefore, by selecting Path A for one storage element 1 to which information is to be written and selecting Path B for the other storage element 1, information is stored in the one storage element 1. The range of the magnetization reversal current allowed at the time of writing is not limited to the region specified by the asteroid curve in the case of Path A (see FIG. 20), but also
The area is expanded to a range (hatched area in FIG. 5) surrounded by two asteroid curves of each of thA and PathB. This region is further enlarged as the size of the asteroid curve in the case of Path B is increased, that is, as the distance between the main lines 21 and 31 and the bypass lines 22 and 32 is increased.

When the range of the magnetization reversal current is expanded, the range of the combination of the word line current pulse and the bit line current pulse allowed for the word line 20 and the bit line 30 is also widened, and various combinations can be realized. for that reason,
It is easy to secure a crosstalk margin while considering the variation of the magnetization reversal current, and the mass production yield, storage capacity, access time, and the like of the MRAM are improved as compared with the conventional case.

In order to realize such an expansion of the magnetization reversal current range, Path A is selected for the storage element 1 on which information is to be written, and Pa is selected for the other storage elements 1.
It is necessary to perform switching such as selecting th B. In the MRAM described in the present embodiment, the switching is
The column address selection signal (WL Select) and the row address selection signal (BL Select) are used as they are, in other words, they are connected to the switch circuit SW in each memory cell 50.
1 to SW4 control signals (BL Path Select signal, WL Path Se
lect signal).

Here, an example of the switching operation between Path A and Path B will be described with reference to FIG. For example, three rows x
The case where information is written to the storage element 1 in one memory cell C22 of the three rows of memory cell groups C11 to C33 will be described as an example.

In this case, based on an address signal externally applied to the MRAM, a column address selection signal (WL Select) for selecting a second column (Column 2) and a second row (Row) are selected.
The selection signal (BL Select) of the row address for selecting 2) is synthesized. Then, the selection signal (WL S
The switch circuits SW01 to SW03 are switched according to the selection (elect), and the word line current pulse is supplied from the current source to only the word line 20 in Column2. This allows the Column
From the second word line 20, the current magnetic field generated by the word line current pulse affects each memory cell 50 on Column 2.

However, at this time, the selection signal (BL Select) of the row address for selecting Row2 is applied to the bit line 30 of Row2.
Not only the switching of the switch circuits SW10 to SW30 for supplying the bit line current pulse to the
Each of the memory cells C21 and C2 on the row 2 is transmitted as a path select signal) through the line path select signal line 42 of the row 2.
2, also given to C23. Then, by the control signal (WL Path Select signal), each memory cell C21,
The switch circuits SW1 and SW2 in C22 and C23 switch the current path to the main line 21 (Path A side).

Therefore, each memory cell C1 on Column2
Of the memory cells C12, C32, C32, the current path is Path A only for the memory cell C22 on Row2, and the current path is Path B for the other memory cells C12, C32.
Even if the current magnetic field affects the storage elements 1 of C22 and C32, the influence is different between the memory cell C22 on Row2 and the other memory cells C12 and C32. That is, when the current path of the word line 20 is switched, the row address to which the selected memory cell 50 belongs is unique, so that if the row address is used as a control signal to the switch circuits SW1 and SW2, The asteroid characteristic of the memory cell 50 that shares (Column) addresses but is not selected is due to Path B, and as a result, the range of the allowable magnetization reversal current is expanded.

The same is true for the bit line 30. That is, when switching the current path of the bit line 30, the column (Co) to which the selected memory cell 50 belongs
lumn) Since the address is unique, the switch circuit
If a column address is used as a control signal to SW3 and SW4, the asteroid characteristic of the memory cell 50 that shares the row address but is not selected is due to Path B, and as a result, the allowable magnetization reversal This leads to an expansion of the current range.

As a result, in the MRAM of this embodiment,
Even if the memory cells 50 are arranged in a matrix, a switching operation such as selecting Path A for one storage element 1 and selecting Path B for the other storage element 1 becomes possible. The range of the magnetization reversal current allowed when writing information to the storage element 1 can be expanded.

Next, an MRAM according to a second embodiment of the present invention will be described. However, here, only the differences from the above-described first embodiment will be described. As shown in FIG. 6, in the MRAM described in the present embodiment, only the word line 20 is composed of the main line 21 and the bypass line 22, and only the line path select signal line 42 is provided correspondingly. Storage element 1
And the bit lines 3 are substantially the same as those in the related art.

Further, since only the word line 20 is composed of the main line 21 and the bypass line 22, as shown in FIG.
Only switch circuits SW1 and SW2 for enabling switching between the switch and the bypass line 22 are provided.

As shown in FIG. 8, such memory cells 51 are arranged in a matrix, and each line path select signal line 42 has a control signal (WL Path Select signal) to the switch circuits SW1 and SW2. ) Is supplied with a row address selection signal (BL Select). Thereby, the control signal (WL Path Select signal)
The switching circuits SW1 and SW2 are switched in accordance with the state (High / Low), so that the current path in the word line 20 is also selectively switched to one of the main line 21 and the bypass line 22.

That is, when switching the current path of the word line 20, the row (Ro
w) Since the address is unique, the switch circuit SW
1, if a row address is used as a control signal to SW2, only the selected memory cell 51 has the asteroid characteristic based on Path A, and the column address is shared but the unselected memory cell 51 is not selected. Asteroid properties are due to Path B.

Therefore, for example, PtMn / CoFe
/ Ru / CoFe / Al ₂ O ₃ / CoFe / Ta, a storage element 1 having a size of 0.13 μm × 0.26 μm and a main line 21 close to the storage element 1
If the bypass line 22 is formed at a distance of about 230 nm from the main line 21, a measurement example of an asteroid curve as shown in FIG. 9 is obtained. Thus, the range of the magnetization reversal current can be expanded. Thereby, only the current path of the word line 20 is connected to the main line 21 and the bypass line 2.
2, the range of the allowable magnetization reversal current can be expanded as compared with the conventional case.

Further, in this case, only the word line 20 has two systems of the main line 21 and the bypass line 22, and the bit line 3 has only one system.
Compared to the case of the first embodiment, the MRAM is suitable for miniaturization and high integration of the MRAM.

Next, an MRAM according to a third embodiment of the present invention will be described. Here, however, only the differences from the above-described first or second embodiment will be described. As shown in FIG. 10, in the MRAM described in the present embodiment, only the bit line 30 is made up of the main line 31 and the bypass line 32, and only the line path select signal line 41 is provided correspondingly. The storage element 1 and the word line 2 are substantially the same as in the related art.

Further, since only the bit line 30 is composed of the main line 31 and the bypass line 22, as shown in FIG.
Only switch circuits SW3 and SW4 for enabling switching between 1 and the bypass line 32 are provided.

As shown in FIG. 12, such memory cells 52 are arranged in a matrix, and switch circuits SW3 and SW4 are connected to each line path select signal line 41.
, A row address selection signal (WL Select) is supplied as a control signal (BL Path Select signal). Thereby, the control signal (BL Path Select signal)
The switching circuits SW3 and SW4 are switched according to the state (High / Low), so that the current path in the bit line 30 is selectively switched to either the main line 31 or the bypass line 32.

That is, when switching the current path of the bit line 30, the column (Colu) to which the selected memory cell 52 belongs
mn) Since the address is unique, the switch circuit SW
3. If a column address is used as a control signal to SW4, only the selected memory cell 52 has the asteroid characteristic of Path A, and the row address is shared but the memory cell 52 not selected is selected. Asteroid properties
Path B.

Therefore, for example, PtMn / CoFe
For a storage element 1 having a size of 0.13 μm × 0.26 μm with a film configuration of / Ru / CoFe / Al ₂ O ₃ / CoFe / Ta, a main line 31 close to the storage element 1 is provided.
If the bypass line 32 is formed at a distance of about 230 nm from the main line 31, a measurement example of an asteroid curve as shown in FIG. 13 is obtained. Thus, the range of the magnetization reversal current can be expanded. Thereby, even when only the current path of the word line 30 can be switched between the main line 31 and the bypass line 32, the allowable range of the magnetization reversal current can be expanded as compared with the conventional case.

Also in this case, as in the second embodiment, only the bit line 30 has two systems, the main line 31 and the bypass line 32, and the word line 2 has only one system. Compared to the case of the first embodiment, the MRAM is more suitable for miniaturization and higher integration of the MRAM.

In the above-described first to third embodiments, each of the switch circuits SW1 to SW4 is configured using a MOS transistor or the like, and these switch circuits SW1 to SW4 are used.
The case where W4 operates in response to control signals (BL Path Select signal and WL Path Select signal) obtained via the line path select signal lines 41 and 42 has been described as an example.
The present invention is not limited to this.

For example, instead of each of the switch circuits SW1 to SW4, each of the memory cells 50, 51, 52 is provided with a logical operation circuit as shown in FIG. 14, that is, any one of the main lines 21, 31 and the bypass lines 22, 32. It is also conceivable to provide a logical operation circuit for generating a negative logic control signal for selecting the above. In this case, the logical operation circuit supplies a column address selection signal (WL) for specifying a column of the word line 20.
Select) and a row address select signal (BL Select) for specifying the row of the bit line 30.
A switch selection signal of negative logic will be generated. Therefore, such a logical operation circuit is connected to each memory cell 50,
By providing them at 51 and 52, Path on the matrix
The memory cells 50, 51, and 52 to be A can be always limited to one.

Also, a column address selection signal (WL Selec
t) and control signals (BL Path Select signal, WL Path Se
lect signal) to each of the switch circuits SW1 to SW4 via the line path select signal lines 41 and 42, for example, an electronic circuit as shown in FIG.
An electronic circuit for generating a negative logic switch selection signal for selecting one of the bypass lines 22 and 32 and
It is also conceivable to provide each of the memory cells 50, 51, 52. In this case, the electronic circuit includes, for example, the word line 20.
And a control signal of negative logic is generated based on the peak value of each current pulse flowing through the bit line 30. Specifically, for example, the current flowing through the word line 20 or the bit line 30 is converted into a voltage by the current detection resistors Rs1 and Rs2, and the voltage is compared with the reference voltages Vref1 and Vref2, thereby selecting a logical-level column address. Signal (WL Select)
And generating a row address selection signal (BL Select). Therefore, in this case, the path A does not need the line path select signal lines 41 and 42, and
Can be limited.

However, as described in the first to third embodiments, the switch circuits SW1 to SW4 are provided in each of the memory cells 50, 51 and 52, and the line path select signals are supplied to these switch circuits SW1 to SW4. When control signals (BL Path Select signal and WL Path Select signal) are applied through the lines 41 and 42, each of the memory cells 50, 51 and 52
Can be minimized, and the address selection signal (WL Select, BL
Select) simultaneously with each of the memory cells 50, 51, 52
It is not necessary to give to
This is very suitable for realizing miniaturization and high integration of AM.

[0051]

As described above, the magnetic memory device of the present invention has a structure in which the current path of a write line such as a word line or a bit line can be switched between a main line and a bypass line. The following effects are mainly exhibited. With respect to the storage elements arranged in a matrix, it is possible to expand the range of the current magnetic field in which only the selected storage element can be stably magnetized without disturbing the magnetization state of the non-selected storage element. Even when the magnetic field Hc at which the magnetization reversal greatly varies due to variations in the magnetic material constant or element dimensions, the product can be used as a product without being defective. As a result, the mass production yield is improved, which can contribute to a reduction in the price of the magnetic memory device. Further, since the interaction between the adjacent storage elements can be reduced, the arrangement interval between the storage elements can be reduced without reducing the crosstalk margin. As a result, the storage capacity per area is improved, and the chip area and cost of the magnetic memory device can be reduced. Furthermore, since the peak value of the current that can stably reverse the magnetization of only the selected storage element can be increased without disturbing the magnetization state of the non-selected storage element, the magnetic switching characteristics of the storage element are improved. Thus, high-speed operation can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration example of a characteristic main part of a magnetic memory device according to a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration example of a memory cell according to the first embodiment;

FIG. 3 is a circuit diagram illustrating a configuration example of a switch circuit in a memory cell;

FIG. 4 is a block diagram illustrating an example of a matrix arrangement of memory cells according to the first embodiment;

FIG. 5 is an explanatory diagram showing a specific example of an asteroid curve and a range of a current allowed for magnetization reversal according to the first embodiment;

FIG. 6 is a schematic diagram illustrating a configuration example of a characteristic main part of a magnetic memory device according to a second embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration example of a memory cell according to a second embodiment;

FIG. 8 is a block diagram illustrating an example of a matrix arrangement of memory cells according to the second embodiment;

FIG. 9 is an explanatory diagram showing a specific example of an asteroid curve and a range of current allowed for magnetization reversal according to the second embodiment.

FIG. 10 is a schematic diagram showing a configuration example of a characteristic main part of a magnetic memory device according to a third embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration example of a memory cell according to a third embodiment;

FIG. 12 is a block diagram illustrating a matrix arrangement example of memory cells according to a third embodiment;

FIG. 13 is an explanatory diagram showing a specific example of an asteroid curve and a range of a current allowed for magnetization reversal according to the third embodiment.

FIG. 14 shows a route selection signal for a main line and a bypass line.
FIG. 9 is a circuit diagram showing a configuration example of a path selection signal generation circuit necessary when memory cells having the same Row or Column are not shared;

FIG. 15 is a circuit diagram illustrating a configuration example of an electronic circuit that generates a path selection signal from a word line or bit line current without independently routing a path selection signal for a main line and a bypass line.

FIG. 16 is an explanatory diagram showing a specific example of a resistance-current characteristic in a storage element of a magnetoresistive element having a size of 0.13 μm × 0.26 μm.

FIG. 17 is a schematic diagram showing a configuration example of a characteristic main part in a conventional magnetic memory device.

FIG. 18 is a block diagram showing a configuration example of a memory cell in a conventional example.

FIG. 19 is a block diagram showing an example of a matrix arrangement of memory cells in a conventional example.

FIG. 20 is an explanatory diagram showing a specific example of an asteroid curve and a range of current allowed for magnetization reversal in a conventional example.

21 is an explanatory diagram showing a specific example of a current range allowed after the first quadrant of the asteroid curve of FIG. 20 is enlarged to eliminate cell characteristic variations and inter-cell crosstalk margin.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Storage element, 20 ... Word line, 21 ... Main line, 22 ...
Bypass line, 30 ... bit line, 31 ... main line, 32 ...
Bypass lines, 41, 42 ... line path select signal lines, 50, 51, 52 ... memory cells, SW1, SW2, SW3, SW4
... Switch circuit

Claims (8)

[Claims] 1. A storage device comprising: a magnetoresistive effect type storage element arranged in a matrix; and write lines arranged for each row and each column of the storage element, and selectively provided by a current magnetic field generated by the write line. In the magnetic memory device for inverting the magnetization direction of each storage element, at least one of the write line for each row and the write line for each column is connected to a main line disposed close to the storage element, A magnetic memory device, comprising: a bypass line disposed farther from the storage element than a line, wherein a current path can be switched between the main line and the bypass line. 2. The magnetic memory device according to claim 1, wherein switching means for switching a current path between the main line and the bypass line is provided individually for each of the storage elements. 3. The magnetic memory device according to claim 2, further comprising a signal line for supplying a control signal for instructing the switching means to switch a current path. 4. The magnetic memory device according to claim 3, wherein a row address signal for specifying a row of a write line to which a current is applied is used as the control signal. 5. The magnetic memory device according to claim 3, wherein a column address signal for specifying a column of a write line to which a current is applied is used as the control signal. 6. A signal generating circuit for generating a control signal for instructing the switching means to switch a current path based on a peak value of a current pulse applied to the write line. 3. The magnetic memory device according to 2. 7. The magnetic memory device according to claim 1, wherein the storage element is a giant magnetoresistive element. 8. The magnetic memory device according to claim 1, wherein the storage element is a tunnel magnetoresistance effect element.