JP2002354485A - Digital signal compressing circuit and digital signal expanding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal compressing circuit and a digital signal expanding circuit with low power consumption. SOLUTION: The digital signal compressing circuit is constituted in such a manner that the circuit is provided with a subtractor 1 for taking a difference between an image signal and a prediction signal, a discrete cosine transformer 2 and quantizer 3 for compressing and quantizing the difference, an inverse quantizer 4 and an inverse discrete cosine transformer 5 for making the output from the quantizer 3 back to the original difference, an adder 6 for adding the difference to a prediction signal to form an accumulated frame signal, an accumulated frame memory 7 for storing the accumulated frame signal, a basic signal memory 19 for storing a basic frame signal, and a selector 20. The selector 20 selects an output from the memory 19 as a prediction signal when transmitting an I frame, and selects an output from the memory 7 as a prediction signal when transmitting frames other than the I frame.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal compression circuit and a digital signal decompression circuit.

[0002]

2. Description of the Related Art A digital signal compression circuit for a still image (for example, JPEG) will be described as an example. In a conventional digital signal compression circuit, as shown in FIG. A difference from the prediction signal is obtained, and the difference is subjected to a discrete cosine transform (Descrete cosine transform:
DCT) to obtain a DCT coefficient as a transformation result, and the DCT coefficient is further quantized (Qu
antization: Q) Further, the compressed signal output from the quantizer 3 is inversely quantized (Inverse quantization: IQ) by the inverse quantizer 4 and inverse discrete cosine transform (Inverse descratec c) by the inverse discrete cosine transformer 5.
sine transform: IDCT), and the resulting decoded difference signal is added to the prediction signal as an input signal to the subtractor 1 in the adder 6, and the result is temporarily stored in the accumulation frame memory 7. , Which is used as a prediction signal for obtaining a difference from the next input signal. Also,
The compressed signal output from the quantizer 3 is output to a variable-length encoder 8.
And output as a compressed image signal.
Here, the “frame” means one screen in the image signal.

FIG. 7 shows a digital signal decompression circuit which decompresses a compressed image signal to obtain a restored image signal. In the figure, a compressed image signal as an input signal is input to a variable-length decoder 9.
, And becomes a quantized signal.
It becomes a CT coefficient signal, becomes an input difference signal by an inverse discrete cosine transformer 11, is added by an adder 12 to a preceding frame signal output from an accumulation frame memory 13, and becomes a restored image signal. 13 is stored.

[0004] The component 1 of the discrete cosine converter 2
FIG. 8 shows a configuration example of the dimensional discrete cosine transformer. Here, an eight-point discrete cosine converter is shown. After fetching eight input data into the registers 14a to 14h, the register 14, the shifter 16, the read-only memory 17, The signal is input to an arithmetic circuit having an adder 18 and the like, and a DA method (Distributed Arithmetic method) for performing a product-sum operation in a bit unit is used.
Calculate CT coefficients. The calculated DCT coefficients are sequentially transferred and output by a shift register having registers 14i to 14p as constituent elements. The two-dimensional DCT can be executed by recording this output in the transposition RAM, exchanging the rows and columns, and performing the one-dimensional DCT again.

[0005] The configuration of the one-dimensional inverse discrete cosine transformer, which is a component of the inverse discrete cosine transformer 11, is the same as the configuration of the one-dimensional discrete cosine transformer illustrated in FIG. This is a one-dimensional IDCT operation. DC
Since the T operation and the IDCT operation have the same operation form (matrix product operation form), the IDCT operation can also be executed by the DA method as in the DCT operation.

[0006] Further, in the ordinary MPEG, there is a motion vector detection block, which is further compressed. In the following, for simplicity, the discussion will be made taking the JPEG architecture as an example.
It goes without saying that the G architecture is also effective.

[0007]

In recent years, there has been a growing demand for obtaining real-time video information such as live cameras and surveillance cameras via the Internet. It is expected that video information can be transmitted and received wirelessly by using a CMOS sensor and Bluetooth to eliminate the hassle of wired communication. At this time, the power consumption of the digital processing portion is large, and it is an important problem to reduce the power consumption.

In a live camera or a surveillance camera in particular, most of the operation time is a series of still images without motion, and the background of the image does not change at all even when there is motion. For this reason, in a live camera or a surveillance camera, the calculation of the DCT part is more important than the motion vector detection block.
It has become an important problem to reduce the power consumption of the semiconductor device. In the still image compression, the DCT block occupies 90% or more of the logic processing, and the reduction of the power consumption of the DCT means the reduction of the power consumption of all the logic circuits.

In MPEG, intra-frame signal compression is performed on an I frame, which is a basic data block, and an inter-frame difference is obtained in the next frame based on the I frame. Taking an inter-frame difference from one to the next generates a prediction error, which accumulates in the time direction.
For this I frame, the signal of the I frame is compressed and transmitted without taking the difference from the preceding frame. At this time, a large logical operation is required to compress the I-frame signal, and there is a problem that the power consumption increases accordingly. A similar problem also occurs in the signal decompression circuit on the receiving side.

When transmitting and receiving video information wirelessly, reducing the signal amount of the video information is an important problem from the viewpoint of power consumption of the RF portion.

An object of the present invention is to solve the above problems and to provide a digital signal compression circuit and a digital signal decompression circuit characterized by low power consumption.

[0012]

In order to solve the above problems, according to the present invention, an accumulative frame memory, a basic frame memory, an output from the accumulative frame memory and A digital signal compression circuit comprising means for selecting one of the outputs from the basic frame memory as a prediction signal according to a predetermined selection rule and calculating a difference between the input signal and the prediction signal.

According to the present invention, one of an accumulation frame memory, a basic frame memory, an output from the accumulation frame memory, and an output from the basic frame memory is used. A digital signal decompression circuit comprising means for selecting a preceding frame signal according to a predetermined selection rule and taking the sum of the input difference signal and the preceding frame signal is provided.

In the present invention, one of the accumulation frame memory and the basic frame memory is selected as a signal input target frame memory according to a predetermined selection rule, and 2. The digital signal compression circuit according to claim 1, further comprising a selection circuit for inputting a signal to the input target frame memory.

Further, in the present invention, one of the accumulation frame memory and the basic frame memory is selected as a signal input target frame memory according to a predetermined selection rule. 3. The digital signal decompression circuit according to claim 2, further comprising a selection circuit for inputting a signal to the input target frame memory.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The above-mentioned problem can be solved as follows. That is, in each of the transmission side system and the reception side system, there is a basic frame memory storing the same data common to both systems, and in the transmission side system, a basic data block (for example,
When transmitting an I frame signal), the same data is extracted as a prediction signal from the basic frame memory,
An input signal (the basic data block described above, for example,
There is a circuit for taking the difference between the I-frame signal) and the prediction signal, and further compressing and transmitting the difference signal. When the receiving system receives the basic data block, it expands the received signal. The input difference signal obtained by
The above-mentioned problem is solved by configuring a transmission / reception system characterized in that there is a circuit for using the same data extracted from the basic frame memory as a restored image signal.

Hereinafter, the present invention will be described in detail with reference to embodiments.

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram of a digital signal compression circuit according to an embodiment of the present invention. In the figure, a subtractor 1, a discrete cosine transformer 2, a quantizer 3, an inverse quantizer 4, an inverse discrete cosine transformer 5, an adder 6, an accumulation frame memory 7, and a variable length encoder 8
Are the same as those given the same reference numerals in the conventional digital signal compression circuit illustrated in FIG. 6, and their functions are the same as those in the conventional digital signal compression circuit.

The present embodiment is different from the conventional digital signal compression circuit illustrated in FIG. 6 in that a basic frame memory 19 and a selector 20 are provided. The basic frame memory 19 stores, for example, an image signal of a still screen in a normal state from a fixed surveillance camera as a basic frame signal. The selector 20 selects an output from the accumulation frame memory 7 as a prediction signal when transmitting a frame other than the I frame, and selects an output from the basic frame memory 19 as a prediction signal when transmitting an I frame. That is, in the present embodiment, when transmitting a frame other than the I frame,
Transmission is performed by the same method as the conventional method, but when transmitting the I frame, unlike the conventional method, the difference between the I frame signal and the basic frame signal selected as the prediction signal is obtained, and the difference is further compressed. Send. Since the logical operation and the data amount at this time are the same as when transmitting a frame other than the I frame, the conventional digital signal compression circuit requires an I frame transmission.
The large logical operation and the need to transmit an image signal with a large amount of data can be eliminated.

When transmitting a frame other than the I frame, the output from the accumulation frame memory 7 is selected as a prediction signal.
The rule of "selecting the output from the basic frame memory 19 as a prediction signal" corresponds to the "predetermined selection rule" according to claim 1, and the selector 20 and the subtractor 1 correspond to the rule.
"Means for selecting one of the output from the accumulation frame memory and the output from the basic frame memory as a prediction signal according to a predetermined selection rule and taking a difference between an input signal and the prediction signal" are doing.

Normally, there is about one I frame per 15 frames. A total of 15 I frames including one I frame and 14 subsequent frames are called 1 GOP. Assuming that one frame of the original image is 20 Mbit, the I frame can be reduced to about 1 Mbit by intra-frame compression. For frames other than I-frames, 10Kbi is used for live cameras and surveillance cameras due to inter-frame compression.
Can be compressed to t. Therefore, in a conventional digital signal compression circuit, 1 Mbit + 14 × 10 Kb per GOP.
it = 1.14 Mbit data amount. On the other hand, in the digital signal compression circuit according to the present invention, since the I-frame is compressed by the difference from the basic frame, the difference can be reduced to about 10 Kbits like other frames. In one GOP, 15 × 10 Kbit =
The data amount is 0.15 Mbit. Therefore, one GOP can be compressed to a data amount of 13% as compared with the conventional method.

As is apparent from the above description, the implementation of the present invention reduces the data amount to about 1/10 of that of the conventional system as shown in FIG.
One GOP can be compressed. It is clear that reducing the data amount to about 1/10 when one GOP is compressed leads to a significant reduction in power consumption.

The compressed image signal from the digital signal compression circuit according to the present invention described above is described below.
Expanded by the digital signal expansion circuit according to the present invention,
It becomes a restored image signal.

(Second Embodiment) FIG. 2 is a block diagram of a digital signal decompression circuit according to a second embodiment of the present invention. In the figure, a variable length decoder 9, an inverse quantizer 10, an inverse discrete cosine transformer 11, an adder 12, and an accumulation frame memory 13 are given the same reference numerals in the conventional digital signal decompression circuit illustrated in FIG. The function is the same as that of the conventional digital signal decompression circuit.

The present embodiment is different from the conventional digital signal decompression circuit illustrated in FIG. 7 in that a basic frame memory 21 and a selector 22 are provided. In the basic frame memory 21, the same basic frame signal as the basic frame signal stored in the basic frame memory (illustrated as 19 in FIG. 1) in the digital signal compression circuit (illustrated in FIG. 1) according to the present invention is used as the basic frame signal. It is remembered. The selector 22 selects an output from the accumulation frame memory 13 as a preceding frame signal when receiving a frame other than an I frame, and selects an output from the basic frame memory 21 as a preceding frame signal when receiving an I frame. . The preceding frame signal selected in this way is added to the input difference signal output from the inverse discrete cosine transformer 11 by the adder 12 and output as a restored image signal. Thus, when receiving a frame other than the I frame, the frame signal is restored by the same method as the conventional method, and when the I frame is received, the difference between the transmitted I frame signal and the basic frame signal is calculated. The basic frame signal output from the basic frame memory 21 is added to restore the I frame signal.

When a frame other than the I frame is received, the output from the accumulation frame memory 13 is selected as the preceding frame signal. When the I frame is received, the output from the basic frame memory 21 is used as the preceding frame signal. The rule of selecting “select as a signal” corresponds to the “predetermined selection rule” of claim 2, and the selector 22 and the adder 12 determine the output from the accumulation frame memory and the adder 12 according to claim 2. Means for selecting one of the outputs from the basic frame memory as the preceding frame signal in accordance with a predetermined selection rule and taking the sum of the input difference signal and the preceding frame signal. "

Since the compressed image signal input to the digital signal decompression circuit is an output signal from the digital signal compression circuit according to the present invention, the data amount does not increase even when the I frame is received. However, there is no increase in the power for signal processing or the power for signal processing, and the adoption of the digital signal decompression circuit according to the present invention achieves a reduction in power consumption.

(Third Embodiment) FIG. 4 is a block diagram of a digital signal compression circuit according to a third embodiment of the present invention. In the figure, a subtractor 1, a discrete cosine transformer 2, a quantizer 3, an inverse quantizer 4, an inverse discrete cosine transformer 5, an adder 6, a cumulative frame memory 7, a variable length encoder 8, a basic frame memory 19 and the selector 20 are shown in FIG.
Are the same as those given the same reference numerals in the first embodiment, and their functions are also the same as those in the first embodiment.

The present embodiment differs from the first embodiment shown in FIG. 1 in that a selector 23 is provided. The selector 23 operates only when the storage contents (basic frame signal) of the basic frame memory 19 are rewritten.
Selects the basic frame memory 19, inputs the output of the adder 6 to the basic frame memory 19, otherwise,
The accumulation frame memory 7 is selected, and the output of the adder 6 is input to the accumulation frame memory 7. Such a selector 23
By the operation described above, the stored contents (basic frame signal) of the basic frame memory 19 can be rewritten. Except for such rewriting, in the present embodiment, the first
The same digital signal compression as in the embodiment is performed. Note that the above-mentioned “selector 23 is a basic frame memory 1
The rule for selecting the basic frame memory 19 only when rewriting the stored contents (basic frame signal) of "9, and selecting the cumulative frame memory 7 in other cases" is described in claim 3. Falls under "predetermined selection rules"
The selector 23 corresponds to the selection circuit according to the third aspect.

(Fourth Embodiment) FIG. 5 is a block diagram of a digital signal decompression circuit according to a fourth embodiment of the present invention. In the figure, a variable length decoder 9 and an inverse quantizer 1
0, the inverse discrete cosine transformer 11, the adder 12, the accumulation frame memory 13, the basic frame memory 21, and the selector 22 are the same as those given the same reference numerals in the second embodiment shown in FIG. The functions are the same as those in the second embodiment.

The present embodiment differs from the second embodiment shown in FIG. 2 in that a selector 24 is provided. The selector 24 operates only when rewriting the storage contents (basic frame signal) of the basic frame memory 21.
The basic frame memory 21 is selected, and the output of the adder 12 is input to the basic frame memory 21. Otherwise, the cumulative frame memory 13 is selected, and the output of the adder 12 is input to the cumulative frame memory 13. . By such an operation of the selector 24, the stored contents (basic frame signal) of the basic frame memory 21 can be rewritten.
Except for such rewriting, in the present embodiment, the same digital signal decompression as in the second embodiment is performed. The above-mentioned “selector 24 selects the basic frame memory 21 only when rewriting the storage contents (basic frame signal) of the basic frame memory 21”
The selection rule of “otherwise select the accumulation frame memory 13” corresponds to the “predetermined selection rule” of claim 4, and the selector 24 corresponds to the selection circuit of claim 4. .

[0032]

According to the present invention, a digital signal compression circuit and a digital signal decompression circuit characterized by low power consumption can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital signal compression circuit according to the present invention.

FIG. 2 is a block diagram of a digital signal decompression circuit according to the present invention.

FIG. 3 is a diagram showing the effect of the present invention.

FIG. 4 is a block diagram of a digital signal compression circuit capable of rewriting a basic frame memory according to the present invention.

FIG. 5 is a block diagram of a digital signal decompression circuit capable of rewriting a basic frame memory according to the present invention.

FIG. 6 is a block diagram of a conventional digital signal compression circuit.

FIG. 7 is a block diagram of a conventional digital signal decompression circuit.

FIG. 8 is a diagram illustrating a configuration of a one-dimensional discrete cosine transformer.

[Explanation of symbols]

1: subtractor, 2: discrete cosine transformer, 3: quantizer,
4 ... Inverse Quantizer, 5 ... Inverse Discrete Cosine Transformer, 6 ... Adder, 7 ... Cumulative Frame Memory, 8 ... Variable Length Encoder, 9
... variable length decoder, 10 ... inverse quantizer, 11 ... inverse discrete cosine transformer, 12 ... adder, 13 ... cumulative frame memory, 14, 14a-14p ... register, 15 ... bit slice distributor, 16 ... Shifter, 17: read-only memory, 18: adder, 19: basic frame memory, 20
... selector, 21 ... basic frame memory, 22, 23,
24 ... selector.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK49 MA00 MA01 MA23 MC11 MC38 ME02 PP05 PP26 SS08 SS14 TA21 TB04 TC24 UA02 UA05 UA33 UA38 5J064 AA04 BA09 BA16 BB01 BB03 BC01 BC08 BC16 BC25 BD02

Claims (4)

[Claims] 1. An accumulative frame memory, a basic frame memory, and one of an output from the accumulative frame memory and an output from the basic frame memory are selected as a prediction signal according to a predetermined selection rule. Means for calculating a difference from a prediction signal. 2. An accumulative frame memory, a basic frame memory, and one of an output from the accumulative frame memory and an output from the basic frame memory are selected as a preceding frame signal in accordance with a predetermined selection rule. And a means for calculating a sum of the preceding frame signal and the preceding frame signal. 3. A selection circuit for selecting one of the accumulation frame memory and the basic frame memory as a signal input target frame memory according to a predetermined selection rule and inputting a signal to the signal input target frame memory. The digital signal compression circuit according to claim 1, wherein: 4. A selection circuit for selecting one of the accumulation frame memory and the basic frame memory as a signal input target frame memory according to a predetermined selection rule and inputting a signal to the signal input target frame memory. The digital signal decompression circuit according to claim 2, wherein