JP2002353397A - Semiconductor integrated circuit and mounting structure of electronic parts - Google Patents

Semiconductor integrated circuit and mounting structure of electronic parts

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Publication number
JP2002353397A
JP2002353397A JP2001159400A JP2001159400A JP2002353397A JP 2002353397 A JP2002353397 A JP 2002353397A JP 2001159400 A JP2001159400 A JP 2001159400A JP 2001159400 A JP2001159400 A JP 2001159400A JP 2002353397 A JP2002353397 A JP 2002353397A
Authority
JP
Japan
Prior art keywords
circuit
semiconductor integrated
integrated circuit
molded body
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001159400A
Other languages
Japanese (ja)
Inventor
Tomoyuki Yoshino
朋之 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2001159400A priority Critical patent/JP2002353397A/en
Publication of JP2002353397A publication Critical patent/JP2002353397A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To achieve high density mounting for realizing miniaturization of portable equipment. SOLUTION: A semiconductor integrated circuit and chip parts are directly mounted on the surface of a circuit molding forming an electric circuit pattern on the surface of a resin molding. In addition, a step is formed on the circuit molding of a part mounting the adjacent semiconductor integrated circuit and the chip parts, and short-circuiting is hardly generated even when it is mounted by narrow adjacency between the steps. Thus, the semiconductor integrated circuit and the chip parts can be highly densely mounted. The useless space in the inside of the portable equipment can be eliminated by designing the structure to contrive miniaturization.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路及
び電子部品の高密度・省スペース実装技術に関する。
The present invention relates to a high-density and space-saving mounting technique for semiconductor integrated circuits and electronic components.

【0002】[0002]

【従来の技術】近年、電子部品や半導体集積回路の小型
化、更には高密度実装技術の発展が著しい。特に携帯機
器の小型化が注目されている。
2. Description of the Related Art In recent years, the miniaturization of electronic components and semiconductor integrated circuits and the development of high-density mounting technology have been remarkable. In particular, the miniaturization of portable devices has attracted attention.

【0003】これまで電子部品や半導体集積回路の実装
方法の一つとして、基板表面に電子部品や半導体集積回
路を二次元的に実装していくSMT(Surface Mount Tec
hnology)が主流になっていた。しかし、携帯電話を代
表とする携帯端末の小型化が進み、その実装面積も縮小
する必要が生じた。
[0003] As one of the mounting methods of electronic components and semiconductor integrated circuits, an SMT (Surface Mount Tec) in which electronic components and semiconductor integrated circuits are two-dimensionally mounted on a substrate surface.
hnology) became mainstream. However, the miniaturization of mobile terminals represented by mobile phones has progressed, and it has become necessary to reduce the mounting area.

【0004】そこで最近では実装密度を向上させるため
に半導体集積回路間やチップ部品間の隙間を小さくする
方法や、半導体デバイスをパッケージ内で積層したスタ
ックトICなどが開発されている。二次元的に狭くなっ
た分を三次元的に広げようとする発想である。
Therefore, recently, a method of reducing a gap between semiconductor integrated circuits and chip components, and a stacked IC in which semiconductor devices are stacked in a package have been developed in order to improve a packaging density. The idea is to expand the two-dimensional narrowing in three dimensions.

【0005】図6には従来のビルドアップ基板を模式的
に示した断面図である。
FIG. 6 is a cross-sectional view schematically showing a conventional build-up substrate.

【0006】ビルドアップ基板は大別してベース層21
とビルドアップ層22の二層からなる。
The build-up substrate is roughly divided into a base layer 21
And the build-up layer 22.

【0007】表面のビルドアップ層に半導体集積回路4
やチップ部品3などを表面実装する。ベース層はガラス
エポキシ積層の硬質配線板であるため折り曲げたり、複
雑な形状に加工したりできない。
[0007] The semiconductor integrated circuit 4 is formed on the build-up layer on the surface.
And chip components 3 are surface-mounted. Since the base layer is a hard wiring board of a glass epoxy laminate, it cannot be bent or processed into a complicated shape.

【0008】図7には従来の携帯電話の断面図を模式的
に示した。
FIG. 7 schematically shows a sectional view of a conventional portable telephone.

【0009】携帯電話本体のほぼ中心に半導体集積回路
4やチップ部品3を実装したビルドアップ基板29が配
置される。硬質なビルドアップ基板であるから携帯電話
の外装ケースも直線的になってしまう。ビルドアップ基
板を挟んで上側にLCDモジュール26、タッチキー2
5、スピーカ27、マイク31が、下側に電池ユニット
28等が配置する。
A build-up board 29 on which the semiconductor integrated circuit 4 and the chip component 3 are mounted is disposed substantially at the center of the main body of the portable telephone. Since it is a rigid build-up board, the outer case of the mobile phone also becomes linear. LCD module 26, touch key 2 on top of build-up board
5. The speaker 27, the microphone 31, and the battery unit 28 are disposed below.

【0010】この様に携帯電話の外装ケース内を最も占
有する硬質のビルドアップ基板29が存在するため、ケ
ース内には無駄なスペースが存在し、携帯電話の小型化
を阻害していた。
Since the hard build-up board 29 occupies the most inside the outer case of the mobile phone, wasteful space exists in the case, which hinders the miniaturization of the mobile phone.

【0011】これは携帯電話に限らず一般的な携帯機器
においても同様である。
This applies not only to mobile phones but also to general mobile devices.

【0012】[0012]

【発明が解決しようとする課題】従来の表面実装では更
なる小型化や高機能化が求められる携帯機器にとって、
半導体集積回路や電子部品を実装する面積が基板の両面
だけでは限界になってきている。
SUMMARY OF THE INVENTION Conventional portable devices that require further miniaturization and higher functionality in surface mounting are required.
The area for mounting semiconductor integrated circuits and electronic components is becoming limited by only the two sides of the substrate.

【0013】小さな外装ケース内に電子部品や半導体集
積回路を実装した回路基板を配置するのも困難になって
きており、外装ケースを小型化する際の妨げになってい
る。更に、携帯端末は単純な直方体ではなく、デザイン
性やハンドリング性から複雑な形状をしている。複雑な
外装ケース内に硬質材からなる回路基板をコンパクトに
収納するのは非常に困難である。
It is becoming difficult to dispose a circuit board on which electronic components and semiconductor integrated circuits are mounted in a small outer case, which hinders downsizing of the outer case. Further, the mobile terminal is not a simple rectangular parallelepiped, but has a complicated shape in terms of design and handling. It is very difficult to compactly store a circuit board made of a hard material in a complicated outer case.

【0014】また、電子部品接続端子のファインピッチ
化、微小化により接合部分の信頼性が問題視されてきて
いる。
In addition, due to the fine pitch and miniaturization of the electronic component connection terminals, the reliability of the joint has been regarded as a problem.

【0015】そこで、本発明では省スペースに有効的に
電子部品を収納する実装技術と確実な電子部品の接合を
提供する。
Accordingly, the present invention provides a mounting technique for effectively storing electronic components in a space-saving manner and reliable bonding of electronic components.

【0016】[0016]

【課題を解決するための手段】本発明による第一の手段
では、電気回路パターンを樹脂成形体の表面に形成した
回路成形体の表面に半導体集積回路、チップ部品や半導
体ベアチップ等を実装した。
According to the first means of the present invention, a semiconductor integrated circuit, a chip component, a semiconductor bare chip, and the like are mounted on a surface of a circuit molded body in which an electric circuit pattern is formed on a surface of a resin molded body.

【0017】この回路成形体は携帯機器の外装ケースと
しても機能している。この方法を採用する事で複雑な形
状をしている外装ケースに対しても従来の回路基板配置
を気にせず、収納性を高める事が出来る。
This molded circuit also functions as an outer case of a portable device. By adopting this method, it is possible to improve the storage ability of an external case having a complicated shape without concern for the conventional circuit board arrangement.

【0018】更に第二の手段として、回路成形体を立体
的に段差を一段または複数段つけ、各段毎に電気回路パ
ターンを形成する。そして、各段にチップコンデンサや
チップ抵抗などのチップ部品あるいは半導体集積回路を
接合することで立体的な電子部品配置を構成する。この
ような立体配置を取ることで部品間の短絡を防止でき、
平面的に見た場合に隣り合う部品間の距離を縮めること
が出来る。
Further, as a second means, the circuit molded body is three-dimensionally provided with one or more steps, and an electric circuit pattern is formed for each step. Then, a chip component such as a chip capacitor or a chip resistor or a semiconductor integrated circuit is joined to each stage to form a three-dimensional electronic component arrangement. By taking such a three-dimensional arrangement, short circuits between parts can be prevented,
When viewed in a plan view, the distance between adjacent parts can be reduced.

【0019】この方法によっても、複雑な形状をしてい
る外装ケースに対して高密度な実装形態を得ることが出
来る。
According to this method as well, a high-density mounting form can be obtained for an outer case having a complicated shape.

【0020】また、第三の手段では、回路成形体の表面
で電気回路パターンを有する部分に凹凸部を形成し、そ
の凹部に半導体集積回路の電極端子を接続した。
In the third means, an uneven portion is formed in a portion having an electric circuit pattern on the surface of the circuit molded body, and an electrode terminal of the semiconductor integrated circuit is connected to the concave portion.

【0021】この方法により電子部品と電気回路パター
ンを接合する導電性接合剤の流れが防止され、電子部品
接続端子のファインピッチ化、微小化によって導電性接
合剤が少なくなっても、発生する接続不良(接続剥が
れ)が無くなる
According to this method, the flow of the conductive bonding agent for bonding the electronic component and the electric circuit pattern is prevented, and even if the conductive bonding agent is reduced due to the fine pitch and miniaturization of the connection terminals of the electronic component, the connection generated is reduced. Eliminates defects (separation)

【0022】[0022]

【発明の実施の形態】以下、図1〜図5を参照して本発
明に係わる実施の形態を詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to FIGS.

【0023】図1は本発明による回路成形体1へ半導体
集積回路4やチップ部品3を表面実装したところを示し
た斜視図である。回路成形体1は成形用樹脂とその表面
に形成された電気回路パターン2からなる。回路成形体
1自体の製法は一般的に既知であり、成形樹脂の表面に
メッキ処理を行った後にフォトリソグラフィー法やレー
ザなどでパターンを描く。そして、その描かれたパター
ンの特定部分に導電性接合剤となるハンダや導電性接着
剤を塗布し、半導体集積回路4やチッブ部品3を直接搭
載し、接合する。これまでは、半導体集積回路やチップ
部品などの電子部品は回路基板に接合し、回路基板のパ
ターンと回路成形体のパターンを接触させて電気的導通
を取る方法は行われていた。
FIG. 1 is a perspective view showing a state where a semiconductor integrated circuit 4 and a chip component 3 are surface-mounted on a circuit molded body 1 according to the present invention. The circuit molded body 1 includes a molding resin and an electric circuit pattern 2 formed on the surface thereof. The manufacturing method of the circuit molded body 1 itself is generally known, and a pattern is drawn by a photolithography method, a laser, or the like after plating the surface of the molding resin. Then, a solder or a conductive adhesive as a conductive bonding agent is applied to a specific portion of the drawn pattern, and the semiconductor integrated circuit 4 and the chip component 3 are directly mounted and bonded. Heretofore, a method has been used in which electronic components such as semiconductor integrated circuits and chip components are bonded to a circuit board, and a pattern of the circuit board and a pattern of a circuit molded body are brought into contact to establish electrical continuity.

【0024】回路成形体の斜めに切り取られた部分にも
半導体集積回路4やチップ部品3を接合できるので製品
内部の空間を有効に使用でき、製品の小型化ができる。
Since the semiconductor integrated circuit 4 and the chip component 3 can be joined to the obliquely cut portion of the circuit molded body, the space inside the product can be effectively used, and the product can be downsized.

【0025】図2は本発明による半導体集積回路5を回
路成形体1に接合する直前の状態を示した側面図であ
る。回路成形体1の表面には電気回路パターン8が形成
され、その上には半導体集積回路のハンダボール6と電
気回路パターン8を接合するための導電性接合剤9が供
給されている。
FIG. 2 is a side view showing a state immediately before the semiconductor integrated circuit 5 according to the present invention is joined to the circuit molded body 1. An electric circuit pattern 8 is formed on the surface of the circuit molded body 1, and a conductive bonding agent 9 for joining the solder ball 6 of the semiconductor integrated circuit and the electric circuit pattern 8 is supplied thereon.

【0026】ここで、導電性接合剤9はハンダや導電接
着剤を示す。
Here, the conductive bonding agent 9 indicates a solder or a conductive adhesive.

【0027】本発明では回路成形体に突起部7を形成し
た。この突起部7を形成することにより、半導体集積回
路5と回路成形体を接合する際の圧力及び熱による導電
性接合剤9の流動がおさえられる。従って、隣接パター
ンとのショートが防止できる。
In the present invention, the projection 7 is formed on the circuit molded body. By forming the protrusions 7, the flow of the conductive bonding agent 9 due to pressure and heat when bonding the semiconductor integrated circuit 5 and the circuit molded body is suppressed. Therefore, a short circuit with an adjacent pattern can be prevented.

【0028】また、半導体集積回路5のハンダボール6
が突起部7を形成することで出来た凹部に配置されるた
め位置決めも安定する。
The solder balls 6 of the semiconductor integrated circuit 5
Are arranged in the concave portions formed by forming the projections 7, so that the positioning is stable.

【0029】図3は本発明による回路成形体1に段差部
を設けた構造を模式的に示した断面図であり、図4は図
3を上面から見た平面図である。
FIG. 3 is a cross-sectional view schematically showing a structure in which a step is provided in the circuit molded body 1 according to the present invention, and FIG. 4 is a plan view of FIG. 3 as viewed from above.

【0030】回路成形体1に第一段の面11の電気回路
パターン2、第二段の面12の電気回路パターン15、
第三段の面13の電気回路パターン16を形成する。
The electric circuit pattern 2 on the first surface 11, the electric circuit pattern 15 on the second surface 12,
The electric circuit pattern 16 on the third surface 13 is formed.

【0031】各の段にチップ部品3や半導体集積回路4
を接合する際に、隣接間に段差があるため、隣接パター
ンや隣接部品間の電気的ショートが発生しにくくなるの
で、隣接部品間距離14を0.01mm程度まで縮める
ことができる。このような構造を取ることで図4のY方
向の距離を小さくでき、高密度実装が可能になる。
In each stage, a chip component 3 and a semiconductor integrated circuit 4
In joining, since there is a step between adjacent parts, an electrical short between adjacent patterns and adjacent parts is less likely to occur, so that the distance 14 between adjacent parts can be reduced to about 0.01 mm. By adopting such a structure, the distance in the Y direction in FIG. 4 can be reduced, and high-density mounting becomes possible.

【0032】図5は本発明による高密度実装を腕時計形
携帯機器に応用した例を示した断面図である。この例で
は、回路成形体1に段差部を三段設け、各段にチップ部
品3や半導体集積回路4を実装している。また、回路成
形体1内に電池34やLCDパネル33を構成する。バン
ド部32を腕につけることで、携帯用の機器になる。
FIG. 5 is a sectional view showing an example in which the high-density mounting according to the present invention is applied to a wristwatch-type portable device. In this example, three steps are provided in the circuit molded body 1, and the chip component 3 and the semiconductor integrated circuit 4 are mounted on each step. Further, the battery 34 and the LCD panel 33 are configured in the circuit molded body 1. By attaching the band portion 32 to the arm, the device becomes a portable device.

【0033】[0033]

【発明の効果】請求項1に記載したように、回路成形体
の表面に半導体集積回路、電子部品、半導体ベアチップ
を実装する事で、携帯機器などの限られた空間内に最適
配置する事が出来る。
According to the present invention, by mounting a semiconductor integrated circuit, an electronic component, and a semiconductor bare chip on the surface of a circuit molded body, the semiconductor device can be optimally arranged in a limited space such as a portable device. I can do it.

【0034】請求項2乃至請求項3に記載したように、
回路成形体の表面に凹凸をつけ、その凹部に半導体集積
回路のハンダボールや外部接続端子を落とし込むことで
半導体集積回路搭載時の位置ズレが防止でき安定した接
合が行える。
As described in claims 2 and 3,
By providing irregularities on the surface of the circuit molded body and dropping the solder balls and external connection terminals of the semiconductor integrated circuit into the concaves, positional displacement when the semiconductor integrated circuit is mounted can be prevented, and stable bonding can be performed.

【0035】また、ハンダボールや端子と電気回路パタ
ーンを接合する導電性接合剤が隣接パターンへ流れにく
くなるので電気的ショート不良も起きにくくなる。
In addition, since the conductive bonding agent for bonding the solder balls and the terminals to the electric circuit pattern does not easily flow to the adjacent pattern, an electric short-circuit failure is unlikely to occur.

【0036】請求項4乃至請求項5に記載したように、
回路成形体に段差を設け、各段差上にある電気回路パタ
ーン上にチップ部品や半導体集積回路を接合する際に、
段が違い、隣り合う部品同士が各段差間で電気的なショ
ートを起こさなくなる。従って、上面方向から見たとき
に隣接部品間の距離を縮められるので高密度実装が実現
し、ケース内の無駄なスペースが無くなり、携帯機器の
更なる小型化が出来る。
As described in claims 4 and 5,
When providing steps on the circuit molded body and joining chip components or semiconductor integrated circuits on the electric circuit pattern on each step,
The steps are different, and adjacent parts do not cause an electrical short between the steps. Therefore, when viewed from the top, the distance between adjacent components can be reduced, so that high-density mounting is realized, and unnecessary space in the case is eliminated, and the size of the portable device can be further reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による第一の半導体集積回路及び電子部
品の実装構造実施例を示す説明用斜視図である。
FIG. 1 is an explanatory perspective view showing an embodiment of a mounting structure of a first semiconductor integrated circuit and an electronic component according to the present invention.

【図2】本発明による半導体集積回路の実装構造実施例
を示す断面説明図である。
FIG. 2 is an explanatory sectional view showing an embodiment of a mounting structure of a semiconductor integrated circuit according to the present invention.

【図3】本発明による第二の半導体集積回路及び電子部
品の実装構造実施例を示す断面説明図である。
FIG. 3 is an explanatory sectional view showing an embodiment of a mounting structure of a second semiconductor integrated circuit and an electronic component according to the present invention.

【図4】本発明による第二の半導体集積回路及び電子部
品の実装構造実施例を示す上面説明図である。
FIG. 4 is an explanatory top view showing an embodiment of a mounting structure of a second semiconductor integrated circuit and an electronic component according to the present invention.

【図5】本発明による実装構造を腕時計型携帯機器に応
用した実施例を示す断面説明図である。
FIG. 5 is an explanatory sectional view showing an embodiment in which the mounting structure according to the present invention is applied to a wristwatch-type portable device.

【図6】従来の半導体集積回路及び電子部品の実装構造
実施例を示す断面説明図である。
FIG. 6 is an explanatory sectional view showing an example of a conventional mounting structure of a semiconductor integrated circuit and an electronic component.

【図7】従来の実装方法で製作した携帯電話の断面図を
模式的に表した説明図である。
FIG. 7 is an explanatory view schematically showing a cross-sectional view of a mobile phone manufactured by a conventional mounting method.

【符号の説明】[Explanation of symbols]

1 回路成形体 2 電気回路パターン 3 チップ部品 4 半導体集積回路 5 半導体集積回路(BGA、CSP) 6 ハンダボール 7 突起部 8 電気回路パターン 9 接合剤 11 第一段の面 12 第二段の面 13 第三段の面 14 隣接部品間距離 15 第二段の面の電気回路パターン 16 第三段の面の電気回路パターン 21 ベース層 22 ビルドアップ層 23 スルーホール 24 層間配線パターン 25 タッチキー 26 LCDモジュール 27 スピーカ 28 電池ユニット 29 ビルドアップ基板 30 アンテナ 31 マイク 32 バンド部 DESCRIPTION OF SYMBOLS 1 Circuit molded object 2 Electric circuit pattern 3 Chip component 4 Semiconductor integrated circuit 5 Semiconductor integrated circuit (BGA, CSP) 6 Solder ball 7 Projection part 8 Electric circuit pattern 9 Bonding agent 11 First stage surface 12 Second stage surface 13 Third-stage surface 14 Distance between adjacent components 15 Second-stage surface electric circuit pattern 16 Third-stage surface electric circuit pattern 21 Base layer 22 Build-up layer 23 Through hole 24 Interlayer wiring pattern 25 Touch key 26 LCD module 27 Speaker 28 Battery Unit 29 Build-up Board 30 Antenna 31 Microphone 32 Band

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 電気回路パターンを樹脂成形体の表面に
形成した回路成形体において、回路成形体の表面に半導
体集積回路、チップ部品や半導体ベアチップ等を実装し
た構造を特徴とする半導体集積回路及び電子部品の実装
構造。
1. A circuit molded product having an electric circuit pattern formed on a surface of a resin molded product, wherein a semiconductor integrated circuit, a chip component, a semiconductor bare chip, and the like are mounted on the surface of the circuit molded product. Electronic component mounting structure.
【請求項2】 電気回路パターンを樹脂成形体の表面に
形成した回路成形体において、回路成形体の表面で電気
回路パターンを有する部分に凹凸部を形成し、その凹部
に半導体集積回路の電極端子を接続した構造を特徴とす
る半導体集積回路及び電子部品の実装構造。
2. In a circuit molded body having an electric circuit pattern formed on a surface of a resin molded body, an uneven portion is formed in a portion having an electric circuit pattern on a surface of the circuit molded body, and an electrode terminal of a semiconductor integrated circuit is formed in the concave portion. A semiconductor integrated circuit and an electronic component mounting structure characterized by a structure in which are connected.
【請求項3】 電気回路パターンを樹脂成形体の表面に
形成した回路成形体において、回路成形体の表面で電気
回路パターンを有する部分に凹凸部を形成し、その凹部
に導電性接合剤を保持し、導電性接合剤を介して半導体
集積回路の電極端子と電気回路パターンを接続した構造
を特徴とする半導体集積回路及び電子部品の実装構造。
3. In a circuit molded body having an electric circuit pattern formed on a surface of a resin molded body, an uneven portion is formed in a portion having an electric circuit pattern on a surface of the circuit molded body, and a conductive bonding agent is held in the concave portion. A semiconductor integrated circuit and an electronic component mounting structure, wherein an electrode terminal of the semiconductor integrated circuit and an electric circuit pattern are connected via a conductive bonding agent.
【請求項4】 電気回路パターンを樹脂成形体の表面に
形成した回路成形体において、回路成形体を断面方向か
ら見た時に、回路成形体の表面で隣り合う電気回路パタ
ーンの配置に高低差をつける段差部を一段または複数段
形成した構造を特徴とする半導体集積回路及び電子部品
の実装構造。
4. In a circuit molded body in which an electric circuit pattern is formed on a surface of a resin molded body, when the circuit molded body is viewed from a cross-sectional direction, there is a difference in height between arrangements of adjacent electric circuit patterns on the surface of the circuit molded body. A mounting structure for a semiconductor integrated circuit and an electronic component, wherein a mounting step is formed in one or more steps.
【請求項5】 請求項4記載の回路成形体の一段または
複数段の段差部にチップ部品や半導体集積回路を配置し
た構造を特徴とする半導体集積回路及び電子部品の実装
構造。
5. A mounting structure of a semiconductor integrated circuit and an electronic component, wherein a chip component or a semiconductor integrated circuit is arranged on one or more steps of the circuit molded body according to claim 4.
JP2001159400A 2001-05-28 2001-05-28 Semiconductor integrated circuit and mounting structure of electronic parts Pending JP2002353397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001159400A JP2002353397A (en) 2001-05-28 2001-05-28 Semiconductor integrated circuit and mounting structure of electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001159400A JP2002353397A (en) 2001-05-28 2001-05-28 Semiconductor integrated circuit and mounting structure of electronic parts

Publications (1)

Publication Number Publication Date
JP2002353397A true JP2002353397A (en) 2002-12-06

Family

ID=19002988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001159400A Pending JP2002353397A (en) 2001-05-28 2001-05-28 Semiconductor integrated circuit and mounting structure of electronic parts

Country Status (1)

Country Link
JP (1) JP2002353397A (en)

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