JP2002353163A - Compound semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device which has electrodes that possess superior ohmic characteristics and proper Schottky characteristics on the compound semiconductor. SOLUTION: This compound semiconductor device has electrodes 20 of a five-layer structure stacked on a compound semiconductor substrate 10. Between a first refractory metal layer and a third refractory metal layer, a second refractory metal layer, that can prevent a component constituting the third refractory metal layer from diffusing into the compound semiconductor, is interposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method of manufacturing the same, and more particularly, to a compound semiconductor device having a good ohmic electrode and a Schottky electrode, and to form the compound semiconductor device easily and with high precision. And a method of manufacturing a compound semiconductor device.

[0002]

2. Description of the Related Art Conventionally, Au / Pt / Ti / Pt is used.
Layer structure (Au film, Pt film, Ti film and Pt film are Au
A structure in which a film is stacked at the top and a Pt film at the bottom is similarly shown even if the type of each film is different) is a P-type ohmic electrode having a carrier concentration of 5 × 19 cm ^{− 3} and a thin P with a film thickness of 50 nm
The method of providing on the type conductive layer (P-AlGaAs layer) is as follows.
July 993 IEICE, IEICE Technical Report (p111)
It is described in. This method uses AlGaAs / GaAs.
In order to improve the performance of s-HBT (Heterojunction Bipolar Transistor), the purpose of the present invention is to reduce the thickness of the P-type base layer. It is described that an electrode is used, whereby a low contact resistance is obtained, and even if a heat treatment at 350 ° C. is performed, the contact resistance does not deteriorate.

A method using a four-layered electrode of Au / Pt / Ti / Pt as a Schottky gate electrode of InAlAs / InGaAs.HEMT is disclosed in 1991.
Fall 2005, 52nd Annual Meeting of the Japan Society of Applied Physics, Proceedings of Lectures 10a-H-3 (P1192). According to this method, Pt has a high Schottky barrier height (0.82 V) with respect to InGaAs, and fluctuation of the threshold voltage due to heat treatment of the HEMT using the above electrode at 350 ° C. was examined. However, it is stated that it remained stable after a fluctuation of about 0.15 V.

[0004]

The above Au / Pt / Ti
/ Pt, which is the lowermost layer of the four-layer electrode,
Reacts with GaAs by heat treatment to form PtAs ₂ , Pt
Intermetallic compounds such as Ga are produced. The PtAs is N
It exhibits good Schottky characteristics with respect to the GaAs, and has a reduced Schottky barrier with respect to the P-type, so that a good ohmic junction can be obtained.

[0005] However, Ti also reacts with GaAs by heat treatment to form an intermetallic compound in the same manner.
By the above heat treatment, the Ti from the second Ti layer forms a metal compound layer of the Pt layer as the first layer and a layer of TiAs, TiGa or the like at a position deeper than the metal compound layer. The PtAs ₂ layer is destroyed, and the ohmic characteristics and the Schottky characteristics deteriorate.

That is, an electrode having a four-layer structure of Au / Pt / Ti / Pt, which contains, for example, Be as a dopant, has a carrier concentration of 4 × 10 ¹⁹ cm ⁻³ and a film thickness of 100 nm
When used as an ohmic electrode for the P-type InGaAs layer, when the thickness of the lowermost Pt film is 5 nm, as shown by a characteristic line 101 in FIG. Beginning at 400 ° C., the more nonlinear the IV characteristic by TLM measurement becomes,
The problem that the increase becomes remarkable arises. Further, as the P-type conductive layer, AlGaAs is used instead of the InGaAs layer.
Similarly, when the s layer is used, the contact resistance significantly increases at 400 ° C. or higher.

Further, when the electrode having the four-layered structure of Au / Pt / Ti / Pt is used as a Schottky electrode of a diode using an N-type GaAs substrate, the temperature is reduced from 300.degree.
In the heat treatment at 00 ° C., the Schottky barrier height φBn is
The value was as high as 0.85 to 0.87 V, and the n value was also 1.05 to 1.1, which is close to 1, which is a value in an ideal case, indicating good Schottky characteristics. However, when the heat treatment temperature rises to 400 ° C. or higher, the Schottky barrier height φBn decreases to 0.42 to 0.50 V, and the n value also increases to 2.0 or more. There has been a problem that the electrode surface is rough.

[0008] Therefore, it is difficult to form a stable ohmic electrode with a small increase in contact resistance and a Schottky electrode without deteriorating Schottky characteristics even if heat treatment at 400 ° C. or higher is performed.
This has been an obstacle to producing a high-speed high-frequency device using a compound semiconductor such as GaAs with good reproducibility.

An object of the present invention is to solve the problems of the prior art and to provide a compound semiconductor device having an electrode whose contact resistance and Schottky characteristics do not deteriorate even after a process at 400 ° C. or higher, and a method of manufacturing the same. That is.

[0010]

In order to achieve the above object, the present invention provides a method for forming a barrier metal layer on a first layer (for example, a Pt layer) for forming an ohmic junction or a Schottky junction with the above-mentioned semiconductor substrate from a high melting point metal. Forming a second layer (for example, a Mo layer), and a component (for example, Ti) constituting a third layer formed on the second layer diffuses into the compound semiconductor substrate via the first layer. It is to prevent that. The refractory metal layer as the second layer is made of N
A film of b, Mo, W, Ta, V, Zr, Hf, or the like can be used. Further, a thin Ti layer may be interposed between the Pt layer serving as the first layer and the refractory metal layer. If the thickness of this Ti layer is sufficiently small (1 to 30 nm),
There is no particular problem.

[0011]

According to the study of the present inventor, the cause of the deterioration in the conventional electrode is that the Pt layer from the lowermost Pt layer
, But not in the Ti layer as the upper layer, as described above. Conventionally, the Ti layer has a structure of Au / Pt / Ti and has a GaAs MES.
Although it is used as a Schottky gate electrode of an FET or the like, the threshold value of this electrode fluctuates due to a change in heat treatment temperature. This is because when the temperature of the heat treatment is different, Ga
This is because the depth at which Ti diffuses into the substrate such as As changes.

Therefore, even in the case of the above-mentioned conventional Au / Pt / Ti / Pt electrode in which a thin Pt layer is interposed below the Ti layer, when the heat treatment is performed at 400 ° C. or more, the thick Ti layer as the second layer is formed. Is diffused into the substrate through the thin Pt layer which is the first layer, and as a result, the junction between the substrate and the electrodes is deteriorated, the contact resistance is increased, and the Schottky junction is further increased. In the case of, it is considered that the Schottky characteristics have deteriorated.

However, between the lowermost Pt layer and the Ti layer provided thereon, a Mo layer, which is a refractory metal, is inserted and formed by Au / Pt / Ti / Mo / Pt. An electrode having a layer structure was provided as an ohmic electrode on the P-type InGaAs layer, and a change in contact resistance due to heat treatment was examined by TLM measurement. P-type InG at this time
The aAs layer has a dopant of Be and a carrier concentration of 4 ×, similar to those used for obtaining the characteristics shown in FIG.
The thickness was 10 ¹⁹ cm ^-3 and the thickness was 100 nm. The thickness of the Mo layer was 30 nm, and the thickness of the lowermost Pt layer was 5 nm.

The obtained result is shown by a characteristic line 102 in FIG. When the conventional electrode was used, as is clear from the characteristic line 101 in FIG. 1, when the temperature became 400 ° C. or more, the contact resistance rapidly increased.
In the case of the t / Ti / Mo / Pt electrode, as shown by the characteristic line 102, the contact resistance is about 8 × 10 ⁻⁷ Ωcm ² even when the heat treatment temperature is 450 ° C. Much lower values were obtained than when used.

In the case of the Au / Pt / Ti / Mo / Pt electrode, the increase in the contact resistance was extremely small.
Is considered to be prevented by the Mo layer, the Ti was hardly diffused into the Pt layer as the first layer by the heat treatment, and the junction between the substrate and the electrode did not deteriorate. That is, Mo and Ti form a solid solution at a temperature of about 1600 ° C. or higher, but at temperatures lower than that, they are considered to be in a stable state with little reaction. Therefore, the Mo layer formed between the Ti layer and the Pt layer acts as a very effective barrier layer, and the T
The diffusion of i is effectively prevented, and as a result, the Pt layer which is the first layer reacts with GaAs without being affected by Ti to form PtAs ₂ ga, and good ohmic characteristics are obtained. Conceivable.

However, the characteristic lines 101 and 102 in FIG.
As is clear from the above, the absolute value of the contact resistance before the heat treatment was lower for the conventional electrode. This is Pt
_This is probably because an intermetallic compound layer having a high Ga composition and a high resistance, such as ₂ Ga ₃ , was formed between the substrate and the substrate. In order to reduce the difference between the two resistance values, a thin Ti layer is interposed between the Pt layer as the lowermost layer and Mo as the uppermost layer, thereby forming six layers of Au / Pt / Ti / Mo / Ti / Pt. An electrode having the above structure was formed on the substrate, and the same measurement was performed. At this time, the thickness of the added Ti layer is 5 nm,
The thicknesses of the other metal layers were the same as those of the five-layer structure electrode.

The obtained result is shown by a characteristic line 103 in FIG. As is clear from the characteristic line 103, Au / Pt / T
By using an electrode having a six-layer structure of i / Mo / Ti / Pt, an increase in contact resistance before heat treatment was effectively prevented, and the resistance was almost the same as that of the conventional electrode. In addition, even if the heat treatment is performed, the contact resistance slightly increases and shows a stable contact resistance. For example, the contact resistance after the heat treatment at 450 ° C. is about 6 × 10 ⁻⁷ Ω.
cm ² , which was lower than the electrode having the five-layer structure.

As described above, Au / Pt / Ti / Mo /
The electrode having a five-layer structure of Pt has a contact resistance after heat treatment at 450 ° C. of about 1/20 as compared with the conventional electrode having a four-layer structure, and can be sufficiently put to practical use. The electrode of the five-layer structure has a slightly larger absolute value of the contact resistance than the electrode of the conventional structure, but has an Au / Pt / T
The electrode having a six-layer structure of i / Mo / Ti / Pt has a much smaller increase in contact resistance in a high-temperature heat treatment than the conventional electrode, and has an absolute value of contact resistance lower than that of the five-layer electrode. It is almost the same as the electrode of the conventional structure, and was extremely excellent as an ohmic electrode. This is because if a thin Ti layer is interposed between the Mo layer and the Pt layer, Ga from the substrate enters the Ti layer through the Pt layer (Ga has a higher diffusion rate into the metal film than As), and P
It is considered that a low-resistance intermetallic compound layer having a small amount of Ga, such as tGa and Pt ₃ Ga, was formed to reduce the resistance, and the contact resistance was also reduced.

Further, the two types of electrodes of the present invention are
When a Schottky electrode of a diode using a GaAs substrate is used, both of them have a Schottky barrier height φBn of 0.82 to 0.86 V by heat treatment at 300 ° C. to 400 ° C. as in the case of the conventional electrode. And the n value is also 1.
07 to 1.12 showed stable and good Schottky characteristics. Moreover, even after the heat treatment at 430 ° C. for 30 minutes, the Schottky barrier height φBn is 0.8 V
It shows a high value of ~ 0.84V, and the n value is 1.14 ~
It remained good at 1.21. From this, Au / P
t / Ti / Mo / Ti / Pt 6 layer structure electrode, and Au
It was confirmed that the / Pt / Ti / Mo / Pt five-layer structure electrode can be used also as a good Schottky electrode.

[0020]

<Embodiment 1> The present invention is applied to InGaAs / InP.
First Embodiment A first embodiment applied to an HBT will be described with reference to FIG. Using a well-known MBE method, a semi-insulating InP substrate 1
0, a carrier concentration of 5 × containing Si as a dopant.
10 ¹⁹ cm ^-3, the sub-collector layer 11 made of N ⁺ -InGaAs layer having a film thickness of 600 nm, carrier concentration 4 × 10 ¹⁹ cm ^-3 comprising collector layer 12, Be made of undoped InGaAs layer having a thickness of 300nm as a dopant, Base layer 1 made of a P ⁺ -InGaAs layer having a thickness of 50 nm
3, a 150 nm-thick spacer layer 14 of an undoped InGaAs layer, a carrier concentration of 3 × 10 ¹⁷ cm ⁻³ containing Si as a dopant, and a 100 nm-thickness N-InG layer.
an emitter layer 15 made of an aAs layer, a spacer layer 16 made of undoped InGaAs having a thickness of 100 nm, and S
Carrier concentration containing i as a dopant 5 × 10 ¹⁹ cm
^-3 , a contact layer 17 made of an N ⁺ -InGaAs layer having a thickness of 150 nm was sequentially grown, and an emitter electrode 18 made of WSi was formed at a desired position on the N ⁺ -InGaAs contact layer 17.

Next, using the emitter electrode 18 as a mask, wet etching is performed using a mixed solution of phosphoric acid, H ₂ O ₂ and H ₂ O as an etchant to form P ⁺ -InG
The surface of the base layer 13 made of the aAs layer was exposed.

The thickness is 2 using a well-known plasma CVD method.
After forming a 00 nm SiO ₂ film on the entire surface, a resist pattern (not shown) having a predetermined shape is formed by using a well-known photolithography technique, and C ₂ F is formed through an opening of the resist pattern. Plasma etching was performed using a mixed gas of ₆ and CHF ₃ as an etching gas, and the P ⁺ -InG formed in the base electrode formation region was formed.
The surface of the base layer 13 made of the aAs layer was exposed. At this time, on the side surface of the emitter electrode 18 or the like, the Si
The side wall 19 made of the O ₂ film was formed.

Using a well-known EB evaporation method, a Pt film having a thickness of 5 nm, a Ti film having a thickness of 5 nm, a Mo film having a thickness of 30 nm,
After a 50 nm-thick Ti film, a 50 nm-thick Pt film, and a 200 nm-thick Au film are sequentially laminated and formed on the entire surface, unnecessary portions are removed using a well-known lift-off method.
The base electrode 20 having a six-layer structure of u / Pt / Ti / Mo / Ti / Pt was formed.

Using a known photolithography technique, a photoresist mask (not shown) having a desired shape is formed, and wet etching using a mixed solution of phosphoric acid, H ₂ O ₂ and H ₂ O is performed. The surface of the ⁺ -InGaAs subcollector layer 11 was exposed. After forming a 200-nm-thick SiO ₂ film on the entire surface by using a well-known plasma CVD method, a known selective etching is performed by photolithography and plasma etching using a mixed gas of C ₂ F ₆ and CHF ₃ to form a collector. N ⁺ -InGaAs in electrode formation region
The surface of the subcollector layer 11 was exposed.

Using a well-known EB evaporation method, a film thickness of 60 nm
AuGe film, 10 nm thick W film, 10 nm thick N
After an i-film and a 200 nm-thick Au film are sequentially laminated to form an entire surface, unnecessary portions are removed by a known lift-off method, and further heat treatment is performed at 400 ° C. for 5 minutes in an N ₂ atmosphere. Au / Ni / W / AuG
e, a collector electrode 21 having a four-layer structure is formed.
nGaAs / InPHBT was completed.

In this embodiment, when the collector electrode 21 is formed, a heat treatment at 400 ° C. for 5 minutes is performed for alloying, but the contact resistance of the base electrode 20 after this heat treatment is reduced. 5.4 × 10 ^-7 Ωcm
² showed very good ohmic properties. Furthermore, even when a heat treatment is performed at 430 ° C. for 60 minutes in an N ₂ atmosphere, the contact resistance of the base electrode 20 is 6.3 × 10 ^−7.
A good ohmic characteristic of Ωcm ² was exhibited, and the withstand voltage between the base and the collector was -5.2 V, which was almost the same value as before the heat treatment. Thereby, the Au formed in the present embodiment is formed.
It was confirmed that the / Pt / Ti / Mo / Ti / Pt electrode was a P-type ohmic electrode that was not deteriorated by heat treatment and had high heat resistance.

In the present embodiment, Au / Pt /
Although the case where the electrode having the six-layer structure of Ti / Mo / Ti / Pt is used is shown, the electrode having the five-layer structure of Au / Pt / Ti / Mo / Pt also has better heat resistance than the conventional electrode. It has been confirmed that it can be put to practical use.

<Embodiment 2> The present invention is applied to a GaAs / MESF
A second embodiment applied to ET will be described with reference to FIG. First, as shown in FIG. 3, using a well-known ion implantation method using a photoresist film as a mask, semi-insulating Ga is used.
After a shallow implantation of silicon ions into a predetermined portion of the As substrate 22, the implantation was further deepened and activated by annealing at 800 ° C. for about 20 minutes to form a first active layer 23 and a second active layer 24.

Using a well-known atmospheric pressure CVD method, a thickness of 50 nm
After forming an SiO ₂ film 25 on the entire surface, a source / drain electrode forming pattern (not shown) made of photoresist is formed at a desired position on the substrate 22, and C ₂ F ₆ and C ₂
A predetermined portion of the SiO ₂ film 25 was removed by plasma etching using a mixed gas of HF _{3 as} an etching gas to expose the surface of the substrate 22.

Using a well-known EB evaporation method, an AuGe film,
W film, Ni film and Au film are sequentially laminated on the entire surface and formed.
Then, unnecessary parts are removed by a well-known lift-off method.
N _TwoHeat treatment at 400 ° C for 5 minutes in an atmosphere
AuGe / W / Ni / Au
A source / drain electrode 26 having a structure was formed.

Next, a gate electrode forming pattern (not shown) made of a photoresist film having a predetermined shape is formed at a desired position between the source / drain electrodes 26.
The SiO ₂ film 25 exposed through the opening of the gate electrode forming pattern is plasma-etched using a mixed gas of C ₂ F ₆ and CHF ₃ to form the first active layer 23.
Surface was exposed.

A Au / Pt / Ti / Mo / Pt metal laminated film is formed on the exposed surface of the first active layer 23 by a well-known EB vapor deposition method, and then the well-known lift-off method is used. The gate electrode forming pattern and the metal laminated film formed thereon were removed, and Au / Pt was removed.
A gate electrode 27 having a five-layer structure of / Ti / Mo / Pt is formed to form a GaAs-MESFE having a structure shown in FIG.
T is completed. The lowermost P of the gate electrode 27
The thickness of the t film was 10 nm.

MESFET formed by this embodiment
In the Schottky characteristics, the Schottky barrier height φBn was as high as 0.84 V and the n value was 1.06, which was very good. In this embodiment, the gate electrode 27 is formed after the source / drain electrodes 26 are formed. In this case, the heat treatment at about 400 ° C. performed when forming the source / drain electrodes 26 is not performed after the gate electrode is formed. However, when forming a very short gate electrode having a gate length of 0.5 μm or less, if the source / drain electrodes are formed first, when forming the gate electrode forming pattern made of a photoresist film, The size of the gate electrode forming pattern changes due to halation due to irregular reflection from the source / drain electrodes, and the size of the gate electrode changes.

In order to eliminate such defects, it is effective to form the gate electrode before forming the source / drain electrodes. However, when a conventional electrode is used, the heat resistance is not high. The order of formation could not be changed. However, in the present invention, since the electrode has excellent heat resistance, there is no problem even if the order of the steps is changed as described above, and there is no possibility that the dimensions of the gate electrode are changed.

In this embodiment, Au /
Although a five-layer electrode of Pt / Ti / Mo / Pt was used,
An additional Ti film is inserted between the o film and the lowermost Pt film,
It goes without saying that a six-layer electrode of Au / Pt / Ti / Mo / Ti / Pt may be used.

<Embodiment 3> The third embodiment of the present invention
This will be described with reference to FIG. 4 showing a cross-sectional structure of the aAs.HIGFET. A well-known MBE is formed on a semi-insulating GaAs substrate 28.
Undoped GaAs layer 2 having a thickness of 300 nm
9. The carrier concentration is 3 × 10 ^{16 using} Be as a dopant.
P-AlGaAs layer 30 having a thickness of 300nm in cm ^-3, S
Carrier concentration is 3 × 10 ¹⁸ cm ^{−3 using} i as a dopant
, An N-GaAs layer channel layer 31 having a thickness of 20 nm; an undoped AlGaAs layer 32 having a thickness of 10 nm;
After sequentially growing m undoped GaAs layers 33, a 100 nm thick SiO ₂ film was formed on the entire surface by plasma CVD.

Next, a pattern for selective growth of an N ⁺ layer made of a photoresist film was formed at a desired position on the undoped GaAs layer 33. The surface of the undoped GaAs layer 33 in the N ⁺ layer selective growth region is exposed by performing plasma etching using a mixed gas of C ₂ F ₆ and CHF ₃ through the opening of the N ⁺ layer selective growth pattern. Then, wet etching is performed using a mixed solution of phosphoric acid, H ₂ O ₂ and H ₂ O, and the N-GaAs layer channel layer 31 is formed.
Surface was exposed.

On the exposed surface of the N-GaAs layer channel layer 31, N ⁺ − is formed by a well-known MOCVD method.
The GaAs layer 34 was selectively grown. At this time, Si was used as a dopant, and the carrier concentration was 3 × 10 ¹⁸ c
m ⁻³ , the film thickness was 400 nm, and the substrate temperature was 550 ° C.

Next, after a 50 nm thick SiO ₂ film 35 is formed on the entire surface by a well-known normal pressure CVD method, a source / drain electrode forming pattern (not shown) made of a photoresist film having a predetermined opening is formed. ) Formed. Through the opening of the source / drain electrode formation pattern, the S 2 gas was mixed with C ₂ F ₆ and CHF ₃ to form
The iO ₂ film 35 is plasma-etched to perform the N ⁺ -GaAs
The surface of the s layer 34 was exposed.

After the Au / Ni / W / AuGe laminated metal film is formed on the entire surface of the substrate, the source / drain electrode forming pattern and the laminated metal film formed thereon are removed by a known lift-off method. Then, an alloying process was performed at 400 ° C. for 5 minutes in an N ₂ atmosphere to form a source / drain electrode 36 having a four-layer structure of Au / Ni / W / AuGe.

Next, a gate electrode forming pattern (not shown) made of a photoresist film is formed at a desired position between the source / drain electrodes 36, and is formed through an opening of the gate electrode forming pattern. The exposed portion of the SiO ₂ film 35 is plasma-etched with a mixed gas of C ₂ F ₆ and CHF ₃ to form the undoped GaAs film 33.
Was exposed, and an Au / Pt / Ti / Mo / Pt laminated metal film was formed by a well-known EB evaporation method.

The gate electrode forming pattern and the laminated metal film formed thereon are removed by using a well-known lift-off method to form a gate electrode having a five-layer structure of Au / Pt / Ti / Mo / Pt. 37 were formed, and the GaAs HIGFET having the cross-sectional structure shown in FIG. 4 was completed. The lowermost Pt film had a thickness of 5 nm.

In this embodiment, the source / drain electrodes 36
After the formation of the gate electrode 37, the gate electrode 37 may be formed earlier than the source / drain electrode 36 as in the second embodiment. In this embodiment, Au / Pt / T is used as the gate electrode.
Although a five-layer electrode of i / Mo / Pt was used, MESF
As in the case of ET, Au / Pt / Ti / Mo / Ti /
A six-layer electrode of Pt may be used.

<Embodiment 4> A fourth embodiment of the present invention will be described with reference to Ga.
This will be described with reference to FIG. 5 showing a cross-sectional structure of As-HEMT.
On a semi-insulating GaAs substrate 38, using a well-known MBE method, an undoped GaAs layer 39 having a thickness of 600 nm, an undoped InGaAs channel layer 40 having a thickness of 20 nm, an undoped AlGaAs layer 41 having a thickness of 5 nm, and a carrier using Si as a dopant. Concentration is 3 × 10 ¹⁸ cm ^-2 and film thickness 2
0 nm N-AlGaAs electron supply layer 42, thickness 10n
A 100 nm-thick N ⁺ -GaAs layer 44 having a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ and a thickness of 100 nm is sequentially grown using the undoped AlGaAs barrier layer 43 of m and Si as a dopant, and then a known plasma CVD method is used. And thickness 5
A 00 nm SiO ₂ film 45 was formed on the entire surface.

After forming a source / drain electrode forming pattern (not shown) made of a photoresist film having a predetermined shape, C ₂ F ₆ is formed through an opening of the source / drain electrode forming pattern. Plasma etching is performed using a mixed gas of CHF ₃ to form the SiO ₂ film 4.
5 is removed, and the N ⁺ -GaAs layer 4 is removed.
4 was exposed.

Next, Au / Ni / W / AuGe laminated metal
After forming the film using a known method, a known lift-off is performed.
The source / drain electrode formation pattern
And removing the laminated metal film formed thereon
Processed to a fixed shape and N _Two400 ℃ in atmosphere, 5
Minute alloying treatment to obtain Au / Ni / W / Au
A source / drain electrode 46 having a four-layer structure of Ge
Formed.

After forming a gate electrode forming pattern (not shown) made of a photoresist film having an opening in the gate electrode forming region, the exposed portion of the SiO ₂ film 45 exposed through the opening is formed. Is removed by plasma etching using a mixed gas of C ₂ F ₆ and CHF ₃ , exposing the surface of the N ⁺ -GaAs layer 44, and performing the well-known reactive ion etching to obtain the N ⁺
The exposed portion of the GaAs layer 44 was removed, exposing the surface of the undoped AlGaAs barrier layer 43.

After a laminated metal film of Au / Pt / Ti / Mo / Pt was formed on the entire surface by a well-known EB evaporation method, the above-described gate electrode forming pattern and a pattern formed thereon were formed by a well-known lift-off method. The laminated metal film was removed to form a gate electrode 47 having a five-layer structure of Au / Pt / Ti / Mo / Pt, and a GaAs HEMT having a cross-sectional structure shown in FIG. 5 was completed. The lowermost Pt layer had a thickness of 5 nm.

In this embodiment, the source / drain electrodes 46
After the formation of the gate electrode 47, the gate electrode 47 may be formed earlier than the source / drain electrodes 46, as in the second embodiment. In this embodiment, a five-layer electrode of Au / Pt / Ti / Mo / Pt is used for the gate electrode 47. However, as in the case of the MESFET, a six-layer electrode of Au / Pt / Ti / Mo / Ti / Pt is used. A gate electrode having a structure may be used.

<Embodiment 5> The fifth embodiment of the present invention
This will be described with reference to FIG. On a semi-insulating GaAs substrate 48, an undoped GaAs layer 49 having a thickness of 600 nm, an undoped AlGaAs layer 50 having a thickness of 5 nm, a Si concentration as a dopant and a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ are formed by a known MBE method. N-GaAs channel layer 51 of 50 nm, thickness of 20 n
carrier concentration comprises an undoped AlGaAs layer 52 and Be as a dopant of m is grown by sequentially stacking the P + -GaAs layer 53 having a thickness of 100nm at 4 × 10 ¹⁹ cm ^-3, further SiO ₂ film having a thickness of 100nm Formed on the entire surface by a known plasma CVD method.

After a mesa etching pattern (not shown) made of a photoresist film covering the gate electrode formation region on the P ⁺ -GaAs layer 53 is formed, C ₂ F ₆ and CHF are formed.
By plasma etching using ₃ gas mixture, the SiO ₂ film exposed portions were removed, and the formed in the region other than the gate electrode forming region P ⁺ -GaAs
The layer 53 was exposed, and the mesa etching pattern was removed.

Using the SiO ₂ film as a mask, the P ⁺ -GaAs layer 53 in the opening was mesa-etched by reactive ion etching to expose the surface of the undoped AlGaAs layer 52.

Next, a film thickness of 2 is formed using a well-known atmospheric pressure CVD method.
After a 0-nm SiO ₂ film is formed on the entire surface, silicon ions are implanted by ion implantation using a photoresist film as a mask, and annealing is performed at 800 ° C. for 20 minutes to activate the silicon ions to form an N-type ohmic contact. Layer 54 was formed.

Using a well-known atmospheric pressure CVD method, a film thickness of 500
After forming a SiO ₂ film 55 nm in thickness over the entire surface, a photoresist pattern for forming source / drain electrodes was formed.
Through the opening of the photoresist pattern, the Si
The exposed portion of the O ₂ film 55 was removed by plasma etching using a mixed gas of C ₂ F ₆ and CHF ₃ to expose the surface of the N-type ohmic contact layer 54.

Using a known method, Au / Ni / W / Au
After a laminated metal film made of Ge is formed on the entire surface, the resist pattern and the laminated metal film formed thereon are removed by using a well-known lift-off method, and further at 400 ° C. for 5 minutes in an N ₂ atmosphere. An alloying process is performed to form a five-layer Au / Ni / W / AuGe source / source on the exposed surface of the N-type ohmic contact layer 54.
A drain electrode 56 was formed.

Next, using a gate electrode forming pattern (not shown) made of a photoresist film having a predetermined shape as a mask, plasma etching is performed with a mixed gas of C ₂ F ₆ and CHF ₃ to form the SiO _2. The exposed portion of the film 55 was removed, and a laminated metal of Au / Pt / Ti / Mo / Ti / Pt was formed on the exposed P ⁺ -GaAs layer 53 by a well-known EB evaporation method. The gate electrode forming pattern and the laminated metal film formed thereon are removed by a well-known lift-off method, and A
A gate electrode 57 having a six-layer structure of u / Pt / Ti / Mo / Ti / Pt was formed to complete a GaAs JFET having a cross-sectional structure shown in FIG. Note that the lowermost layer P
The thickness of the t film is 5 nm, and the thickness of the second Ti layer is 10 nm.
And

In this embodiment, the source / drain electrodes 56
After the formation of the gate electrode 57, the gate electrode 57 may be formed first as in the second embodiment.
In this embodiment, Au / Pt / T is used as the gate electrode.
Although a six-layered electrode of i / Mo / Ti / Pt is used, a five-layered electrode of Au / Pt / Ti / Mo / Pt may be used as in the second embodiment. In each of the above embodiments, the case where Mo was used as the high melting point metal was shown.
Similar effects were obtained by using b, W, Ta, V, Zr or Hf.

In each of the above embodiments, the case where the Pt layer is used as the first refractory metal layer in contact with the substrate has been described. However, instead of the Pt layer, the element constituting the compound semiconductor substrate and the Pt metal A compound layer or an alloy layer of Pt and Ti may be used. As the fifth refractory metal layer provided between the first refractory metal layer and the second refractory metal layer, Ti may be used. Not only a layer but also an intermetallic compound layer of an element constituting a compound semiconductor serving as a substrate or an alloy layer of Pt and Ti may be used.

[0059]

According to the present invention, a compound semiconductor device having an electrode having good ohmic characteristics and Schottky characteristics with respect to a compound semiconductor can be obtained with good reproducibility.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between a heat treatment temperature and a contact resistance in an electrode of the present invention and a conventional electrode;

FIG. 2 is a sectional view showing Embodiment 1 of the present invention;

FIG. 3 is a sectional view showing a second embodiment of the present invention;

FIG. 4 is a sectional view showing a third embodiment of the present invention;

FIG. 5 is a sectional view showing a fourth embodiment of the present invention;

FIG. 6 is a sectional view showing a fifth embodiment of the present invention.

[Explanation of symbols]

10 ... Semi-insulating InP substrate, 11 ... N + -InG
aAs subcollector layer, 12 undoped InGaAs
s collector layer, 13... P + -InGaAs base layer, 14... undoped InGaAs spacer layer,
15 N-InGaAs emitter layer 16 Undoped InGaAs spacer layer 17 N + -In
GaAs contact layer, 18 WSi emitter electrode, 19 SiO ₂ sidewall, 20 A
u / Pt / Ti / Mo / Ti / Pt base electrode, 21
... AuGe-based collector electrode 22... Semi-insulating Ga
As substrate, 23 first active layer 24 second active layer 25 SiO ₂ film 26 AuGe-based source / drain electrodes 27 Au / Pt / Ti / Mo
/ Ti / Pt gate electrode, 28 ... Semi-insulating GaAs
Substrate, 29 ... Undoped GaAs layer, 30 ... P
-AlGaAs layer, 31 ... N-GaAs channel layer, 32 ... Undoped AlGaAs layer, 33 ... Undoped GaAs layer, 34 ... N + -GaAs layer, 35
...... SiO ₂ film, 36 ...... AuGe based source and drain electrodes, 37 ...... Au / Pt / Ti / Mo / Pt gate electrode 38 ...... semi-insulating GaAs substrate, 39 ...... undoped GaAs layer, 40 ...... undoped InGaAs channel layer, 41 ... undoped AlGaAs layer, 42 ... N
-AlGaAs electron supply layer, 43 ... undoped Al
GaAs barrier layer, 44... N + -GaAs layer, 45
... SiO ₂ film, 46 ... AuGe-based source / drain electrode, 47 ... Au / Pt / Ti / Mo / Pt gate electrode 48 ... Semi-insulating GaAs substrate, 49 ... Undoped GaAs layer, 50 ... Undoped An AlGaAs layer,
51: N-GaAs channel layer, 52: undoped AlGaAs layer, 53: P + -GaAs layer, 5
4 ... N-type ohmic contact layer, 55 ... SiO
₂ films, 56... AuGe source / drain electrodes,
57 ... Au / Pt / Ti / Mo / Ti / Pt gate electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/737 29/812 (72) Inventor Tomoki 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi, Ltd. F-term in the Central Research Laboratory (reference) 4M104 AA04 AA05 AA07 BB06 BB10 BB13 BB14 BB28 CC01 CC03 DD35 DD68 DD78 DD83 EE09 EE16 GG06 GG11 GG12 HH15 HH20 5F003 BA92 BB01 BE01 BH08 BH99 BM03 BG11 G01 BP11 G01 BP12 GL05 GM05 GM06 GM08 GN05 GQ01 GS02 GT01 GT03 HC01 HC02 HC07 HC16 HC19 HC21

Claims (26)

[Claims] A first refractory metal layer, a second refractory metal layer, a third refractory metal layer, and a third refractory metal layer having a predetermined shape, which are formed on the compound semiconductor substrate in order and are in ohmic contact with the compound semiconductor substrate. An electrode comprising a high-melting point metal layer, a fourth high-melting point metal layer, and a low-resistance conductor layer, wherein the second high-melting point metal layer comprises the semiconductor of the component constituting the third high-melting point metal layer A compound semiconductor device having a function of preventing diffusion to a substrate. 2. The method according to claim 1, wherein a fifth refractory metal layer is provided between the first refractory metal layer and the second refractory metal layer. Compound semiconductor device. 3. The compound semiconductor device according to claim 1, wherein the conductivity type of said semiconductor substrate is p-type. 4. A first refractory metal layer, a second refractory metal layer, a third refractory metal layer, and a third refractory metal layer having a predetermined shape, which are sequentially laminated on the compound semiconductor substrate and have a Schottky connection with the compound semiconductor substrate. An electrode comprising a high-melting point metal layer, a fourth high-melting point metal layer and a low-resistance conductor layer, wherein the second high-melting point metal layer is a component of the third high-melting point metal layer. A compound semiconductor device having a function of preventing diffusion into a semiconductor. 5. The method according to claim 4, wherein a fifth refractory metal layer is provided between the first refractory metal layer and the second refractory metal layer. Compound semiconductor device. 6. The compound semiconductor device according to claim 4, wherein the conductivity type of said compound semiconductor substrate is N-type or undoped. 7. The first refractory metal layer is composed of Pt, an intermetallic compound of Pt with an element constituting the compound semiconductor, and Pt.
The compound semiconductor device according to any one of claims 1 to 6, wherein the compound semiconductor device is a film made of a material selected from the group consisting of an alloy of t and Ti. 8. The second refractory metal layer is made of Mo, Nb,
The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a film made of a material selected from the group consisting of W, Ta, V, Zr, and Hf. 9. The compound semiconductor device according to claim 1, wherein said third refractory metal layer is a film made of Ti. 10. The compound semiconductor device according to claim 1, wherein said fourth refractory metal layer is a film made of Pt. 11. The fifth refractory metal layer is a film made of a material selected from the group consisting of Ti, an intermetallic compound of an element constituting the compound semiconductor and Ti, and an alloy of Pt and Ti. The compound semiconductor device according to claim 3 or 7, wherein 12. The compound semiconductor device according to claim 4, wherein said electrode is a gate electrode of a field effect transistor. 13. The compound semiconductor device according to claim 1, wherein said electrode is a base electrode of a bipolar transistor. 14. The first refractory metal layer has a thickness of 1 nm.
The compound semiconductor device according to any one of claims 1 to 13, wherein the thickness is from 30 to 30 nm. 15. The film thickness of the second refractory metal layer is 10 m.
15 to 100 nm.
The compound semiconductor device according to any one of the above. 16. The compound semiconductor device according to claim 1, wherein said third or fifth refractory metal layer has a thickness of 10 to 200 nm. 17. The film thickness of the fourth refractory metal layer is 10 m.
17. The structure according to claim 1, wherein the thickness is from 200 to 200 nm.
The compound semiconductor device according to any one of the above. 18. The compound according to claim 1, wherein said low-resistance metal film is a film made of a material selected from the group consisting of Au, Al, W and Mo. Semiconductor device. 19. A sub-collector layer composed of a low-resistance compound semiconductor layer having a first conductivity type and a collector layer composed of a high-resistance compound semiconductor layer having a first conductivity type and formed sequentially on a compound semiconductor substrate. A base layer made of a compound semiconductor layer having a second conductivity type opposite to the mold type, an emitter layer made of the compound semiconductor layer having the first conductivity type, an emitter electrode made of a low-resistance conductor layer, and an exposed portion of the base layer. A base electrode formed on the exposed surface of the base layer, wherein the base electrode is formed on the exposed surface of the base layer, and is formed of a first refractory metal that is in ohmic contact with the base layer. Layer, a second refractory metal layer,
An electrode comprising a third refractory metal layer, a fourth refractory metal layer, and a low-resistance conductor layer; and the second refractory metal layer forms the third refractory metal layer. A compound semiconductor device having a function of preventing a component to be diffused into the base layer. 20. The compound semiconductor according to claim 19, wherein a fifth refractory metal layer is provided between said first refractory metal layer and said second refractory metal layer. apparatus. 21. An ohmic contact layer, a first refractory metal layer, and a second refractory metal formed on a compound semiconductor substrate and sequentially formed on the compound semiconductor substrate, the contact layer comprising a compound with the compound semiconductor and the compound semiconductor substrate. A compound semiconductor device comprising an ohmic electrode including at least a layer and a conductor layer. 22. An ohmic contact layer with the compound semiconductor substrate, comprising at least two kinds of ohmic connection elements composed of a compound with the compound semiconductor substrate, which are successively formed on the compound semiconductor substrate. A compound semiconductor device comprising an ohmic electrode including at least a high melting point metal layer, a second high melting point metal layer, and a conductor layer. 23. A first refractory metal film made of a material for forming an ohmic connection or a Schottky connection with the first region on the first region of the compound semiconductor substrate;
A step of sequentially laminating a second refractory metal film, a third refractory metal film, a fourth refractory metal film, and a low-resistance conductor film to form a metal laminated film; and unnecessary portions of the metal laminated film. At least a step of forming a first electrode by removing and a step of heat-treating at a temperature higher than 300 ° C., wherein the second refractory metal film is a component of the third refractory metal film. A method for manufacturing a compound semiconductor device having a function of preventing diffusion into a compound semiconductor substrate. 24. After forming the first electrode, the method includes a step of forming a second electrode on a second region of the semiconductor substrate, and the step of heat treating includes forming the second electrode. The method for manufacturing a compound semiconductor device according to claim 23, wherein the method is performed later. 25. The method according to claim 24, wherein the first and second electrodes are a gate electrode and a source / drain electrode of a field effect transistor, respectively. 26. The method according to claim 24, wherein the first and second electrodes are a base electrode and a collector electrode of a bipolar transistor, respectively.