JP2002353144A - p-TYPE III NITRIDE SEMICONDUCTOR, ITS PRODUCING METHOD AND SEMICONDUCTOR DEVICE - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low resistance p-type III nitride semiconductor, and its producing method, in which a mother crystal can be doped efficiently and heavily with three atom complex dopant. SOLUTION: A low temperature GaN buffer layer 11 and a p-type GaN layer 12 are formed sequentially on a sapphire substrate 10. The p-type GaN layer 12 is doped with p-type impurities, i.e., Mg (magnesium) and O (oxygen), by about 1×10<20> cm<-3> and 3×10<19> cm<-3> , respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a light source for an optical pickup such as a DVD or a CD, a writing light source for an electrophotograph, a light source for an optical communication, a display panel, a lighting fixture, an ultraviolet sensor, a high-temperature operating transistor, and the like. p-type II
The present invention relates to a group I nitride semiconductor, a manufacturing method thereof, and a semiconductor device.

[0002]

2. Description of the Related Art In recent years, a high-intensity blue LED using a group III nitride semiconductor represented by GaN and a purple LD oscillating at an output of about 30 mW have been put to practical use. Also, ultraviolet sensors, high-temperature operation transistors, and the like have been developed. Further, utilizing these semiconductor elements, a full-color display, a white light source, a traffic light, a lighting device, an optical recording medium writing / reading device, a laser microscope, and the like have been developed. For the practical use of a semiconductor device using these group III nitride semiconductors, a technique for manufacturing a p-type group III nitride semiconductor is an important basic technique.

For example, a p-type group III nitride semiconductor used for a semiconductor device such as a light emitting element requiring a high current density requires a high carrier concentration. However, a group III nitride semiconductor having a wide band gap cannot be a p-type one having a high carrier concentration. For example, in AlGaN used for a cladding layer of a semiconductor laser, it is difficult to produce AlGaN having a carrier concentration exceeding 10 ¹⁸ cm ⁻³ . This is because the acceptor level of the group III nitride semiconductor is deep. In AlGaN, as the band gap increases, the acceptor level becomes deeper, so that the activation rate of the acceptor at room temperature decreases. For example, even if GaN does not contain Al, the activation rate of the acceptor at room temperature is 1% or less. Therefore,
Even if GaN is doped with an acceptor impurity of about 10 ²⁰ cm ^{−3, the} carrier concentration is only about 10 ¹⁸ cm ⁻³ . AlG with acceptor level deeper than GaN
In the case of aN, the activation rate is further reduced, so that the carrier concentration is further reduced. Even if the doping amount of the acceptor impurity is increased to increase the carrier concentration, if the doping amount exceeds 10 ²⁰ cm ⁻³ , the acceptor impurity enters the interstitial position and functions as a donor. As a result, the carrier concentration decreases. Therefore, even if the doping amount is increased, the carrier concentration has an upper limit.
For example, it is about 10 ¹⁸ cm ^{-3 in} GaN.

As a method for solving this problem, Japanese Patent Laid-Open No.
No. 101496 (hereinafter referred to as prior art 1) discloses Mg
And Si at a ratio of 2: 1, Mg and O at a ratio of 2: 1, Be and Si at a ratio of 2: 1, or Be and O at a ratio of 2: 1.
A method of increasing the carrier concentration by simultaneously doping GaN at about 10 ¹⁸ cm ⁻³ to about 10 ²⁰ cm ⁻³ at a ratio of 1 to 10 cm ^{3 is} disclosed. In this method, a complex composed of two atoms of an acceptor impurity and one atom of a donor impurity is formed in a host crystal (GaN in this case), so that the impurity level (acceptor level) becomes shallower, Since the solid capacity of the acceptor impurity is increased, p-type GaN having a high carrier concentration can be manufactured.

Japanese Patent Application Laid-Open No. Hei 10-144960 (hereinafter referred to as prior art 2) discloses that by doping Si and Mg at a Si / Mg ratio of 1/10 or more and 1/1 or less,
It is shown that the same effect as that of the prior art 1 can be obtained. Japanese Patent Application Laid-Open No. H10-154829 (hereinafter referred to as “prior art 3”) discloses that the same effect as in prior art 1 can be obtained by doping O and Mg at an O / Mg ratio of 1/10 or more and 1/1 or less. It is shown that it can be obtained. In addition, JP
000-294880 (hereinafter referred to as prior art 4) discloses that the same effect as in prior art 1 can be obtained by doping O and Zn at an O / Zn ratio of 1/5 or more and 1/2 or less. It is shown.

[0006]

As described above, it is difficult to produce a low-resistance p-type group III nitride semiconductor having a high carrier concentration and a low resistance. Therefore, the operating voltage of a semiconductor device using a p-type group III nitride semiconductor is high, which causes an increase in power consumption. In the case of a semiconductor laser, a high resistance of the p-type cladding layer and a high contact resistance of the p-side ohmic electrode increase the operating voltage during high-power operation, thereby causing heat generation and shortening the life.

In the method of forming a complex of two acceptor atoms and one donor atom in a host crystal and producing a low-resistance p-type semiconductor shown in Prior Art 1 to Prior Art 4, the crystal of the host crystal is grown. Since the acceptor impurity and the donor impurity are supplied as separate dopant source gases, the probability that a complex is formed when the dopant is incorporated into the growth host crystal is low, and most of them are used as a single dopant. Alternatively, it is taken into the base crystal as a diatomic complex. Then, Mg atoms or Zn atoms, which are acceptor impurities, form deep levels, and these dopants hinder the function of the target composite dopant.
It has been difficult to easily grow a group I nitride semiconductor crystal.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and provides a low-resistance p-type capable of efficiently and efficiently doping a three-atom complex dopant into a host crystal.
It is an object to provide a group III nitride semiconductor, a manufacturing method thereof, and a semiconductor device.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a p-type group III nitride semiconductor including a complex of an acceptor impurity and a donor impurity. A p-type group III nitride semiconductor is manufactured using a compound having a bond between a sexual impurity element and a donor impurity element as a dopant material.

According to a second aspect of the present invention, there is provided a method for manufacturing a p-type group III nitride semiconductor according to the first aspect, wherein the compound dopant having an acceptor impurity element and a donor impurity element has a bond with an acceptor impurity element. A feature is that a p-type group III nitride semiconductor is manufactured by simultaneously doping impurity materials.

According to a third aspect of the present invention, there is provided a p-type group III nitride semiconductor manufactured by the method for manufacturing a p-type group III nitride semiconductor according to the first or second aspect.

According to a fourth aspect of the present invention, there is provided a semiconductor device having a semiconductor laminated structure including the p-type group III nitride semiconductor according to the third aspect.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, an ohmic electrode is formed on the p-type group III nitride semiconductor.

According to a sixth aspect of the present invention, in the semiconductor device of the fourth or fifth aspect, the semiconductor device is a light emitting element having a light emitting region sandwiched between a p-type semiconductor and an n-type semiconductor. It is characterized by:

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the light emitting element is a semiconductor laser.

According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, all the p-type group III nitride semiconductor layers constituting the semiconductor laser are p-type group III nitride semiconductor layers according to the third aspect. It is characterized by being formed of a semiconductor.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment A first embodiment of the present invention relates to a method of manufacturing a p-type group III nitride semiconductor containing a complex of an acceptor impurity and a donor impurity, the method comprising the steps of: A p-type group III nitride semiconductor is manufactured using a compound having a bond with an element as a dopant material.

Here, the group III nitride semiconductor is Ga
The term means a binary compound of N, AlN, InN, and BN, or a ternary, quaternary, or ternary mixed crystal semiconductor that is a mixed crystal of these binary compounds.

A compound having a bond between an acceptor impurity element and a donor impurity element includes an acceptor impurity element and a donor impurity element as constituent elements of the compound, and includes an acceptor impurity element and a donor impurity element. Is a compound having one or more bonds.

Specifically, a compound having a bond between an acceptor impurity element and a donor impurity element is represented by III
In group III nitride crystals, Mg, Zn, Cd, Be, and other elements that can become acceptors by substituting with group III atoms to enter the lattice position and replace with nitrogen atoms and become donors by substituting with nitrogen atoms O (oxygen), Se, S, T
e, and other elements that can serve as donors are included in the constituent elements, and examples thereof include compounds having a bond such as Mg and O, Mg and Se, Zn and O, and Zn and Se.

For example, Zn or a compound having a bond between Mg and O (oxygen) includes Mg (C ₅ H ₇ O ₂ ) ₂ (magnesium bisacetylacetonate) and Mg (C ₁₁ H _19).
O ₂ ) ₂ (magnesium bisdipivaloyl methanate),
There are β-diketone compounds of acetylacetone and dipyrroylmethane such as Zn (C ₅ H ₇ O ₂ ) ₂ (bisacetylacetonate zinc) and Zn (C ₁₁ H ₁₉ O ₂ ) ₂ (bis dipivaloyl methanate zinc). .

In the manufacturing method of the first embodiment, G
a, a group III element material such as Al, In, and B, a nitrogen material, and the dopant material (compound having a bond between an acceptor impurity element and a donor impurity element) are transported to a heated substrate surface; A group III nitride semiconductor can be crystal-grown thereon to produce a p-type group III nitride semiconductor. Here, the acceptor impurity is 10 ¹⁹ cm ^−3.
To 10 ²⁰ cm ^-3 or so, donor impurities may be doped with an amount of about 1 / 10-1 / 2 of the amount of acceptor impurity. The crystal growth method is not particularly limited. Further, the group III raw material and the nitrogen raw material are not particularly limited. For example, in the MOCVD method, TMGa, DEGa, TMAl, TMIn,
TEB can be used, and NH ₃ is used as a nitrogen raw material.
Can be used.

According to the first embodiment, since a compound in which an acceptor impurity element and a donor impurity element are combined is used as a dopant raw material, a part of the donor impurity element in the dopant raw material is used as the acceptor impurity element. In the state of being bonded to the impurity element, it is taken into the group III nitride host crystal. Then, a pair of an acceptor and a donor is formed, and the electrostatic energy is stabilized. New acceptor impurities (Group II atoms) in stabilized Group III nitride crystals
When one atom is added, the position of the group III atom is stably substituted, a high concentration of acceptor impurities (group II atom) can be doped, and a three-atom complex of two acceptor atoms and one donor atom is formed. You. As a result, the acceptor level becomes shallow and a low-resistance p-type group III nitride semiconductor crystal can be manufactured.

Conventionally, since the acceptor impurity and the donor impurity were doped as separate dopant materials, it was difficult to form a three-atom complex. Since the base dopant is doped into the base crystal, a p-type group III nitride semiconductor crystal having lower resistance than before can be manufactured.

Second Embodiment According to a second embodiment of the present invention, there is provided a method of manufacturing a p-type group III nitride semiconductor according to the first embodiment of the present invention, wherein the acceptor impurity element and the donor In addition to a compound dopant having a bond of an impurity element, an acceptor impurity material is simultaneously doped.

According to the fabrication method of the second embodiment, during the crystal growth, a compound dopant material having a bond of a group III material, a nitrogen material, an acceptor impurity element and a donor impurity element and a compound dopant material such as Mg or Zn at the same time. The dopant raw material of the acceptor impurity is transported to the heated substrate surface, and a group III nitride semiconductor is crystal-grown on the substrate.
A group nitride semiconductor can be manufactured. Here, acceptor impurities 10 ¹⁹ cm ^-3 ~10 ²⁰ cm ^-3 or so,
The donor impurity is 1/1 of the amount of the acceptor impurity.
Doping is performed in an amount of about 0 to 1/2. In addition, Mg or Z
The dopant raw material of the acceptor impurity such as n is not particularly limited. For example, in the MOCVD method,
Cp ₂ Mg, (EtCp) ₂ Mg, and DEZn can be used.

According to the second embodiment, in addition to the compound dopant having the bond between the acceptor impurity element and the donor impurity element, the dopant material of the acceptor impurity is simultaneously doped. It is possible to precisely control the doping concentration and the amount ratio of the impurity. As a result, the triatomic complex dopant can be more efficiently formed in the host crystal at a high concentration, and a low-resistance p-type group III nitride semiconductor crystal can be manufactured.

The p-type group III nitride semiconductor manufactured by the manufacturing method according to the first or second embodiment described above contains 10 ¹⁹ cm ⁻³ to 10 ²⁰ cm ^{−3 in the} group III nitride semiconductor host crystal. About 1/10 to 1/2 of the acceptor impurity and about 1/10 to 1/2 of the acceptor impurity are doped to form a complex in which two acceptors and one donor are bonded. . The p-type group III nitride semiconductor crystal thus manufactured may be a single crystal or a polycrystal, and is not particularly limited.

As described above, p of the first or second embodiment is
A p-type group III nitride semiconductor manufactured by the method of manufacturing a type-III group nitride semiconductor has a high concentration of a three-atom complex dopant doped in a host crystal, and has a lower resistance than a conventional p-type group III nitride semiconductor. It becomes a nitride semiconductor.

Further, a semiconductor device having a semiconductor multilayer structure including a p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment can be formed. The p-type group III nitride semiconductor manufactured by the manufacturing method according to the first or second embodiment described above may be present in any part of the semiconductor multilayer structure constituting the semiconductor device,
There is no particular limitation. Further, the laminated structure may be a single crystal or a polycrystal, and is not particularly limited. Further, such a semiconductor device is a p-type semiconductor device manufactured by the manufacturing method of the first or second embodiment described above.
The form of the light emitting element, the light receiving element, the electronic device, and the like is not limited as long as it functions using the characteristics of the group III nitride semiconductor.

In this semiconductor device, a p-type group III nitride semiconductor layer having a low resistance (the first or second embodiment described above) is formed on a p-type group III nitride semiconductor layer which has conventionally been one of the causes of high element resistance. ), The element resistance is lower than that of the conventional group III nitride semiconductor device, and therefore, the operating voltage can be lower than that of the conventional device. .

Further, in the above semiconductor device, the p-type semiconductor device manufactured by the manufacturing method of the first or second embodiment described above is used.
An ohmic electrode can be formed on a group III nitride semiconductor. Such a semiconductor device functions by forming a p-side ohmic electrode on the p-type group III nitride semiconductor manufactured by the manufacturing method of the above-described first or second embodiment and injecting a current. If so, the form of the light emitting element, the light receiving element, the electronic device, etc. is not limited. Further, the p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment described above does not need to be the outermost surface of the stacked structure, and may be, for example, the lowermost layer. Further, the laminated structure may be a single crystal or a polycrystal, and is not particularly limited.

In this semiconductor device, an ohmic electrode is formed on a p-type group III nitride semiconductor having a high carrier concentration (p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment described above). Therefore, the contact resistivity of the p-side ohmic electrode is lower than that of the conventional one. Therefore, the contact resistance of the p-side ohmic electrode, which is one of the causes of the high operating voltage of the device using the group III nitride semiconductor, can be reduced, and the operating voltage is lower than that of the conventional device. Can be provided.

The semiconductor device described above can take the form of a light emitting element having a light emitting region sandwiched between a p-type semiconductor and an n-type semiconductor. That is, this light emitting element
It has a laminated structure in which a p-type semiconductor layer and an n-type semiconductor layer are laminated, and a part or all of the p-type semiconductor is a p-type semiconductor produced by the production method of the above-described first or second embodiment.
It is a group III nitride semiconductor layer. Then, the p-type manufactured by the manufacturing method of the first or second embodiment described above.
An ohmic electrode can be formed on a group III nitride semiconductor.

In such a light emitting element, the light emitting section is
It is located in a region between the n-type semiconductor and the p-type semiconductor. This light emitting portion has a homojunction (pn junction), a single heterojunction, a double heterojunction, a quantum well structure, a multiple quantum well structure, or any other structure as long as it emits light by current injection and carrier recombination. A simple structure is acceptable. The form of the light emitting element is not particularly limited as long as a current is injected into the light emitting region from the p-type semiconductor and the n-type semiconductor and light is emitted by recombination of carriers. That is, the light emitting element can take the form of a light emitting diode, a semiconductor laser, a super luminescent diode, or the like. Further, the laminated structure may be a single crystal or polycrystal structure.

Specifically, when the light emitting element is a semiconductor laser, the structure of the semiconductor laser is not particularly limited. That is, a semiconductor laser having a stacked structure of a p-type group III nitride semiconductor may be used as long as carriers are injected into the active layer and laser light is extracted to the outside. The structure may be as follows.

In such a light emitting device, a p-type III
Since a low-resistance p-type group III nitride semiconductor (a p-type group III nitride semiconductor manufactured by the manufacturing method of the above-described first or second embodiment) is used for the group-III nitride semiconductor layer,
The element resistance is lower than the conventional one, and therefore, the operating voltage is lower than the conventional one. In addition, since the element resistance is low, heat generation is small even at the time of a large current operation, generation and growth of defects due to heat generation are suppressed, and deterioration of the element is small. Therefore, high output operation is possible. Therefore, an operating voltage lower than that of a conventional group III nitride semiconductor light emitting device, and a high output, long life, and highly reliable light emitting device can be provided.

In the case where the light emitting element is a semiconductor laser, the p of the semiconductor multilayer structure constituting the semiconductor laser is
Any one of the type III group nitride semiconductor layers may be formed by using the p-type formed by the manufacturing method of the first or second embodiment described above.
By using a group III nitride semiconductor layer, device resistance can be reduced. Further, when the p-side ohmic electrode is formed on the p-type group III nitride semiconductor layer manufactured by the manufacturing method of the first or second embodiment described above, the contact resistance of the ohmic electrode can be reduced. . Therefore,
In the semiconductor laser of the present invention, the operating voltage can be made lower than that of the conventional one. Further, since the element resistance is low, heat generation is small even at the time of a large current operation, generation and growth of defects due to heat generation are suppressed, and deterioration of the laser element is small. Therefore, high output operation is possible. Therefore, it is possible to provide a semiconductor laser having a lower operating voltage than the conventional group III nitride semiconductor laser, and having high output, long life and high reliability.

In the above-described semiconductor laser, all of the p-type group III nitride semiconductor layers constituting the semiconductor laser are replaced with the p-type group III nitride semiconductor layer manufactured by the manufacturing method of the first or second embodiment. It can be a nitride semiconductor. That is, all the p-type IIs that constitute the semiconductor laser
The group I nitride semiconductor can be a p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment described above.

All the p-type IIIs constituting the semiconductor laser
In the case where the group III nitride semiconductor layer is a low-resistance p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment described above, the resistance of the element semiconductor layer portion and the p-side ohmic electrode Has low contact resistance. That is, the element resistance is low. Therefore, in this semiconductor laser, the operating voltage can be further reduced. Further, since the element resistance is low, heat generation is small even at the time of a large current operation, generation and growth of defects due to heat generation are suppressed, and deterioration of the laser element is small. Therefore, high output operation is possible. Therefore, it is possible to provide a semiconductor laser having a lower operating voltage than the conventional group III nitride semiconductor laser, and having high output, long life and high reliability.

[0042]

Embodiments of the present invention will be described below.

Example 1 In Example 1, a p-type group III nitride semiconductor was manufactured by the manufacturing method of the first embodiment. The fabricated p-type group III nitride semiconductor is p-type GaN.

FIG. 1 is a view showing a fabricated p-type group III nitride semiconductor (p-type GaN layer) of Example 1. Referring to FIG. 1, a low-temperature GaN buffer layer 11 and a p-type GaN layer 12 are sequentially formed on a sapphire substrate 10. Here, the p-type GaN layer 12 is made of p-type impurity Mg.
(Magnesium) and O (oxygen), respectively, Mg is 1
× 10 ²⁰ cm ^-3 approximately, O (oxygen) is doped about 3 × 10 ¹⁹ cm ^-3.

Next, a method of manufacturing the p-type group III nitride semiconductor (p-type GaN layer 12) of the first embodiment will be described. Example 1
The p-type GaN layer 12 can be manufactured by crystal growth by MOCVD. At this time, as the dopant _{material, Mg (C 5 H 7 O} 2) it can be used ₂ (magnesium bis acetylacetonate).

That is, first, the sapphire substrate 10 was set in a reaction tube, and heated at 1120 ° C. in a hydrogen gas to clean the surface of the substrate 10. Then, the temperature is set to 52
The temperature was lowered to 0 ° C., the growth atmosphere was changed to a mixed gas atmosphere of NH ₃ and nitrogen, and TMG was flowed to deposit a low-temperature GaN buffer layer 11.

Next, the temperature was raised to 1050 ° C., and TMG and Mg (C ₅ H ₇ O ₂ ) ₂ (bisacetylacetonate magnesium) were supplied using nitrogen as a carrier gas, and the p-type GaN layer 12 was laminated.

The p-type GaN layer 12 has a carrier concentration of 2 ×
At 10 ¹⁸ cm ^-3 or more, a p-type having lower resistance than the conventional one was exhibited. In the case where Mg and O (oxygen) are doped with different dopant materials, the carrier concentration is 2 × 10 ¹⁷
cm ^-3 .

Example 2 In Example 2, a p-type group III nitride semiconductor was manufactured by the manufacturing method of the second embodiment. The fabricated p-type group III nitride semiconductor is p-type GaN.

FIG. 2 is a view showing a manufactured p-type group III nitride semiconductor (p-type GaN layer) of Example 2. Referring to FIG. 2, a low-temperature GaN buffer layer 21 and a p-type GaN layer 22 are sequentially formed on a sapphire substrate 20. Here, the p-type GaN layer 22 is doped with p-type impurities Zn and O (oxygen), where Zn is doped at about 1 × 10 ²⁰ cm ⁻³ and O (oxygen) is doped at about 2 × 10 ¹⁹ cm ^−3. ing.

Next, a method of manufacturing the p-type group III nitride semiconductor (p-type GaN layer 22) of the second embodiment will be described. Example 2
The p-type GaN layer 22 can be manufactured by crystal growth by MOCVD. At this time, Zn (C ₅ H ₇ O ₂ ) ₂ (bisacetylacetonate zinc) and DEZn can be used as dopant raw materials.

That is, first, the sapphire substrate 20 was set in a reaction tube and heated in a hydrogen gas at 1120 ° C. to clean the surface of the substrate 20. Then, the temperature is set to 52
The temperature was lowered to 0 ° C., the growth atmosphere was changed to a mixed gas atmosphere of NH ₃ and nitrogen, TMG was flowed, and the low-temperature GaN buffer layer 21 was deposited.

Then, the temperature was raised to 1050 ° C., and TMG, Zn (C ₅ H ₇ O ₂ ) ₂ (bisacetylacetonate zinc) and DEZn were supplied using nitrogen as a carrier gas.
A p-type GaN layer 22 was stacked.

The p-type GaN layer 22 has a carrier concentration of 2 ×
At 10 ¹⁸ cm ^-3 or more, a p-type having lower resistance than the conventional one was exhibited. Note that Zn and O (oxygen) doped with different dopant materials without using Zn (C ₅ H ₇ O ₂ ) ₂ (bisacetylacetonate zinc) have a carrier concentration of 5 × 10 ¹⁶ cm. ^{Was -3} .

Example 3 Example 3 is a semiconductor device having a semiconductor laminated structure including a p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment. Specifically, the semiconductor device according to the third embodiment is configured as a light receiving / emitting element in which an edge emitting light emitting diode and an edge receiving light receiving photodiode are monolithically integrated.

FIGS. 3 and 4 are views showing a semiconductor device (light receiving / emitting element) according to the third embodiment. FIG. 3 is a cross-sectional view of the light emitting and receiving element in a plane perpendicular to the light emitting end face of the light emitting diode, and FIG. 4 is a cross sectional view of the light emitting diode in a plane parallel to the light emitting end face.

In the examples shown in FIGS. 3 and 4, the light emitting diode and the photodiode have a substantially rectangular parallelepiped shape, and a space is formed so that one light emitting end face of the light emitting diode faces the light receiving end face of the photodiode. It is formed so as to be separated from each other.

The light emitting diode and the photodiode have the same laminated structure. The laminated structure is such that an AlN low-temperature buffer layer 31, an n-type Al _0.03 Ga _0.97 N contact layer 32, an n-type Al _0.07 Ga _0.93 N cladding layer 33, an In _0.17 Ga _0.83 are formed on a sapphire substrate 30.
N active layer 34, p-type Al _0.07 Ga _0.93 N clad layer 3
5. The p-type GaN contact layer 36 is formed by sequentially laminating.

Here, the p-type Al _0.07 Ga _0.93 N cladding layer 35 and the p-type GaN contact layer 36 have Mg and O
(Oxygen) is doped.

The stacked structure of the light emitting diode and the photodiode is etched from the surface of the p-type GaN contact layer 36 to the n-type Al _0.03 Ga _0.97 N contact layer 32 to form the n-type Al _0.03 Ga _0.97 N contact layer 3.
The surface of No. 2 is exposed. On the p-type GaN contact layer 36 of the light emitting diode and the photodiode, Ni / A
A p-side ohmic electrode 38 made of u is formed.
In addition, the exposed n-type Al _0.03 Ga _0.97 N contact layer 3
2, an n-side ohmic electrode 39 made of Ti / Al
Are formed. Further, an insulating protective film 37 made of SiO ₂ is deposited on portions other than the ohmic electrode. Then, a wiring electrode 40 made of Ti / Al is formed on the insulating protection film 37. The wiring electrode 40 is electrically connected to the respective p-side ohmic electrodes 38 of the light emitting diode and the photodiode.

The side surfaces of the light emitting diode and the photodiode are formed substantially perpendicular to the substrate 30. The side faces of the light emitting diode and the photodiode that face each other via the groove become the light emitting end face 102 and the light receiving face 103, respectively. The end face of the light emitting diode opposite to the side face facing the photodiode is a light emitting end face 101 for emitting light to the outside.

Next, a method of manufacturing the integrated type light receiving / emitting element shown in FIGS. 3 and 4 will be described. The stacked structure of the integrated light emitting and receiving device shown in FIGS. 3 and 4 can be manufactured by crystal growth by MOCVD.

That is, first, the sapphire substrate 30 was set in a reaction tube and heated in a hydrogen gas at 1120 ° C. to clean the surface of the substrate 30. Then, the temperature is set to 52
The temperature was lowered to 0 ° C., the growth atmosphere was a mixed gas atmosphere of NH ₃ , nitrogen and hydrogen, TMA was flowed, and a low-temperature AlN buffer layer 31 was deposited.

Next, the temperature is raised to 1070 ° C., TMG, TMA, and SiH ₄ are supplied in accordance with the composition using hydrogen as a carrier gas, and the n-type Al _0.03 Ga _0.97 N contact layer 32 is formed to a thickness of 3 μm. , N-type Al _0.07 Ga _0.93
The N cladding layers 33 were sequentially laminated to a thickness of 0.5 μm.
Next, the supply of hydrogen gas was stopped, the atmosphere was changed to a mixed gas atmosphere of NH ₃ and nitrogen, the temperature was lowered to 810 ° C., TMG and TMI were supplied using hydrogen as a carrier gas, and
_{A 0.17} Ga _0.83 N active layer 34 was grown to a thickness of 50 nm. Next, the temperature was increased to 1070 ° C., and nitrogen was used as a carrier gas, and TMG, TMA, Mg (C ₅ H ₇ O ₂ ) ₂ ,
(EtCp) ₂ Mg is supplied according to the composition, and p-type Al
The thickness of the _0.07 Ga _0.93 N cladding layer 35 is set to 0.5 μm,
Further, the p-type GaN contact layer 36 was sequentially laminated to a thickness of 0.2 μm.

Next, a pattern in which two rectangular patterns each having a width of 30 μm and a length of 50 μm were arranged at a distance of 5 μm in the length direction and formed side by side was formed with a resist. Using this resist pattern as a mask, dry etching was performed to form a rectangular parallelepiped having a height of about 1.5 μm to become a light emitting diode and a photodiode, and the n-type Al _0.03 Ga _0.97 N contact layer 32 was exposed. Next, Si to be the insulating protective film 37
O ₂ was deposited to a thickness of about 0.5 μm on the surface of the laminated structure. Next, a p-side ohmic electrode 38 was formed.

The process for forming the p-side ohmic electrode 38 is as follows. That is, first, after forming a nuclei stripe pattern with a resist on the light emitting diode and the photodiode, the p-type GaN contact layer 36 on the ridge is exposed by etching the SiO ₂ film 37. Next, Ni / Au as a p-side ohmic electrode material was deposited. Thereafter, the wafer was immersed in an organic solvent to dissolve the resist and lift off the electrode material deposited on the resist, thereby forming a p-side ohmic electrode pattern on the light emitting diode and the photodiode. Thereafter, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to form a p-type GaN contact layer 36.
A p-side ohmic electrode 38 was formed thereon.

Next, an n-side ohmic electrode 39 and a wiring electrode 40 were formed. The steps for forming the n-side ohmic electrode 39 and the wiring electrode 40 are as follows. That is, first, n
Type Al _0.03 Ga _0.97 N SiO _{2 on} contact layer 32
After a nuclei stripe pattern having a width of about 100 μm is formed on the film 37 with a resist, the SiO ₂ film 37 is etched to expose the n-type Al _0.03 Ga _0.97 N contact layer 32. Next, the resist is removed, and a lift-off pattern of the wiring electrode 40 and the n-side electrode 39 is formed again with the resist. Next, Ti / Al as an n-side ohmic electrode and a wiring electrode material was deposited. Thereafter, the wafer was immersed in an organic solvent to dissolve the resist and lift off the electrode material deposited on the resist, thereby forming an n-side ohmic electrode and a wiring electrode pattern. Thereafter, heat treatment was performed at 450 ° C. in a nitrogen atmosphere to form an n-side ohmic electrode 39. Then
Dicing was performed to separate the integrated light emitting and receiving elements into chips.

The integrated light emitting and receiving device shown in FIGS. 3 and 4 operates by injecting a forward current into the light emitting diode and applying a reverse bias to the photodiode. That is,
When a bias is applied in the forward or reverse direction to the p-side ohmic electrode and the n-side ohmic electrode of each element,
The light emitting diode emits light from two light emitting end faces 101 and 102. Then, light emitted from the light emitting end face 102 facing the photodiode is incident on the light receiving surface 103 of the photodiode, and a photoelectromotive force corresponding to the intensity is generated in the photodiode, and is extracted to the outside as a photocurrent. By monitoring the photocurrent of the photodiode, the current injected into the light emitting diode can be adjusted to control the light output. When light was emitted by injecting a current into the light emitting diode, the peak wavelength of the light emission was about 412 nm.

Example 4 Example 4 is a semiconductor device having a semiconductor laminated structure including a p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment. Specifically, the semiconductor device of the fourth embodiment is configured as an edge emitting light emitting diode. FIG. 5 is a diagram illustrating a semiconductor device (edge-emitting light emitting diode) according to a fourth embodiment. In the example of FIG. 5, the light emitting diode has a substantially rectangular parallelepiped shape, and one side surface 200 of the light emitting diode is a light emitting end face.

Referring to FIG. 5, the light emitting diode of the fourth embodiment has an n-type Al _0.07 Ga
_0.93 N low temperature buffer layer 51, n-type Al _0.2 Ga _0.8 N clad layer 52, Al _0.07 Ga _0.93 N active layer 53, p-type A
It has a laminated structure in which a l _0.2 Ga _0.8 N clad layer 54 and a p-type GaN contact layer 55 are sequentially laminated.

Here, the p-type Al _0.2 Ga _0.8 N cladding layer 54 and the p-type GaN contact layer 55
n and O (oxygen) are added simultaneously.

A p-side ohmic electrode 56 made of Ni / Au is formed on the p-type GaN contact layer 55 of the light emitting diode. An n-side ohmic electrode 57 made of Ti / Al is formed on the back surface of the substrate 50 where the laminated structure is not formed. The side surface 200 of the light emitting diode is formed perpendicular to the substrate.

Next, a method for manufacturing the light emitting diode shown in FIG. 5 will be described. The stacked structure of the light emitting diode of FIG.
It can be manufactured by crystal growth by the VD method.

That is, first, the n-type GaN substrate 50 was set in a reaction tube and heated in an ammonia gas at 1120 ° C. to clean the surface of the substrate 50. Next, the temperature was lowered to 600 ° C., the atmosphere was changed to a mixed gas atmosphere of NH ₃ , nitrogen, and hydrogen, and TMA, TMG, and SiH ₄ gas as an n-type dopant gas were flowed, and n-type low-temperature Al _0.07 Ga
_{A 0.93} N buffer layer 51 was deposited.

Next, the temperature was raised to 1070 ° C. and TM
G, TMA and SiH ₄ as an n-type impurity gas are supplied according to the composition, and the n-type Al _0.2 Ga _0.8 N clad layer 5 is supplied.
2 and an Al _0.07 Ga _0.93 N active layer 53 were sequentially laminated to a thickness of 0.3 μm and a thickness of 0.05 μm. Next, instead of the n-type impurity raw material, Zn (C ₅ H ₇ O ₂ ) ₂ and, at the same time, DEZn are supplied according to the composition, and p-type A
l _0.2 Ga _0.8 N cladding layer 54 to a thickness of 0.3 μm,
Further, a p-type GaN contact layer 55 was sequentially laminated to a thickness of 0.2 μm. Next, Ni / Au as a p-side ohmic electrode material was deposited on the upper surface of the stacked structure. Thereafter, heat treatment was performed at 600 ° C. in a nitrogen atmosphere to form a p-side ohmic electrode 56 on the p-type GaN contact layer 55. Next, the back surface of the GaN substrate 50 was polished to a thickness of about 100 μm. Next, an n-side ohmic electrode material Ti
/ Al deposited and heat treated at 450 ° C. in a nitrogen atmosphere,
An n-side ohmic electrode 57 was formed. Next, the substrate was cleaved to form the emission end face 200 and perform chip separation.

The light emitting diode shown in FIG. 5 operates when a forward bias is applied to the p-side ohmic electrode 56 and the n-side ohmic electrode 57. That is, when a forward bias is applied to the p-side ohmic electrode 56 and the n-side ohmic electrode 57, light is emitted to the outside from the light emitting end face 200 which is one side surface of the light emitting diode. The peak wavelength of light emission of this light emitting diode was about 350 nm.

Example 5 Example 5 is a semiconductor device having a semiconductor laminated structure including a p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment. Specifically, the semiconductor device of the fifth embodiment is configured as a semiconductor laser.

FIG. 6 is a view showing a semiconductor device (semiconductor laser) according to the fifth embodiment. In the example of FIG. 6, the semiconductor laser includes an AlGaN low-temperature buffer layer 61, an n-type Al _0.03 Ga _0.97 N contact layer 62 on a sapphire substrate 60,
n-type Al _0.08 Ga _0.92 N clad layer 63, n-type GaN guide layer 64, In _0.15 Ga _0.85 N / In _0.02 Ga _0.98 N
Multiple quantum well active layer (2 pairs) 65, p-type Al _0.2 Ga
_0.8 N layer 66, p-type GaN guide layer 67, p-type Al _0.08
Ga _0.92 N cladding layer 68, p-type GaN contact layer 6
9 are sequentially laminated to form a laminated structure.

Here, p-type Al_0.2Ga_0.8N layer 66, p
-Type GaN guide layer 67, p-type Al_{0. 08}Ga_0.92N crush
Layer 68 and p-type GaN contact layer 69 include Mg and O
(Oxygen) is doped.

The above laminated structure has a p-type GaN capacitor.
N-type Al from the surface of the tact layer 69_{0. 03}Ga_0.97N contour
Is etched to the contact layer 62, and n-type Al_0.03Ga_0.97
The surface of N contact layer 62 is exposed. Exposed n
Type Al_0.03Ga_0.97On the N contact layer 62, Ti /
An n-side ohmic electrode 72 made of Al is formed.
You. Also, the p-type GaN contact layer 69 has a p-type
Al_0.08Ga_0.92Etching to the middle of N cladding layer 68
The current constriction ridge structure 400 is formed.
On the p-type GaN contact layer 69 on the outermost surface of the ridge 400
Formed a p-side ohmic electrode 71 made of Ni / Au
Have been. In addition, except for the electrode forming portion, the insulating protective film 70
And SiO_TwoIs deposited on the insulating protective film 70.
A wiring electrode 73 extended from the p-side electrode 71 is formed.
ing. And the laminated structure and the current constriction ridge structure
An optical resonator end face is formed vertically.

Next, a method of manufacturing the semiconductor laser shown in FIG. 6 will be described. The crystal growth of the laminated structure of the semiconductor laser of FIG. 6 was performed by the MOCVD method. That is, first, the sapphire substrate 60 is set in a reaction tube, and is placed in a hydrogen gas at 1120 ° C.
To clean the surface of the substrate 60. Next, the temperature was lowered to 520 ° C., the atmosphere was changed to a mixed gas atmosphere of NH ₃ , nitrogen and hydrogen, TMG and TMA were flowed, and a low-temperature AlGaN buffer layer 61 was deposited. Next, the temperature was raised to 1050 ° C., and hydrogen was used as a carrier gas, and TM was used.
G, TMI and SiH ₄ are supplied according to the composition, and n-type A
l _0.03 Ga _0.97 N contact layer 62 to a thickness of 2 μm,
Further, the n-type Al _0.08 Ga _0.92 N clad layer 63 is
μm and the n-type GaN guide layer 64 is 0.1 μm thick.
The layers were sequentially laminated to a thickness of μm. Next, the supply of hydrogen gas was stopped, the atmosphere was changed to a mixed gas atmosphere of NH ₃ and nitrogen, the temperature was lowered to 810 ° C., and TM was used as a carrier gas with hydrogen.
G, TMI and supply In _0.15 Ga _0.85 N / In _0.02 G
a _0.98 N multiple quantum well active layer 65 (two pairs) was grown.

Next, the growth atmosphere is a mixed gas atmosphere of NH ₃ , nitrogen and hydrogen, the temperature is raised to 1070 ° C., and TMG, TMA, Mg (C ₅ H ₇
O ₂ ) ₂ and (EtCp) ₂ Mg are supplied according to the composition.
The p-type Al _0.2 Ga _0.8 N layer 66 has a thickness of 20 nm, the p-type GaN guide layer 67 has a thickness of 0.1 μm, and the p-type Al _0.08 Ga _0.92 N cladding layer 68 has a thickness of 0.7 μm.
m and a p-type GaN contact layer 69 having a thickness of 0.1 mm.
The layers were sequentially laminated to a thickness of 2 μm.

Next, a stripe pattern having a width of 4 μm was formed at a pitch of 1 mm by using a resist. Using this resist pattern as a mask, a ridge 400 was formed by dry etching to a depth of about 0.7 μm. After removing the resist mask, the ridge 40 is further applied with resist.
A stripe pattern of 500 μm width covering 0 was repeatedly formed at a pitch of 1 mm. Using this resist pattern as a mask, dry etching was performed to a depth of about 1.5 μm to expose the n-type Al _0.03 Ga _0.97 N contact layer 62. Next, an SiO ₂ film serving as an insulating protective film 70 was deposited on the surface of the laminated structure to a thickness of about 0.5 μm.

Next, a p-side ohmic electrode 71 was formed. The process for forming the p-side ohmic electrode 71 is as follows. First, after forming a nuclei stripe pattern with a resist on the ridge 400, the SiO ₂ film 70 is etched to expose the p-type GaN contact layer 69 on the ridge 400. Next, the resist is removed, and a Nuki stripe pattern having a width of about 450 μm is formed again with the resist, and Ni / A, which is a p-side ohmic electrode material, is formed on the ridge 400.
u was deposited. Thereafter, the wafer was immersed in an organic solvent, the resist was dissolved, and the electrode material deposited on the resist was lifted off to form a p-side ohmic electrode pattern only on the laminated structure of the semiconductor laser. Thereafter, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to form a p-type GaN contact layer 69.
A p-side ohmic electrode 71 was formed thereon.

Next, an n-side ohmic electrode 72 and a wiring electrode 73 were formed. The steps of forming the n-side ohmic electrode 72 and the wiring electrode 73 are as follows. That is, first, n
Type Al _0.03 Ga _0.97 N SiO _{2 on} contact layer 62
After a nuclei stripe pattern having a width of about 100 μm is formed on the film 70 with a resist, the SiO ₂ film 70 is etched to expose the n-type Al _0.03 Ga _0.97 N contact layer 62. After removing the resist, the resist is applied again to form a lift-off electrode pattern on the p-side electrode and on the portion where the n-side ohmic electrode is to be formed. Next, an n-side ohmic electrode material and Ti / Al as a wiring electrode material are deposited, the wafer is immersed in an organic solvent, the resist is dissolved, and the electrode material deposited on the resist is lifted off to form an n-side ohmic electrode pattern. And a wiring electrode pattern were formed. Thereafter, heat treatment was performed at 450 ° C. in a nitrogen atmosphere to form an n-side ohmic electrode 72.

Next, the sapphire substrate 60 was polished thinly and divided so as to be substantially perpendicular to the ridge 400 to form an optical resonator end face.

The semiconductor laser shown in FIG.
When a current is injected in the forward direction, light is emitted, and when the current is further increased, laser oscillation occurs. The oscillation wavelength was about 409 nm.

Example 6 Example 6 is a semiconductor device having a semiconductor laminated structure including a p-type group III nitride semiconductor manufactured by the manufacturing method of the first or second embodiment. Specifically, the semiconductor device of the sixth embodiment is configured as a semiconductor laser. FIG.
14 is a perspective view of a semiconductor laser according to a sixth embodiment. FIG. 8 is a cross-sectional view taken along a plane perpendicular to the light emitting direction of the semiconductor laser of the sixth embodiment.

Referring to FIGS. 7 and 8, a semiconductor laser
Has a stacked structure 2000 on an n-type GaN substrate 120.
-Type AlGaN low-temperature buffer layer 121, n-type Al_0.03G
a_{0. 97}N high temperature buffer layer 122, Al_0.15Ga_0.85N
N-type consisting of a superlattice of layer 123a and GaN layer 123b
Clad layer 123, n-type GaN guide layer 124, In
_0.15Ga_0.85N / In_0.02Ga_0.98N multiple quantum well activity
Layer 125, p-type Al_0.2Ga_0.8N layer 126, p-type GaN
Guide layer 127, Al_0.15Ga_0.85N layer 128a and Ga
P-type cladding layer 12 composed of superlattice with N layer 128b
8. The p-type GaN contact layer 129 is sequentially stacked
Is formed.

Here, the p-type Al _0.2 Ga _0.8 N layer 126,
p-type GaN guide layer 127, p-type cladding layer 128, p-type
The type GaN contact layer 129 is doped with Zn and O (oxygen).

Then, the laminated structure 2000 is composed of p-type GaN
The current confinement ridge structure 900 is formed by etching from the surface of the contact layer 129 to the middle of the p-type cladding layer 128. And the p-type G on the outermost surface of the ridge 900
On the aN contact layer 129, a p of Ni / Au
A side ohmic electrode 131 is formed. In addition, an SiO ₂ film is deposited as the insulating protective film 130 except for the p-side electrode forming portion.

Then, the optical resonator end faces 901 and 902 are substantially perpendicular to the laminated structure 2000 and the current confinement ridge structure 900.
Are formed. On the back surface of the GaN substrate 120, an n-side ohmic electrode 132 made of Ti / Al is formed.

Next, a method of manufacturing the semiconductor laser shown in FIGS. 7 and 8 will be described. The crystal growth of the laminated structure 2000 of the semiconductor laser shown in FIGS. 7 and 8 was performed by the MOCVD method. That is, first, the n-type GaN substrate 120 is set in a reaction tube,
1120 ° C in a mixed gas of hydrogen, nitrogen and ammonia gas
To clean the surface of the substrate 120. Next, the temperature was lowered to 600 ° C., and in a mixed gas atmosphere of NH ₃ , nitrogen and hydrogen, TMA, TMG and SiH ₄ gas as an n-type dopant gas were flown to deposit an n-type low-temperature AlGaN buffer layer 121. Then, the temperature was set to 1070 ° C
To TMG, TMA, n using hydrogen as carrier gas
Supply SiH ₄ as the type impurity gas according to the composition,
n-type Al _0.03 Ga _0.97 N high-temperature buffer layer 122
m. Next, TMG, TMA, and SiH ₄ as an n-type impurity gas are supplied according to the composition, and Al
_An n-type clad layer 123 composed of a superlattice of a _0.15 Ga _0.85 N layer 123a and a GaN layer 123b was laminated to a thickness of about 0.6 μm. Here, the thickness of each layer is Al _0.15 Ga _0.85
The N layer 123a has a thickness of 7 nm, the GaN layer 123b has a thickness of 7 nm,
It grew for 43 cycles.

Next, the temperature was lowered to 1050 ° C.
The aN guide layer 124 was laminated to a thickness of 0.1 μm. Next, the supply of hydrogen gas was stopped, the atmosphere was changed to a mixed gas atmosphere of NH ₃ and nitrogen, the temperature was lowered to 810 ° C., TMG and TMI were supplied using hydrogen as a carrier gas, and In _0.15
Ga _0.85 N / In _0.02 Ga _0.98 N multiple quantum well active layer 1
Grew 25 (2 pairs). Then, the growth atmosphere was changed to NH
₃ and a mixed gas atmosphere of nitrogen and hydrogen.
℃, TMG, TMA, Zn (C ₅ H ₇ O ₂ ) ₂ , DE
Zn was supplied according to the composition, and the p-type Al _0.2 Ga _0.8 N layer 126 was sequentially laminated to a thickness of 20 nm, and the p-type GaN guide layer 127 was laminated to a thickness of 0.1 μm. Then A
An n-type cladding layer 128 comprising a superlattice of l _0.15 Ga _0.85 N layer 128a and GaN layer 128b was laminated to a thickness of about 0.6 μm. Here, the thickness of each layer is Al _0.15 Ga
_0.85 N layer 128a is 7 nm, GaN layer 128b is 7 nm
Thus, 43 cycles were grown. Next, a p-type GaN contact layer 129 was laminated to a thickness of 0.2 μm.

Next, a stripe pattern having a width of 4 μm was formed of a resist at a repetition pitch of 300 μm. Using this resist pattern as a mask, a ridge 900 was formed by dry etching to a depth of about 0.7 μm. After removing the resist mask, the S
An iO ₂ film was deposited to a thickness of about 0.5 μm on the surface of the laminated structure.

Next, a p-side ohmic electrode 131 was formed. The process for forming the p-side ohmic electrode 131 is as follows. That is, first, a nuclei stripe pattern is formed with a resist on the ridge 900, and then the SiO ₂ insulating protective film 130 is etched to form p-type GaN on the ridge.
The contact layer 129 is exposed. Next, the resist was removed, and Ni / Au as a p-side ohmic electrode material was deposited on the wafer surface. Then, in a nitrogen atmosphere, 60
Heat treatment at 0 ° C. to form a p-type GaN contact layer 129
A side ohmic electrode 131 was formed.

Next, after the back surface of the substrate 120 was polished to a thickness of about 100 μm, Ti / Al as an n-side ohmic electrode material was deposited. Then, in a nitrogen atmosphere, 450
C. to form an n-side ohmic electrode 132.
Next, the wafer on which the semiconductor laser structure was formed was cleaved so as to be substantially perpendicular to the ridge 900, and optical resonator end faces 901 and 902 were formed.

This semiconductor laser has electrodes 131 and 13
Light emission occurred when a current was injected in the forward direction into No. 2, and laser oscillation occurred when the current was further increased. Oscillation wavelength is about 403nm
Met.

[0099]

As described above, according to the first and second aspects of the present invention, there is provided a method of manufacturing a p-type group III nitride semiconductor including a complex of an acceptor impurity and a donor impurity. Since a p-type group III nitride semiconductor is manufactured by using a compound having a bond between an acceptor impurity element and a donor impurity element as a dopant material, a three-atom complex dopant is efficiently doped into a host crystal at a high concentration. As a result, a low-resistance p-type group III nitride semiconductor can be manufactured.

According to a third aspect of the present invention, there is provided a p-type group III nitride semiconductor manufactured by the method for manufacturing a p-type group III nitride semiconductor according to the first or second aspect. Therefore, it is possible to provide a low-resistance p-type group III nitride semiconductor in which a host crystal is doped with a triatomic complex dopant at a high concentration.

According to a fourth and fifth aspect of the present invention, there is provided a semiconductor device having a semiconductor laminated structure including the p-type group III nitride semiconductor according to the third aspect. Therefore, a semiconductor device having an operating voltage lower than that of a conventional group III nitride semiconductor device can be provided.

According to the invention described in claim 6 to claim 8, in the semiconductor device according to claim 4 or claim 5, the semiconductor device includes a light emitting device sandwiched between a p-type semiconductor and an n-type semiconductor. Since the light emitting device has the region, the operating voltage is lower than that of the conventional group III nitride semiconductor light emitting device, and a light emitting device having high output, long life, and high reliability can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a p-type group III nitride semiconductor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a p-type group III nitride semiconductor according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a diagram illustrating a semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a semiconductor device according to a sixth embodiment of the present invention.

[Explanation of symbols]

10, 20, 60 Sapphire substrate 11, 21 Low-temperature GaN buffer layer 12, 22 p-type GaN layer 31 AlN low-temperature buffer layer 32 n-type Al _0.03 Ga _0.97 N contact layer 33 n-type Al _0.07 Ga _0.93 N cladding layer 34 In _0.17 Ga _0.83 N active layer 35 p-type Al _0.07 Ga _0.93 N cladding layer 36, 129, 55, 69 p-type GaN contact layer 37, 70, 130 Insulating protective film 38, 56, 71, 131 p-side ohmic electrode 37, 57, 72 , 132 n-side ohmic electrode 40, 73 wiring electrode 50, 120 n-type GaN substrate 51 n-type Al _0.07 Ga _0.93 N low-temperature buffer layer 52 n-type Al _0.2 Ga _0.8 N cladding layer 53 Al _0.07 Ga _0.93 N active layer 54 p-type Al _0.2 Ga _0.8 N clad layer 61 AlGaN low temperature buffer layer 62 n-type Al _0.03 Ga _0.97 N contact layer 63 n-type Al _0.08 Ga _0.92 N cladding layer 64,124 n-type GaN guide layer 65,125 In _0.15 Ga _0.85 N / In _0.02 G
a _0.98 N multiple quantum well active layer 66, 126 p-type Al _0.2 Ga _0.8 N layer 67, 127 p-type GaN guide layer 68 p-type Al _0.08 Ga _0.92 N cladding layer 101, 102, 200 Light emitting end face 103 Light receiving face 121 n -Type AlGaN low-temperature buffer layer 122 n-type Al _0.03 Ga _0.97 N high-temperature buffer layer 123 n-type cladding layer made of super lattice 123a Al _0.15 Ga _0.85 N layer 123b GaN layer 128 p-type cladding layer made of super lattice 128a Al _0.15 Ga _0.85 N Layer 128b GaN layer 400,900 Current confinement ridge structure 901,902 Optical cavity facet 2000 Stacked structure of semiconductor laser

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F041 AA08 CA04 CA14 CA34 CA49 CA53 CA54 CA57 CA65 CA84 CB03 CB11 CB32 FF01 FF13 5F045 AA04 AB09 AB14 AB17 AC08 AC09 AC11 AC12 AC19 AD12 AD14 AF04 AF05 AF09 BB16 CA11 CA12 CA13 CB01 DA63 5F073 AA11 AA45 AA74 AA77 BA01 BA04 CA07 CB03 CB16 CB22 DA05 DA24 DA30 DA32 EA23

Claims (8)

[Claims] In a method for manufacturing a p-type group III nitride semiconductor including a complex of an acceptor impurity and a donor impurity, a compound having a bond between an acceptor impurity element and a donor impurity element is used as a dopant material. P
P-type I characterized by producing a type III nitride semiconductor
A method for manufacturing a group II nitride semiconductor. 2. The method for producing a p-type group III nitride semiconductor according to claim 1, wherein an acceptor impurity material is simultaneously doped with a compound dopant having a bond between an acceptor impurity element and a donor impurity element. p characterized by producing a p-type group III nitride semiconductor
A method for manufacturing a type III nitride semiconductor. 3. The p-type III according to claim 1 or claim 2.
A p-type group III nitride semiconductor manufactured by a method for manufacturing a group III nitride semiconductor. 4. A semiconductor device having a semiconductor multilayer structure including the p-type group III nitride semiconductor according to claim 3. 5. The semiconductor device according to claim 4, wherein an ohmic electrode is formed on said p-type group III nitride semiconductor. 6. The semiconductor device according to claim 4, wherein said semiconductor device is a light-emitting element having a light-emitting region sandwiched between a p-type semiconductor and an n-type semiconductor. . 7. The semiconductor device according to claim 6, wherein said light emitting element is a semiconductor laser. 8. The semiconductor device according to claim 7, wherein all the p-type group III nitride semiconductor layers constituting the semiconductor laser are formed of the p-type group III nitride semiconductor according to claim 3. A semiconductor device characterized by the above-mentioned.