JP2002351820A - Bus structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus structure which can achieve high speed action and reduce power consumption and is applicable to electronic equipment such as a computer and a semiconductor circuit such as an LSI. SOLUTION: A data bus is split into a master bus 11 which is connected with CPU 1, a memory 2, an external input/output circuit 3 or the like, has a high access frequency, and operates at a high speed, slave buses 12 to 14 which are connected with internal function blocks which operate only at necessary times, have low access frequencies, and works with low power consumption, and an interconnect bus 15 which connects slave buses each other. The master bus 11 and the slave buses 12 to 14 are connected by primary connecting circuits 21 to 23 which can arbitrarily be connected or cut off electrically. The slave buses 12 to 14 and the interconnect bus 15 are arbitrarily connected electrically or by secondary connecting circuit 31 to 33 which can arbitrarily be connected or cut off electrically. In addition, the adjustment processing of operation of each connecting circuit is performed by the adjustment circuit 10 and data transfer between each bus is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus structure capable of operating at high speed and reducing power consumption and applicable to semiconductor integrated circuits such as LSIs and electronic devices such as computers.

[0002]

2. Description of the Related Art A conventional bus structure capable of reducing power consumption and realizing high-speed data transfer is disclosed in
Japanese Unexamined Patent Publication No. 73258 discloses a technology related to a low power consumption bus structure and a control method thereof, a low power consumption bus structure synthesis system and a synthesis method thereof, and portable information devices. FIG.
FIG. 1 is a block diagram showing a conventional bus structure in which a plurality of functional blocks are connected. Note that the bus structure shown in FIG. 1 of the above publication has a configuration in which one bus is divided into a plurality of subsections and connection means are provided between the subsections. In FIG. 8, this configuration is modified. A plurality of slave buses are connected in a branch to the master bus, and a first
2 illustrates a configuration provided with connection means.

A conventional bus structure 81 has a structure in which a plurality of slave buses are connected to a master bus 11 in a branch shape. In FIG. 8, as an example, slave buses 12 to 14 are respectively connected to the master bus 11. 1 shows the configuration.
Between the master bus 11 and the slave buses 12 to 14,
Each has primary connection circuits 21 to 23 as first connection means. That is, the master bus 11 and the slave bus 12 are connected via the primary connection circuit 21, the master bus 11 and the slave bus 13 are connected via the primary connection circuit 22, and the master bus 11 and the slave bus 14 are connected via the primary connection circuit 23, respectively. ing.

The master bus 11 has a CPU 1 and a memory 2
And an external input / output circuit 3 are connected. The slave bus 12 has functional blocks 51 and 52, the slave bus 13 has functional blocks 53 and 54, and the slave bus 1 has functional blocks 53 and 54.
4 are connected to functional blocks 55 and 56, respectively. The external input / output circuit 3 can be connected to an external device (not shown).

The slave buses 12 to 14 and the functional blocks 51 to 56 are connected via input buffers 41a to 41f and output buffers 42a to 42f, respectively, which are function block connecting means. That is, the slave bus 12 and the functional block 51 are connected via the input buffer 41a and the output buffer 42a,
The output terminal of the input buffer 41a and the input terminal of the output buffer 42a are connected to the functional block 51. The slave bus 12 and the functional block 52 are connected via an input buffer 41b and an output buffer 42b. The functional block 52 is connected to an output terminal of the input buffer 41b and an input terminal of the output buffer 42b. I have. The slave bus 13 and the functional block 53
The function block 53 is connected via an input buffer 41c and an output buffer 42c.
The output terminal 1c and the input terminal of the output buffer 42c are connected. Slave bus 13 and functional block 54
Are the input buffer 41d and the output buffer 42d.
The output terminal of the input buffer 41d and the input terminal of the output buffer 42d are connected to the functional block 54. The slave bus 14 and the functional block 55 are connected via an input buffer 41e and an output buffer 42e, and the functional block 55 has an output terminal of the input buffer 41e and an output buffer 42e.
Input terminals are connected. The slave bus 14 and the function block 56 are connected via an input buffer 41f and an output buffer 42f, and the function block 56 is connected to an output terminal of the input buffer 41f and an input terminal of the output buffer 42f. I have.

[0006] The primary connection circuits 21 to 23 are connected to the arbitration circuit 10.
The connection and disconnection between the master bus 11 and the slave buses 12 to 14 are performed according to control signals transmitted from the control buses 201 to 203 via the control lines 201 to 203. When data is transferred from the master bus 11 to the slave buses 12 to 14, or when data is transferred from the slave buses 12 to 14 to the master bus 11, the data transfer direction can be switched to any one direction.

[0007] The control lines 101 to 106 are for sending control signals for enabling the respective functional blocks 51 to 56 to drive the respective buses. Control lines 101-
106 is connected to the control terminals of the output buffers 42a to 42f, respectively. For example, the output buffer 42a
When the control signal input to the control terminal is turned on, the output signal of the functional block 51 is output to the slave bus 12. Also, the other output buffers 42b to 42f perform the same operation when the control signal is turned on.

The arbitration circuit 10 serving as a control means includes a control line 1
01 to 106, to the output buffers 42a to 42f, and to the primary connection circuit 2 through control lines 201 to 203.
1 to 23. The arbitration circuit 10 includes output buffers 42a to 42f and primary connection circuits 21 to 23.
Can be controlled. Further, the arbitration circuit 10
Controls the operation of each of the primary connection circuits 21 to 23 so that the plurality of slave buses 12 to 14 are not connected to the master bus 11 at the same time.

For example, when transferring the data output from the functional block 51 to the CPU 1, the arbitration circuit 10 transmits a control signal via the control lines 101 and 201,
While the output buffer 42a is turned on, the primary connection circuit 21 is switched to a setting that enables data transfer from the slave bus 12 to the master bus 11, and the function block 51
To transfer data to the CPU 1. At this time, the primary connection circuit and the output buffer other than those described above are all turned off, and control is performed so that data transfer with other functional blocks is not performed.

In order to transfer data from the function block 51 to the function block 53, the arbitration circuit 10 first transmits a control signal from the control lines 101 and 201 to turn on the output buffer 42a, The connection circuit 21 is switched to a setting that allows data transfer from the slave bus 12 to the master bus 11, and data is transferred from the functional block 51 to the master bus 11 via the slave bus 12. Thereafter, the arbitration circuit 10 waits for a sufficient time for the signal value on the master bus 11 to stabilize, and the control line 201,
A control signal is transmitted from the connection bus 202 to switch between the connection circuit 21 and the connection circuit 22, and the master bus 11 is connected in the same procedure.
Is connected to the slave bus 13, data is transferred to the slave bus 13, and input to the functional block 53.

[0011]

In the conventional bus structure,
Large-scale blocks such as the CPU 1 and the memory 2 are connected, and the wiring length of the bus becomes longer to surround these large-scale blocks, and all parasitic capacitances on the bus are charged and discharged, thereby increasing power consumption. There is a problem of doing. Also,
Since the master bus 11 is connected to frequently accessed blocks such as the CPU 1 and the memory 2, the frequency of charging and discharging also increases, and the power consumption further increases.

Further, in the bus structure 81, the CPU 1 is always operated while the CPU 1 or the memory 2 is operating or when an interrupt process occurs. Therefore, CP
Since U1 occupies the master bus 11, the master bus 11
Can operate at high speed, but there is a problem that data transfer between slave buses is delayed. In addition, in order to transfer data between slave buses, data must be transmitted via the master bus 11 without fail. Therefore, there is a problem in that data transfer between devices connected to the master bus is waited while data is transferred between slave buses.

There is also a problem that the transfer delay increases due to an increase in the parasitic capacitance accompanying an increase in the wiring length, and the throughput of the entire circuit decreases. In recent electronic circuits that require high-speed processing, the data transfer speed affects the performance of the entire circuit. Therefore, speeding up data transfer is a very important issue.

Therefore, the present invention can solve the above-mentioned problem by operating at high speed and reducing power consumption.
It is an object of the present invention to provide a bus structure applicable to a semiconductor integrated circuit such as an LSI or an electronic device such as a computer.

[0015]

The present invention has the following arrangement as means for solving the above-mentioned problems.

(1) A master bus, a plurality of slave buses, a plurality of first connection means for connecting and disconnecting between the master bus and the slave bus, and a control means for controlling the operation of the first connection means; A bus structure comprising: an interconnect bus; and a plurality of second connecting means for connecting and disconnecting between the interconnect bus and the plurality of slave buses. The operation is controlled.

In this configuration, a master bus, a plurality of slave buses, a plurality of first connection means for connecting and disconnecting between the master bus and the slave bus, a control means,
An interconnect bus, and a plurality of second connecting means for connecting and disconnecting between the interconnect bus and the plurality of slave buses, wherein the control means controls the operations of the first connecting means and the second connecting means. Therefore, when performing data transfer between various functional blocks connected to the bus, for example, only the bus to which the functional blocks are connected is driven and the other buses are electrically disconnected, so that the bus wiring distance should be reduced. As a result, it is possible to prevent a reduction in data transfer speed due to the parasitic capacitance of the wiring and to reduce power consumption.

(2) At least one of a CPU, a memory, an external input / output circuit, and an internal function block is connected to the master bus, and one or a plurality of internal function blocks are respectively connected to the plurality of slave buses. Are connected.

In this configuration, at least one of a CPU, a memory, an external input / output circuit, and an internal function block is connected to a master bus, and one or more internal function blocks are connected to a plurality of slave buses. ing. Therefore, when performing data transfer between a plurality of functional blocks connected to different slave buses, since data transfer can be performed via the interconnect bus, the access frequency of the CPU, memory, or the like is low. The data transfer between the various functional blocks can be performed irrespective of the operation of the functional blocks without occupying the master bus connecting the high blocks. Further, even when it becomes necessary to operate the CPU by an operation such as an interrupt, the other slave buses can perform high-speed processing without interrupting data transfer.

(3) The first connecting means is capable of switching between data transfer from the master bus to the slave bus and data transfer from the slave bus to the master bus. Data transfer from the slave bus to the interconnect bus and data transfer from the interconnect bus to the slave bus can be switched.

In this configuration, the first connection means can switch between data transfer from the master bus to the slave bus and data transfer from the slave bus to the master bus, and can perform data transfer from the slave bus to the interconnect bus. And the data transfer from the interconnect bus to the slave bus can be switched by the second connection means. Therefore, it is possible to reliably transfer data between functional blocks connected to the slave bus or between, for example, a CPU connected to the master bus and a functional block connected to the slave bus.

(4) When data transfer is performed between any one of the plurality of slave buses and the master bus, the control means connects only the first connection means between the slave bus and the master bus. And setting the second connection means between the slave bus for performing the data transfer and the interconnect bus to a cutoff state.

In this configuration, when performing data transfer between any one of the plurality of slave buses and the master bus, the control means sets only the first connection means between the slave bus and the master bus to a connected state. Then, the second connection means between the slave bus performing the data transfer and the interconnect bus is turned off. Therefore, it is possible to reliably transfer data between the slave bus and the master bus without erroneously transferring data from the slave bus to another slave bus.

(5) The control means, when performing data transfer between any two of the plurality of slave buses,
Wherein only the second connection means between the two slave buses and the interconnect bus is connected, and the first connection means between the slave bus performing the data transfer and the master bus is cut off. I do.

In this configuration, when data transfer is performed between any two of the plurality of slave buses, the control means connects only the second connection means between the two slave buses and the interconnect bus. Then, the first connection means between the slave bus and the master bus for performing the data transfer is turned off. Therefore, it is possible to reliably transfer data between the two slave buses without erroneously transferring data from the slave bus to the master bus.

(6) When the control means performs data transfer in the master bus, the control means sets all the first connection means to a cutoff state.

In this configuration, when data transfer is performed within the master bus, the control means sets all the first connection means in a cutoff state. Therefore, data can be transferred between, for example, a CPU and a memory connected to the master bus without erroneously transferring data to the slave bus.

(7) The control means, when performing data transfer in one of the plurality of slave buses, the first connection means between the slave bus and the master bus, and the slave bus And disconnecting the second connection means between the interconnect buses.

In this configuration, when data transfer is performed in the slave bus, the control means sets the first connection means and the second connection means connected to the slave bus to a cutoff state. Therefore, data can be transferred between the functional blocks connected to the slave bus without erroneously transferring data from the slave bus to another slave bus or the master bus.

(8) A bus structure according to any one of (1) to (7) is provided.

In this configuration, the semiconductor integrated circuit includes:
The bus structure according to any one of (1) to (7) is provided. Therefore, when performing data transfer between, for example, various functional blocks connected to the bus, it is necessary to shorten the bus wiring distance because only the bus connected to the functional block is driven and the other buses are electrically disconnected. As a result, it is possible to prevent a reduction in data transfer speed due to the parasitic capacitance of the wiring and to reduce power consumption. When data is transferred between a plurality of functional blocks connected to different slave buses, the data can be transferred via the interconnect bus. It does not occupy the master bus connected to the high block. For this reason, in data transfer between various functional blocks, processing can be performed regardless of the operation of the functional blocks. Further, even when it becomes necessary to operate the CPU by an operation such as an interrupt, the other slave buses can perform high-speed processing without interrupting data transfer.

(9) A bus structure according to any one of (1) to (7) or a semiconductor integrated circuit according to (8).

In this configuration, the electronic equipment is composed of (1) to
The bus structure described in any of (7) or the semiconductor integrated circuit described in (8) is mounted. Therefore, when performing data transfer between, for example, various functional blocks connected to the bus, it is necessary to shorten the bus wiring distance because only the bus connected to the functional block is driven and the other buses are electrically disconnected. As a result, it is possible to prevent a reduction in data transfer speed due to the parasitic capacitance of the wiring and to reduce power consumption. In addition, when performing data transfer between a plurality of functional blocks connected to different slave buses, since data transfer can be performed via the interconnect bus, a master bus connected to frequently accessed blocks is used. No occupancy. For this reason, in data transfer between various functional blocks, processing can be performed regardless of the operation of the functional blocks. Further, even when it becomes necessary to operate the CPU by an operation such as an interrupt, the other slave buses can perform high-speed processing without interrupting data transfer.

[0034]

FIG. 1 is a block diagram showing a bus structure according to an embodiment of the present invention. Here, in FIG. 1, the same portions as those in the configuration shown in FIG. 8 are denoted by the same reference numerals. The bus structure 71 shown in FIG. 1 connects one ends of the secondary connection circuits 31 to 33 to the open ends of the slave buses 12 to 14 of the bus structure 81 shown in FIG. Interconnect bus 1 at each of the other ends
5 is connected, and the arbitration circuit 10 can control the connection and disconnection operations of the secondary connection circuits 31 to 33.

Hereinafter, the bus structure 71 will be described in detail. The bus structure 71 is a structure in which a plurality of slave buses are connected to the master bus 11 in a branch shape, and each slave bus is connected by an interconnect bus. In FIG. 1, as an example, a master bus 11 is connected to one end of each of the slave buses 12 to 14.
The other end of 14 has an interconnect bus 15 connected thereto. Primary connection circuits 21 to 23 as first connection means are provided between the master bus 11 and the slave buses 12 to 14, respectively. That is, the master bus 11 and the slave bus 12 are connected to the primary connection circuit 21.
, The master bus 11 and the slave bus 13 are connected via a primary connection circuit 22, and the master bus 11 and the slave bus 14 are connected via a primary connection circuit 23.

Further, secondary connection circuits 31 to 33 as second connection means are provided between the interconnect bus 11 and the slave buses 12 to 14, respectively. That is, the interconnect bus 15 and the slave bus 12 are connected via the secondary connection circuit 31, the interconnect bus 15 and the slave bus 13 are connected via the secondary connection circuit 32, and the interconnect bus 15 and the slave bus 14 are connected via the secondary connection circuit. Each is connected via a circuit 33.

The master bus 11 has a CPU 1 and a memory 2
And an external input / output circuit 3 are connected. The slave bus 12 has functional blocks 51 and 52, the slave bus 13 has functional blocks 53 and 54, and the slave bus 1 has functional blocks 53 and 54.
4 are connected to functional blocks 55 and 56, respectively. The external input / output circuit 3 can be connected to an external device (not shown).

The bus configuration of the present invention is not limited to the above configuration, and the master bus 11 is configured by connecting at least one of a CPU, a memory, an external input / output circuit, and a functional block. It may be. The slave buses 12 to 14 may have a configuration in which one or more functional blocks are connected. Further, one or more functional blocks may be connected to the interconnect bus 15.

Each of the slave buses 12 to 14 and each of the functional blocks 51 to 56 are connected to input buffers 41 a to 4
1f and output buffer 4 as a function block connecting means
They are connected via 2a to 42f. That is, the slave bus 12 and the function block 51 are connected via the input buffer 41a and the output buffer 42a, and the function block 51 is connected to the output terminal of the input buffer 41a and the input terminal of the output buffer 42a. Have been. The slave bus 12 and the function block 52 are connected via an input buffer 41b and an output buffer 42b, and the function block 52 is connected to an output terminal of the input buffer 41b and an input terminal of the output buffer 42b. I have. The slave bus 13 and the functional block 53
The function block 53 is connected via an input buffer 41c and an output buffer 42c.
The output terminal 1c and the input terminal of the output buffer 42c are connected. Slave bus 13 and functional block 54
Are the input buffer 41d and the output buffer 42d.
The output terminal of the input buffer 41d and the input terminal of the output buffer 42d are connected to the functional block 54. The slave bus 14 and the functional block 55 are connected via an input buffer 41e and an output buffer 42e, and the functional block 55 has an output terminal of the input buffer 41e and an output buffer 42e.
Input terminals are connected. The slave bus 14 and the function block 56 are connected via an input buffer 41f and an output buffer 42f, and the function block 56 is connected to an output terminal of the input buffer 41f and an input terminal of the output buffer 42f. I have.

The primary connection circuits 21 to 23 include the arbitration circuit 10
The connection and disconnection between the master bus 11 and the slave buses 12 to 14 are performed according to control signals transmitted from the control buses 201 to 203 via the control lines 201 to 203. When data is transferred from the master bus 11 to the slave buses 12 to 14, or when data is transferred from the slave buses 12 to 14 to the master bus 11, the data transfer direction can be switched to any one direction.

The secondary connection circuits 31 to 33 include the arbitration circuit 10
In response to the control signals transmitted from the control buses 301 to 303 via the interconnect bus 15 and the slave bus 12
To 14 are connected and disconnected. Also, slave bus 1
When performing data transfer between the interconnect buses 2 to 14 or between any of the slave buses 12 to 14 and the interconnect bus 15, the direction of data transfer from the slave bus to the interconnect bus, and from the interconnect bus to the slave bus And the data transfer direction.

The control lines 101 to 106 are for sending control signals for enabling the respective functional blocks 51 to 56 to drive the respective buses. Control lines 101-
106 is connected to the control terminals of the output buffers 42a to 42f, respectively. For example, the output buffer 42a
When the control signal input to the control terminal is turned on, the output signal of the functional block 51 is output to the slave bus 12. Also, the other output buffers 42b to 42f perform the same operation when the control signal is turned on.

The arbitration circuit 10 serving as a control means includes a control line 1
01 to 106, to the output buffers 42a to 42f, and to the primary connection circuit 2 through control lines 201 to 203.
1 to 23 and connected to secondary connection circuits 31 to 33 via control lines 301 to 303. The arbitration circuit 10 can control the operations of the output buffers 42a to 42f, the primary connection circuits 21 to 23, and the secondary connection circuits 21 to 23.

The arbitration circuit 10 prevents data conflict,
In order to minimize the utilization rate of the master bus 11, the operation of each connection circuit is controlled so that the slave buses 12 to 14 are not simultaneously connected to the master bus 11 or the interconnect bus 15.

First, the arbitration circuit 10 controls the slave bus 1
When data transfer is performed between any one of 2 to 14 and the master bus 11, only the first connection circuit between the slave bus performing data transfer and the master bus 11 is connected, and the slave bus performing data transfer is performed. And the second connection circuit between the interconnect buses 15 is cut off. For example, data output from the functional block 51 connected to the slave bus 12 is
In order to transfer data to the CPU 1 connected to the output buffer 42 a and the primary connection circuit 21, data is transferred in a direction from the slave bus 12 to the master bus 11.
A control signal transmitted from the arbitration circuit 10 via the control lines 101 and 201 is turned on. Then, from the functional block 51 via the primary connection circuit 21 and the master bus 11, the CP
Transfer data to U1. At this time, the output buffer 42,
The primary connection circuit other than the primary connection circuit 21 and the secondary connection circuit 31 are all turned off, and control is performed so as not to conflict with data output from other functional blocks.

Second, the arbitration circuit 10 controls the slave bus 1
When performing data transfer between any two of 2 to 14,
Two selected slave buses and interconnect bus 1
5 and only the second connection circuit is connected.
Control is performed such that the first connection circuit between the slave bus and the master bus 11 that perform data transfer is cut off. For example, in order to transfer data from the function block 51 connected to the slave bus 12 to the function block 53 connected to the slave bus 13, the arbitration circuit 10
Similarly, control signals are output from 1, 301 and 302 to turn on the output buffer 42a and the secondary connection circuits 31 and 32, and transfer data from the slave bus 12 to the slave bus 13 via the interconnect bus 15. At this time, the secondary connection circuits other than the output buffer 42a and the secondary connection circuits 31 and 32, and the primary connection circuits 21 and 22 are all turned off, and control is performed so as not to compete with data output from other functional blocks.

It should be noted that as described above, the interconnect bus 1
When connecting the two slave buses via 5, the secondary connection circuit 31 and the secondary connection circuit 32 are simultaneously turned on,
Slave buses 12 and 13 and interconnect bus 15
By simultaneously connecting the three buses, data may be transferred from one functional block 51 to a plurality of functional blocks 52, 53, 54.

Also, as described above, the interconnect bus 1
In the case where all the slave buses are connected via the bus 5, the secondary connection circuits 31 to 33 are turned on at the same time, and the slave buses 12 to 14 and the interconnect bus 15 are connected at the same time, thereby forming one bus. Data may be transferred from the function block 51 to all the other function blocks 52 to 56.

Third, the arbitration circuit 10 includes a master bus 11
In the case where data transfer is performed within the network, control is performed so that all of the first connection units are in a cutoff state. For example, the arbitration circuit 10
When data transfer is performed between the CPU 1 and the memory 2, the primary connection circuits 21 to 23 are all turned off, and control is performed so as not to conflict with data output from other functional blocks.

Fourth, the arbitration circuit 10 controls the slave bus 1
When data transfer is performed in one of the slave buses 2 to 14, the first connection means between the selected slave bus and the master bus 11 and the second connection means between the selected slave bus and the interconnect bus 15 Control is performed so as to be in the cutoff state. For example, when the arbitration circuit 10 performs data transfer from the function block 51, which is a function block connected to the slave bus 12, to the function block 52,
While the primary connection circuit 21 and the secondary connection circuit 31 connected to both ends of the slave bus 12 are turned off, only the output buffer 42a is turned on without turning on the output buffer 42b, and data transfer between the other buses is performed. Control so that no conflict occurs.

As described above, in the bus structure of the present invention, since the arbitration circuit 10 as the control means operates as described above, it is possible to simultaneously perform data transfer between different buses. FIG. 2 is a block diagram showing a bus structure for performing data transfer between different buses. In the bus structure shown in FIG. 2, the arbitration circuit 10, the input buffers 41a to 41a
The illustration of 1f and the output buffers 42a to 42f is omitted.

As shown in FIG. 2A, by turning off the primary connection circuits 21 to 23 and the secondary connection circuits 31 to 33, the buses are separated from each other.
In the master bus 11, between the CPU 1 and the memory 2, and in the slave bus 12, the function blocks 51 and 5
2, the data transfer can be performed between the functional blocks 53 and 54 on the slave bus 13 and between the functional blocks 55 and 56 on the slave bus 14.

Further, as shown in FIG. 2B, by turning off all the primary connection circuits 21 to 23 and the secondary connection circuit 33 and turning on the secondary connection circuits 31 and 32, the slave bus is turned off. 12, the interconnect bus 15 and the slave bus 13 are connected and the other buses are separated from each other.
Between the slave bus 12 and the slave bus 13, between the functional blocks 52 and 54, and between the slave bus 14 and the functional blocks 55 and 5
6, data transfer can be performed.

Further, as shown in FIG. 2C, the primary connection circuits 22, 23 and the secondary connection circuit 31 are all turned off, and the primary connection circuit 21, and the secondary connection circuits 32, 33 are turned on. . Thereby, the master bus 11 and the slave bus 12, and the slave bus 13, the interconnect bus 15, and the slave bus 14 are connected.
Data transfer can be performed between U1 and the functional block 51, between the slave bus 13 and the slave bus 14, and between the functional block 54 and the functional block 56, respectively.

As described above, according to the present invention, the connection with other buses other than within the bus for data transfer or between buses is cut off, so that the parasitic capacitance of the bus can be apparently reduced, thereby reducing power consumption. Can be reduced. Also,
In addition, even when the master bus is used, data can be transferred between slave buses using the interconnect bus.

Next, specific circuit configurations of the primary connection circuit and the secondary connection circuit will be described. FIG. 3 is a circuit diagram showing a circuit configuration of the primary connection circuit. For the sake of simplicity, FIG. 3 illustrates the configuration of the primary connection circuit 21, but other primary connection circuits 22 and 23 and a secondary connection circuit 31
To 33 have the same configuration. As shown in FIG. 3A, the primary connection circuit 21 is an example of a connection circuit that can input signals from two control terminals and perform bidirectional control independently. The primary connection circuit 21 has a configuration including tri-state buffers 61a and 62a. The input terminal of the tristate buffer 61a is connected to a terminal on the master bus 11 side, which is one input / output terminal of the primary connection circuit. The output terminal is connected to a terminal on the slave bus 12 side, which is the other input / output terminal of the primary connection circuit 21. Further, the control terminal is connected to the control signal input terminal 201-1 of the primary connection circuit 21. on the other hand,
The tristate buffer 62a has an input terminal connected to the slave bus 12 which is the other input / output terminal of the primary connection circuit 21.
Connected to the side terminal. The output terminal is connected to a terminal on the master bus 11 side, which is one input / output terminal of the primary connection circuit 21. Further, the control terminal is connected to the control signal input terminal 201-2 of the primary connection circuit 21.

When the signal input to the control terminal 201-1 is turned on, the tristate buffer 61a is turned on, data is transferred from the master bus 11 to the slave bus 12, and when the control signal 201-1 is turned off. Stops data transfer and outputs high impedance value. on the other hand,
When the signal input to the control terminal 201-2 is turned on,
When the tri-state buffer 62a is turned on, data is transferred from the slave bus 12 to the master bus 11, and when the control signal 201-2 is turned off, the data transfer is stopped and a high impedance value is output. Control signal 201-1
, And both are turned off at the same time, no data transfer is performed in either direction. It should be noted that if both the control signals 201-1 and 201-2 are turned on at the same time, a data conflict occurs, and thus such control is not performed.

The primary connection circuit 21 may have a configuration as shown in FIG. As shown in FIG. 3B, the primary connection circuit 21 can input a signal from one control terminal and independently perform bidirectional control. Primary connection circuit 21 includes tristate buffers 61b, 6
2b and an inverter 63. That is, the input terminal of the tristate buffer 61b is connected to a terminal on the master bus 11 side, which is one input / output terminal of the primary connection circuit 21. The output terminal is a switch 6
4 is connected to the other input / output terminal of the primary connection circuit 21 on the slave bus 12 side. further,
The control terminal is the control signal input terminal 20 of the primary connection circuit 21
1 connected. On the other hand, the tri-state buffer 6
2b, an input terminal is connected to a terminal on the slave bus 12 side, which is the other input / output terminal of the primary connection circuit 21. The output terminal is connected to a terminal on the master bus 11 side, which is one input / output terminal of the primary connection circuit 21.
Further, the control terminal is connected to the output terminal of the inverter 63 whose input terminal is connected to the control signal input terminal 201 of the primary connection circuit 21.

When the control signal 201 is turned on, the tristate buffer 61b is turned on and the tristate buffer 62b is turned off, and data transfer from the master bus 11 to the slave bus 12 is performed. When the control signal 201 is turned off, the tri-state buffer 61a is turned off and the tri-state buffer 62a is turned on, and data transfer from the slave bus 12 to the master bus 11 is performed.

When the connection between the master bus 11 and the slave bus 12 is cut off by using the connection circuit shown in FIG. 3B, a configuration in which these two circuits are connected in series may be used. Further, the configuration of the primary connection circuit and the secondary connection circuit is not limited to the configuration shown in FIG. 3, but may be another configuration.

FIG. 4 is a table showing an example of each control signal when data is transferred from the CPU 1 to the functional block 51 when the connection circuit shown in FIG. 3B is used. As shown in FIG. 4, the control signal 10 output from the arbitration circuit 10
1 to 106 off, control signal 201 on, control signal 2
By turning off 02 and 203 and turning off the control signals 301 to 306, data can be transferred from the CPU 1 to the functional block 51.

FIG. 5 is a table showing an example of each control signal when data is transferred from the functional block 51 to the CPU 1 when FIG. 3B is used. As shown in FIG. 5, the control signal 101 is turned on, the control signals 102 to 106 are turned off,
By turning on the control signal 201, turning off the control signals 202 to 203, and turning off the control signals 301 to 306, data can be transferred from the functional block 51 to the CPU 1.

FIG. 6 is a table showing an example of each control signal when data is transferred from the function block 51 to the function block 52 when FIG. 3B is used. As shown in FIG. 6, the control signal 101 is turned on, and the control signals 102 to 106 are turned on.
Off, control signals 201-203 off, control signal 30
By turning off 1 to 303, data can be transferred from the functional block 51 to the functional block 52.

FIG. 7 is a table showing an example of each control signal when data is transferred from the function block 51 to the function block 53 when FIG. 3B is used. As shown in FIG. 7, the control signal 101 is turned on, and the control signals 102 to 106 are turned on.
Off, control signals 201-203 off, control signal 30
By turning on the signals 1 and 302 and turning off the control signal 303, data can be transferred from the functional block 51 to the functional block 53.

In the bus structure 71 shown in FIG. 1, only one line is displayed for each bus, and only one control signal for the primary connection circuit and the secondary connection circuit is described. In the case of a configuration that performs bidirectional data transfer, bidirectional data transfer may be performed using two buses. Further, a configuration including a plurality of bus lines and control signals so that data transfer of a plurality of bits can be individually controlled may be employed.

In the bus structure 71 shown in FIG. 1, only the output buffer can be turned on / off.
However, the present invention is not limited to this. For example, a configuration in which the input buffer can be turned on / off, and a configuration in which the operation control is performed by an arbitration circuit serving as control means may be adopted.

[0067]

According to the present invention, the following effects can be obtained.

(1) A master bus, a plurality of slave buses, a plurality of first connection means for connecting and disconnecting between the master bus and the slave bus, a control means, an interconnect bus, an interconnect bus and a plurality of slaves A plurality of second connection means for connecting and disconnecting between buses,
By controlling the operation of the first connection means and the second connection means by the control means, when data transfer is performed between, for example, various functional blocks connected to the bus, only the bus to which the functional blocks are connected is driven, and Is electrically cut off, the bus wiring distance can be shortened, the data transfer speed can be prevented from lowering due to the parasitic capacitance of the wiring, and the power consumption can be reduced.

(2) At least one of a CPU, a memory, an external input / output circuit, and an internal function block is connected to a master bus, and one or more internal function blocks are connected to a plurality of slave buses. Therefore, when performing data transfer between a plurality of functional blocks connected to different slave buses, it is possible to perform data transfer via an interconnect bus, and to access data such as a CPU or a memory at a low frequency. Without occupying the master bus to which the higher block is connected, processing can be performed regardless of the operation of the functional block in data transfer between various functional blocks. Further, even when it becomes necessary to operate the CPU by an operation such as an interrupt, the other slave buses can perform high-speed processing without interrupting data transfer.

(3) The first connection means can switch between data transfer from the master bus to the slave bus and data transfer from the slave bus to the master bus, and can perform data transfer from the slave bus to the interconnect bus and The data transfer from the connect bus to the slave bus can be switched by the second connection means, so that the function blocks connected to the slave bus or the functions connected to, for example, the CPU and slave bus connected to the master bus are connected. Data transfer can be reliably performed between blocks.

(4) When performing data transfer between any one of the plurality of slave buses and the master bus, the control means sets only the first connection means between the slave bus and the master bus to a connected state. Since the second connection means between the slave bus and the interconnect bus that perform data transfer is cut off, the data can be reliably transferred between the slave bus and the master bus without erroneous data transfer from the slave bus to another slave bus. Data transfer can be performed.

(5) When performing data transfer between any two of the plurality of slave buses, the control means sets only the second connection means between the two slave buses and the interconnect bus to a connected state. In this case, the first connection means between the slave bus and the master bus for performing the data transfer is cut off, so that the data transfer between the two slave buses can be reliably performed without erroneous data transfer from the slave bus to the master bus. be able to.

(6) When performing data transfer within the master bus, the control means sets all of the first connection means in the cutoff state, so that the control means is connected to the master bus without erroneous data transfer to the slave bus. For example, data transfer can be performed between a CPU and a memory.

(7) When data transfer is performed within the slave bus, the control means sets the first connection means and the second connection means connected to the slave bus to a cutoff state. Data can be transferred between functional blocks connected to the slave bus without erroneously transferring data to the bus or master bus.

(8) Since the semiconductor integrated circuit has the bus structure described in any one of (1) to (7), when data transfer is performed between, for example, various functional blocks connected to the bus, the functional block Drive only the connected buses and electrically cut off the other buses, shortening the bus wiring distance, preventing a reduction in data transfer speed due to wiring parasitic capacitance, and reducing power consumption. Can be reduced.

(9) Since the electronic equipment includes the bus structure described in any one of (1) to (7) or the semiconductor integrated circuit described in (8), for example, various functional blocks connected to the bus are provided. When data transfer is performed between buses, only the bus connected by the function block is driven and the other buses are electrically disconnected, so the bus wiring distance can be shortened, and data transfer due to the parasitic capacitance of the wiring Power consumption can be reduced while preventing a decrease in speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a bus structure according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a bus structure for performing data transfer between different buses.

FIG. 3 is a circuit diagram showing a circuit configuration of a primary connection circuit.

FIG. 4 illustrates a case where the connection circuit illustrated in FIG. 3B is used.
5 is a table showing an example of each control signal when data is transferred from PU1 to a functional block 51.

FIG. 5 is a table showing an example of each control signal when data is transferred from the functional block 51 to the CPU 1 when FIG. 3B is used.

FIG. 6 is a table showing an example of each control signal when data is transferred from the function block 51 to the function block 52 when FIG. 3B is used.

FIG. 7 is a table showing an example of each control signal when data is transferred from the function block 51 to the function block 53 when FIG. 3B is used.

FIG. 8 is a block diagram showing a conventional bus structure in which a plurality of functional blocks are connected.

[Explanation of symbols]

 1-CPU 2-Memory 3-External I / O Circuit 10-Arbitration Circuit 11-Master Bus 12-14-Slave Bus 15-Interconnect Bus 21-23-Primary Connection Circuit 31-33 Secondary Connection Circuit

Claims (9)

[Claims] 1. A master bus, a plurality of slave buses,
A bus structure comprising: a plurality of first connection means for connecting and disconnecting between the master bus and the slave bus; and control means for controlling an operation of the first connection means. And a plurality of second connection means for connecting and disconnecting the bus and the plurality of slave buses, wherein the control means controls the operation of the second connection means. 2. The master bus includes a CPU, a memory,
2. The device according to claim 1, wherein at least one of an external input / output circuit and an internal function block is connected, and one or a plurality of internal function blocks are connected to the plurality of slave buses, respectively. Bus structure. 3. The first connection unit is capable of switching between data transfer from the master bus to the slave bus and data transfer from the slave bus to the master bus. 3. The bus structure according to claim 1, wherein data transfer from a slave bus to the interconnect bus and data transfer from the interconnect bus to the slave bus are switchable. 4. The control unit, when performing data transfer between any one of the plurality of slave buses and the master bus, connects only the first connection unit between the slave bus and the master bus. 4. The bus structure according to claim 1, wherein said second connection means between said slave bus performing said data transfer and said interconnect bus is cut off. 5. When the data transfer is performed between any two of the plurality of slave buses, the control means connects only the second connection means between the two slave buses and the interconnect bus. And a first bus between the slave bus performing the data transfer and the master bus.
The bus structure according to any one of claims 1 to 4, wherein the connection means is set in a cutoff state. 6. The bus according to claim 1, wherein said control means, when performing data transfer within said master bus, turns off all said first connection means. Construction. 7. The control means, when performing data transfer within one slave bus among the plurality of slave buses, wherein the first control unit controls the first bus between the slave bus and the master bus.
7. The bus structure according to claim 1, wherein said connecting means and said second connecting means between said slave bus and said interconnect bus are cut off. 8. A semiconductor integrated circuit comprising the bus structure according to claim 1. 9. An electronic device comprising the bus structure according to claim 1 or the semiconductor integrated circuit according to claim 8.