JP2002342399A - Method and program for designing dummy pattern accompanying polishing process and recording medium with the program recorded thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently design a dummy pattern to be formed on a wiring layer for eliminating the surface step of polished surfaces after a chemical mechanical polishing(CMP) process in a production process of semiconductor device. SOLUTION: The correction value of pattern density is determined on the basis of allowable pattern density derived from the request of inter-wiring capacity reduction and proper pattern density derived from the request of surface step reduction on the polished surfaces. Further, it is verified by simulation whether the surface step of the polished surfaces is settled within an allowable range or not when the dummy pattern is formed so that the corrected pattern density can be provided and when the step is out of the allowable range, by repeating similar processing, the pattern density satisfying two requests in good balance is determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, in which CMP (Chemical Mechanical Polishing) is performed beforehand on a wiring layer in order to eliminate a surface step on a polished surface. The present invention relates to a method for designing a dummy pattern, a design program for implementing the method, and a computer-readable recording medium on which the program is recorded.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices,
Many processes in the manufacturing process use CMP technology. Since CMP is easy to locally planarize, it is used for polishing of an interlayer film of a multilayer wiring, polishing of a wiring metal, polishing of an oxide film in an STI (Shallow Trench Isolation) step, and the like.

[0003] Among them, it has been pointed out that in the CMP of an interlayer film, when the density of a wiring pattern covered by the interlayer film is not uniform, a surface step remains after polishing.
As a solution, a method is known in which a dummy pattern different from the wiring pattern is formed in the wiring layer to make the pattern density uniform, thereby improving the flatness after polishing. For example, Ruiqi Tian et al.
d Dummy Feature Placement for Oxide Chemical-Mecha
nical Polishing Manufacturability "(37 ^th Design Au
At tomation Conference, 2000, pp. 667-670), a method of determining the arrangement of dummy patterns with uniform pattern density based on a simulation model is proposed. In this method, the chip is divided into a plurality of regions, which are the units of calculation, and a pattern density that minimizes the film thickness difference within the chip for each region is obtained by linear programming, and the actual pattern density is calculated. This is a method of arranging the dummy patterns so as to be equal to the pattern density. By arranging the dummy pattern by this method, the surface step of the polished surface after the CMP step can be reduced.

[0004]

However, the formation of the dummy pattern causes a new problem of increasing the capacitance between wirings while reducing the surface step on the polished surface. Therefore, it is not preferable to form a large number of dummy patterns so that the capacitance between wirings becomes a problem even though the pattern density is made uniform. The above method has a problem in that it is impossible to verify whether the finally determined pattern arrangement has no problem from the viewpoint of the capacitance between wirings. Furthermore, the above-mentioned method takes a long time for calculation because it performs optimization processing based on a linear programming for each calculation unit area, and is not very practical.

In view of these problems, the present invention implements a design method and a method for efficiently finding an optimal dummy pattern arrangement within a short time without causing a problem of inter-wiring capacitance. And a computer-readable recording medium on which the program is recorded.

[0006]

According to the present invention, there is provided a method of designing a dummy pattern formed on a wiring layer of a semiconductor device, which is different from a wiring pattern of the wiring layer. Performing a polishing simulation based on the pattern density to calculate a thickness of a layer to be polished representing a height from a predetermined reference plane to a polished surface in each calculation unit area defined on the chip; and (b) performing the calculation Based on the polished layer thickness of each calculation unit region determined by the step of determining whether the surface step of the polished surface is within an allowable range,
(C) When it is determined that the value is outside the allowable range in the determination,
Allowable pattern density representing the upper limit of the pattern density of the calculation unit area when the dummy pattern is arranged so that the inter-wiring capacitance generated between the wiring pattern and the dummy pattern is equal to or less than a predetermined value for each calculation unit area And, determine the appropriate pattern density representing the pattern density of the calculation unit area when the dummy pattern is arranged such that the surface step of the polished surface is within the allowable range, based on the allowable pattern density and the appropriate pattern density Determining the correction pattern density of the calculation unit area, and replacing the pattern density of the wiring layer in step (a) with the correction pattern density, and performing steps (a) to (c) on the step of the polished surface. Is repeated until it is determined to be within the allowable range, thereby determining the pattern density of each calculation unit area. That is a method of designing a dummy pattern. After the pattern density is determined, a dummy pattern having a predetermined shape is arranged so that the pattern density of each calculation unit area becomes the determined pattern density.

In the step (c), the permissible pattern density is calculated by extracting a region which is at least a predetermined distance from a predetermined wiring and forming a dummy pattern so as to fill the entire region. It is preferable to set the pattern density of the unit area. At this time, the width of the region representing each wiring is enlarged according to the predetermined distance, and a region other than the expanded region is extracted by a logical operation, thereby being separated from the predetermined wiring by a predetermined distance or more. It is preferable to extract a region. In addition, the predetermined wiring is not limited to the wiring in the same layer as the layer forming the dummy pattern,
It is preferable to include wiring of another layer.

In the step (c), the proper pattern density is determined based on the thickness of the layer to be polished determined by the polishing simulation so that the surface step of the polished surface is within an allowable range. Is preferably set, and the pattern density for achieving the target film thickness is calculated back from the target film thickness.

In the step (c), when determining the corrected pattern density, comparing the proper pattern density with the allowable pattern density, if the proper pattern density is larger than the allowable pattern density,
It is preferable that the permissible pattern density be a corrected pattern density.

Next, a first design program of the present invention is as follows:
A program for designing a dummy pattern different from the wiring pattern of the wiring layer formed on the wiring layer of the semiconductor device. The computer executes a polishing simulation based on the pattern density of the wiring layer and defines the program on the chip. The polishing simulation means for calculating the thickness of the polished layer representing the height from the predetermined reference plane to the polished surface in each calculation unit region, and the polished layer thickness of each calculation unit region obtained by the polishing simulation means Based on the surface step evaluation means to determine whether the surface step of the polished surface is within an allowable range, as a result of the determination by the surface step evaluation means, if it is determined that the outside of the allowable range, for each of the calculation unit area The calculation unit when the dummy pattern is arranged such that the capacitance between wirings generated between the wiring pattern and the dummy pattern is equal to or less than a predetermined value. The allowable pattern density indicating the upper limit value of the pattern density of the area and the appropriate pattern density indicating the pattern density of the calculation unit area when the dummy pattern is arranged so that the surface step of the polished surface is within the allowable range are obtained. Functioning as correction pattern density determining means for determining a correction pattern density of the calculation unit area based on the allowable pattern density and the appropriate pattern density, and correcting the pattern density of the wiring layer by the correction pattern density determining means. By replacing the pattern density, the calculation of the thickness of the layer to be polished by the polishing simulation means and the evaluation of the surface step of the polished surface by the surface step evaluation means,
This is a dummy pattern design program characterized by determining the pattern density of each calculation unit area by causing the computer to repeat the process until the surface step of the polished surface is determined to be within the allowable range.

The computer may further function as dummy pattern arranging means for arranging a dummy pattern having a predetermined shape so that the pattern density of each of the calculation unit areas becomes the determined pattern density.

Further, a second design program of the present invention comprises:
A dummy pattern design program formed on a wiring layer of a semiconductor device, which is different from a wiring pattern of the wiring layer, and a computer is provided with a wiring pattern and a dummy pattern for each calculation unit area defined on a chip. Means for obtaining an allowable pattern density representing the upper limit of the pattern density when the dummy pattern is arranged so that the inter-wiring capacitance generated between the dummy patterns is equal to or less than a predetermined value. Means for determining an appropriate pattern density representing the pattern density when the dummy patterns are arranged so as to be within the allowable range, and correcting the corrected pattern density of each calculation unit area to the allowable pattern density and the appropriate pattern density of the calculation unit area. This is a dummy pattern design program characterized by functioning as a means for determining based on the dummy pattern.

At this time, the permissible pattern density is defined as a pattern of each calculation unit region when a region separated from a predetermined wiring by a predetermined distance or more is extracted and a dummy pattern is formed so as to fill the entire region. Preferably, it is a density. In addition, the process of extracting an area that is at least a predetermined distance from the predetermined wiring expands the width of the area representing each wiring according to the predetermined distance, and performs a logical operation on an area other than the expanded area. It is preferable that the extraction is performed by the following method. Further, it is preferable that the predetermined wiring includes not only wiring in the same layer as the layer forming the dummy pattern but also wiring in another layer.

The proper pattern density is determined by the CM
A target thickness is set based on the thickness of the layer to be polished obtained by the P simulation means so that the surface step of the polished surface is within an allowable range, and the target thickness is achieved from the target thickness. Is preferably obtained by back calculation of the pattern density.

Further, when determining the corrected pattern density of each of the calculation unit areas, the appropriate pattern density is compared with the allowable pattern density, and when the appropriate pattern density is larger than the allowable pattern density, the allowable pattern density is determined. It is preferable that the pattern density is the corrected pattern density.

Further, a recording medium of the present invention is a computer-readable recording medium in which the first or second dummy pattern design program of the present invention is recorded.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First, the definition of the term “film thickness” will be described. In this specification, for convenience of description, the term “film thickness” is used to express a step on a polished surface. In other words, the term “film thickness” is used not as a term representing the film thickness in a strict sense, but as a term representing the distance (height) from a predetermined reference surface to a polished surface. For example, FIG.
FIG. 3 is a chip cross-sectional view showing a state where an insulating layer 19 is formed on a wiring pattern 20. In this figure, the reference plane is a plane X
If the thickness of the point A is h _a, point B
The film thickness rather than H, a h _b. Further, the reference plane is not limited to the plane X in FIG. 7 and may be an arbitrary plane.

Embodiment 1 FIG. 1 is a flowchart showing an outline of processing of a dummy pattern designing method and a program according to an embodiment of the present invention. First, the density of the wiring pattern before arranging the dummy pattern is calculated (S101). Next, based on the pattern density, a CMP simulation is executed to calculate a film thickness when CMP is performed without forming a dummy pattern (S102). As a result of evaluating the surface step on the polished surface based on the simulation result (S103), if the step is within the allowable range, it is not necessary to add a dummy pattern, so the original layout data becomes the final layout data as it is (S107). ). On the other hand, if the step is not within the allowable range, the value of the pattern density is corrected (S10).
6) Re-evaluate by simulation based on the corrected values (S102, S103). As a result of the reevaluation,
If the step is not within the allowable range, the condition for evaluating the surface step on the polished surface or the condition of the calculation formula for correcting the pattern density is adjusted (S105). The pattern density is corrected again under the adjusted conditions (S106), and the simulation and the evaluation of the result are performed (S102, S10).
3). The same processing is repeated until the level difference falls within the allowable range, and the pattern density at the time when the level finally falls within the allowable range is determined as the pattern density after forming the dummy pattern.
Further, final layout data in which dummy patterns of a predetermined shape (for example, a mesh shape) are arranged so that the pattern density becomes the determined pattern density is generated (S
107). Step S104 in FIG. 1 is a step of determining the number of times of evaluation, and is a step of determining whether it is necessary to adjust conditions (S105) before performing a re-simulation.

The above is the overall flow of the processing. Next, the pattern density correction processing (S106) will be further described. FIG. 2 is a block diagram showing the structure of a design program for implementing the above method. In FIG. 2, a pattern density calculation means 2 is a means for calculating the density of a wiring pattern before dummy pattern placement based on the layout data 1 (a means for executing step S101), and includes a CM
The P simulation means 3 is a means for executing the simulation of step S102, the surface step evaluation means 4 is a means for determining whether or not the step is within an allowable range (a means for executing step S103), and the layout data correcting means. Reference numeral 5 denotes a unit (means for executing step S107) that modifies the original layout data 1 and generates a modified version of the layout data in which a dummy pattern is added. In FIG. 2, means surrounded by a frame 6 is means for correcting the pattern density (step S1).
06 for executing the process No. 06).

The means 6 for modifying the pattern density comprises:
A dummy pattern allowable area extracting means 7 for extracting a dummy pattern allowable area based on the layout data 1, an allowable pattern density calculating means 8 for calculating an allowable pattern density based on the extracted dummy pattern allowable area, and a surface step evaluation means 4, when it is determined that the step is not within the allowable range, the target film thickness setting means 11 sets the target film thickness based on the simulation result subjected to the determination.
And an appropriate pattern density calculating means 9 for obtaining an appropriate pattern density from the set target film thickness, an allowable pattern density obtained by the allowable pattern density calculating means 8 and an appropriate pattern density obtained by the appropriate pattern density calculating means 9. Correction pattern density determining means 1 for determining a correction pattern density based on
It consists of 0.

Here, the "dummy pattern allowable area" refers to an area which does not adversely affect the function of the semiconductor device even if a dummy pattern is formed in the area. In other words, it is a region where the capacitance between wirings generated between the dummy pattern formed in that region and the original wiring pattern is sufficiently small. The “dummy pattern allowable area” can be extracted based on the layout data 1. The “allowable pattern density” refers to the pattern density when as many dummy patterns as possible are formed within a range that does not affect the function of the semiconductor device. In other words, it is the pattern density when the dummy pattern is formed so as to fill the “dummy pattern allowable area”. “Allowable pattern density” can be obtained based on the result of extracting “dummy pattern allowable area”. Further, “appropriate pattern density” refers to an appropriate pattern density for performing CMP flattening. In other words, the pattern density is simply determined without taking into account the problem of the capacitance between the wirings, so that the surface step of the polished surface is within an allowable range. In the present embodiment, the “appropriate pattern density” is not calculated from the layout data 1 but is calculated from the set target film thickness by back calculation. At this time, the target film thickness is set based on the result of the CMP simulation so that the surface step on the polished surface is reduced.

In the present embodiment, the corrected pattern density determining means 10 compares the allowable pattern density with the appropriate pattern density, and if the appropriate pattern density is equal to or less than the allowable pattern density, sets the appropriate pattern density as the corrected pattern density. If the appropriate pattern density is higher, the allowable pattern density is set as the corrected pattern density. In other words, in order to keep the surface step of the polished surface within the allowable range, the corrected pattern density may be set to the appropriate pattern density. However, when the appropriate pattern density is higher than the allowable pattern density, there is a problem such as the capacity between wirings. Therefore, priority is given to avoiding the problem, and an allowable pattern density is adopted. The determined corrected pattern density becomes an input to the CMP simulation means 3, and the CMP simulation is executed again.

The overall flow of the processing of the present invention and the processing executed by each processing step or each means have been described above. Next, specific calculation processing will be described in further detail.

FIG. 3 is a diagram for explaining an example of a chip layout and a method of calculating a pattern density. The calculation of the pattern density and the CMP simulation described above are shown in FIG.
As shown in (1), an area 12 having a predetermined size as a unit of calculation (hereinafter, referred to as a calculation unit area) is defined on the LSI chip 1 and executed for each calculation unit area. In the present embodiment, the actual size is 100 μm × 100
The area of μm is set as a calculation unit area. However, since the size of the calculation unit area is only one of the design items, it may be a larger (or smaller) area. Further, in the present embodiment, to simplify the processing, all the calculation unit regions are set to a uniform size. However, the method of the present invention is not limited to the case where the calculation unit regions have a uniform size. Absent. In the following description, each calculation unit area is represented by i =
.., For example, the pattern density ρ of the calculation unit area _i is expressed as ρi.

First, the processing of the pattern density calculation means 2 in FIG. 2 will be described. The pattern density can be obtained as an area ratio of a region representing a wiring. For example, as shown in FIG. 3, in a layout in which six wirings 13 are arranged, the pattern density of the calculation unit area 12 is obtained by calculating the total area of the areas representing the six wirings 13 by the calculation unit area. It can be obtained as a value obtained by dividing by the entire area.

Next, the processing of the CMP simulation means 3 of FIG. 2 will be described with reference to FIG. Figure 4 shows CM
FIG. 3 is a diagram for explaining a model of a P simulation, in which an insulating film 19 formed on a wiring pattern 20 is polished with a polishing cloth 18 (hereinafter referred to as a “pad”) attached to a polishing apparatus 17.
That. ) Shows the state of polishing.

In the simulation model used in the present embodiment, first, the pad 18 is deformed due to the unevenness of the surface of the insulating film 19 and stress is applied to the pad. It is assumed that it is given as a convolution of the step distribution and the stress response function.
As described above, if the step on the surface is expressed as the film thickness h of the insulating film 19, the distortion generated in the pad 18 in the calculation unit region i is obtained by subtracting the change due to the force applied from the peripheral region from the change in hi. It is required by doing. At this time, the difference in the amount of change can also be expressed as the difference in the original film thickness, so that the vertical stress σ applied to the pad 18 can be expressed by the following equation (1).

(Equation 1) Here, E is the elastic modulus of the pad, and L is the thickness of the pad before deformation. In the present embodiment, the stress response function f is
Based on the tensile stress obtained by the elastic analysis when only the center coordinate point was displaced and constrained using the axially symmetric model, the stress response function value was determined so as to conform to the actual measurement results. For the elasticity analysis, for example, a finite element method analysis program “ANSSYS” manufactured by Cybernet Systems, Inc. is used.

Second, in this simulation model, the vertical stress σ applied to the pad 18 due to stress concentration
Is inversely proportional to the density ρ of the pattern 20. Third, from the Preston's equation, the polishing rate is equal to the pad 18
Shall be proportional to the vertical stress applied to However, in addition to the vertical stress σ from the insulating film 19,
It is assumed that the stress Pi from the device 17 is also applied.

Based on the above three assumptions, the polishing rate (the polishing amount per unit time) is represented by the following equation (2).

(Equation 2) Here, Δh _i / Δt is the polishing amount per unit time, A is a constant, E is the elastic modulus of the pad, L is the film thickness of the pad, ρ _i
Is the pattern density. By integrating the equation (2) with time, the polishing amount when CMP is performed for a predetermined time can be obtained. Further, by calculating the difference between the original film thickness and the polishing amount, each polishing amount after the CMP process can be obtained. it can be determined thickness h _i of the region. If a fast Fourier transform (FFT) algorithm is used for the calculation of the convolution, the calculation time can be further reduced. Note that this simulation model is merely an example, and it goes without saying that another simulation model may be adopted.

Next, the processing of the surface step evaluation means 4 of FIG. 2 will be described. In the present embodiment, the maximum value and the minimum value are selected from the film thickness of each calculation unit region determined by the CMP simulation, and the difference is compared with a predetermined target difference. Evaluate whether it is within the allowable range. In the present embodiment, the target step ΔH is defined by the following equation (3).

(Equation 3) _{However, h max} is the maximum value of the film thickness obtained by the CMP _simulation, is _{h m in} the minimum value. Also, the average value of the pattern density of a 500 μm square area centered on the calculation unit area where the film thickness is minimum is defined as D _min, and the dummy pattern is formed in the entire dummy pattern allowable area in this area. The increase in pattern density is Δd
_min . However, it goes without saying that the definition of the target step ΔH is not limited to the definition by the above equation (3).

Next, the processing of the target film thickness setting means 11 of FIG. 2 will be described. In the present embodiment, a value represented by the following equation (4) is calculated based on the target step ΔH.
The target film thickness h _gi of each calculation unit region is set.

(Equation 4) Needless to say, the target film thickness _hgi may be defined by another equation.

Next, the proper pattern density calculating means 9 shown in FIG.
Will be described. In the present embodiment, the appropriate pattern density D _pi of each calculation unit region is calculated back from the target film thickness h _g obtained by the equation (4) using the following equation (5).

(Equation 5) Here, the function F is a filter function obtained as a time integral of the stress response function f. Note that the expression (5) may be calculated using a fast Fourier transform algorithm.

Next, the processing of the dummy pattern allowable area extracting means 7 in FIG. 2 will be described. FIG. 5 is a diagram for explaining a method of extracting a dummy pattern allowable area and a method of obtaining an allowable dummy pattern density. As described above, the dummy pattern allowable area is an area in which the problem of inter-wiring capacitance does not occur with the original wiring even when the dummy pattern is formed. Therefore, in the present embodiment, an area where a problem occurs when a dummy pattern is formed is obtained, and the other area is extracted by a logical operation to be a dummy pattern allowable area. First, as shown in FIG. 5A, by performing data processing for increasing the width 14 of the wiring 13, a region where a dummy pattern cannot be formed (hereinafter, referred to as a dummy pattern non-permissible region). This is because the capacitance between wires does not matter even if a dummy pattern is formed at a position at least a predetermined distance from the wires. When the process of increasing the wiring width 14 is performed for all the wirings, a dummy pattern non-permissible region 15 is obtained as shown in FIG. By executing the NOR operation for inverting the layout data, the dummy pattern allowable area 16 can be extracted as a result.

However, the method of extracting the dummy pattern allowable area 16 is not limited to the above method. For example, if it is sufficient that the problem of the capacitance between wirings does not occur with some of the selected wirings, the dummy pattern allowable area 16
It is not necessary to be at least a certain distance from all the wirings, and it is sufficient that the wiring is at least a certain distance from some of the target wirings.

Next, the allowable pattern density calculating means 8 shown in FIG.
Will be described with reference to FIG. As described above, in the present embodiment, the allowable pattern density is the pattern density when the dummy pattern is formed so as to fill the dummy pattern allowable area. Therefore,
The value obtained by dividing the value obtained by adding the area of the wiring 13 shown in FIG. 5C and the area of the dummy pattern allowable area 16 by the area of the calculation unit area is the allowable pattern density.

The processing of the correction pattern density determining means 10 in FIG. 2 is as described above. That is, if the appropriate pattern density is larger than the allowable pattern density, the allowable pattern density is used as the corrected pattern density of the calculation unit area,
In other cases, the appropriate pattern density is used as the corrected pattern density. However, the method of determining the corrected pattern density is also
It is not limited to the method of the present embodiment. For example, a method may be used in which a value obtained by multiplying each of the allowable pattern density and the appropriate pattern density by a weighting factor is used as the corrected pattern density.

Further, in the present embodiment, as the adjustment of the condition of step S105 in FIG. 1, the value of the target step ΔH defined by the equation (3) is increased by 10%. In addition, as a condition for the adjustment, for example, when the wiring width is increased in the process of extracting the dummy pattern allowable area, a method of reducing the increase in the width can be considered.

As described above, in the present embodiment,
In deciding the arrangement of the dummy pattern,
The simulation is executed, the target film thickness of each calculation unit region is set based on the simulation result, and the pattern density such that the film thickness after the CMP becomes the target film thickness is calculated back by a predetermined calculation formula. On the other hand, the upper limit (allowable pattern density) of the pattern density is determined so that the inter-wiring capacitance generated between the dummy pattern and the original wiring is equal to or less than a predetermined value. If the upper limit is exceeded, the upper limit is used as the corrected pattern density. For this reason, the CMP is performed while keeping the inter-wiring capacitance below a predetermined value.
It is possible to eliminate the surface step of the polished surface later.

When the above-mentioned simulation model is adopted, the calculations to be performed are limited to simple logical operations and several convolution operations. Therefore, a conventional method for optimizing the pattern density based on a linear programming method is used. The calculation amount is much smaller than the method, and the result can be obtained in a short time. For example, in a standard chip, the size of the calculation unit area is 100 μm square, and the clock frequency is 500 μm.
It has been confirmed that the calculation is completed within 20 minutes when the calculation is performed by the CPU of the MHx.

As is clear from the above description, the processing in each step can be automated to some extent by setting some values in advance. For this reason, CM
An automatic system for designing a dummy pattern for the P process can be constructed.

Embodiment 2 Next, a second embodiment will be described. In the first embodiment, the dummy pattern allowable region is extracted as a region where the problem of the capacitance between the wirings does not occur between the wirings in the same layer. In some cases, the inter-wiring capacitance generated between them may be a problem. Therefore, in the second embodiment, a dummy pattern allowable region is extracted in consideration of wirings in upper and lower layers.

FIG. 6 is a diagram for explaining a method of extracting a dummy pattern allowable region in the case of a multilayer wiring, and is a diagram in which layouts of two layers are displayed in an overlapping manner. The wiring 13a is in a layer for forming a dummy pattern, and the wiring 13b is in a layer thereabove. As in the first embodiment, the width of the wiring 13a is increased by the distance 21a and the width of the wiring 13b is increased by the distance 21b, and the dummy pattern allowable area 16 is extracted by performing a NOR operation. However, the distance 21b may be smaller than the distance 21a. This is because, in the case of the wiring in the upper layer, even if only the distance 21b is separated in plan, it is actually separated by the distance 21a.

According to the second embodiment, the optimum arrangement of the dummy patterns can be obtained in consideration of the inter-wiring capacitance generated between the upper and lower wirings, and the speed degradation caused by the formation of the dummy patterns can be determined. It exerts a further effect on prevention.

[0044]

According to the method and the like of the present invention, an allowable pattern density derived from a demand for reducing the capacitance between wirings and an appropriate pattern density derived from a demand for reducing the surface step on the polished surface are obtained, respectively, and based on both densities. Since the correction value of the pattern density is obtained by the simulation, and whether the surface step of the polished surface is within an allowable range is repeatedly verified by simulation,
It is possible to determine a pattern density satisfying the two requirements in a well-balanced manner.

Furthermore, if the shape of the dummy pattern is predetermined as a predetermined shape (for example, a mesh shape), the arrangement of the dummy pattern is uniquely determined, so that the processing up to the layout correction can be automated.

On the assumption that the inter-wiring capacitance is less than a predetermined value if the wiring pattern is separated from the wiring pattern by a predetermined distance or more, the allowable pattern density can be obtained only by a simple calculation, and the efficiency is high. Furthermore, under this assumption,
By expanding the width of the wiring region on the layout and extracting the other region by a logical operation, a region where a dummy pattern can be formed can be extracted, so that the region extraction processing can be automated.

When the capacitance between wirings is taken into consideration, not only the wiring in the layer on which the dummy pattern is formed but also the wiring capacitance between wirings in other layers is taken into consideration. Speed degradation due to an increase in capacity can be more efficiently prevented.

Further, when obtaining an appropriate pattern density, instead of performing calculations based on the original wiring layout,
If the target film thickness is set based on the result of the CMP simulation and the pattern density is calculated backward from the target film thickness, the processing time can be reduced because the amount of calculation is small.

Further, if the allowable pattern density is compared with the proper pattern density, and the proper pattern density exceeds the allowable pattern density, the allowable pattern density is determined to be the corrected pattern density. It becomes possible to design a dummy pattern in consideration of the problem of the capacitance between wirings.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an outline of a dummy pattern design method and program processing;

FIG. 2 is a block diagram showing a structure of a dummy pattern design program.

FIG. 3 is a diagram for explaining an example of a layout and a method of calculating a pattern density;

FIG. 4 is a diagram for explaining a model of a CMP simulation;

FIG. 5 is a diagram for explaining a method of extracting a dummy pattern allowable area and a method of obtaining an allowable dummy pattern density;

FIG. 6 is a diagram for explaining a method of extracting a dummy pattern allowable region in the case of a multilayer wiring;

FIG. 7 is a diagram for explaining the definition of “film thickness”;

[Explanation of symbols]

1 layout data, 12 calculation unit area, 13 wiring, 14 wiring width, 15 dummy pattern non-permissible area,
16 Dummy pattern allowable area, 17 CMP device, 1
8 polishing cloth (pad), 19 insulating film, 20 wiring pattern, 21 distance to dummy pattern allowable area.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA06 5F033 QQ48 UU03 UU07 VV02 XX19 XX23 5F064 EE02 EE03 EE12 EE14 EE15 EE16 EE17 EE22 EE26 EE43 EE60 HH06 HH09 HH10

Claims (16)

[Claims] 1. A method of designing a dummy pattern formed on a wiring layer of a semiconductor device, which is different from a wiring pattern of the wiring layer, the method comprising: (a) performing a polishing simulation based on a pattern density of the wiring layer; Calculating a thickness of a layer to be polished representing a height from a predetermined reference plane to a polished surface in each calculation unit area defined on the chip; and (b) calculating a thickness of each calculation unit area obtained by the calculation. A step of determining whether or not the surface step of the polished surface is within an allowable range based on the thickness of the polishing layer; and (c) a wiring pattern for each of the calculation unit areas when the determination is made that the surface step is outside the allowable range. An allowable pattern density indicating an upper limit value of a pattern density of the calculation unit area when the dummy pattern is arranged so that an inter-wiring capacitance generated between the dummy pattern and the dummy pattern is equal to or less than a predetermined value; A suitable pattern density representing the pattern density of the calculation unit area when the dummy pattern is arranged such that the surface step of the surface is within the allowable range, and the calculation unit area is calculated based on the allowable pattern density and the appropriate pattern density. Determining the corrected pattern density of step (a), wherein the pattern density of the wiring layer in step (a) is replaced with the corrected pattern density, and the steps of steps (a) to (c) are within an allowable range. A pattern density of each calculation unit area by repeating until a determination is made. 2. The dummy pattern designing method according to claim 1, wherein a dummy pattern having a predetermined shape is arranged so that the pattern density of each of the calculation unit areas becomes the determined pattern density. 3. The method according to claim 1, wherein in the step (c), the allowable pattern density is obtained by extracting an area that is at least a predetermined distance from a predetermined wiring and forming a dummy pattern so as to fill the entire area. 3. The method for designing a dummy pattern according to claim 1, wherein the pattern density is a pattern density of each calculation unit area. 4. The method according to claim 1, further comprising: expanding a width of a region representing each wiring according to the predetermined distance, and extracting a region other than the expanded region by a logical operation, by a predetermined distance or more from the predetermined wiring. 4. The method for designing a dummy pattern according to claim 3, wherein a distant region is extracted. 5. The design of the dummy pattern according to claim 3, wherein the predetermined wiring includes not only wiring in the same layer as a layer forming the dummy pattern but also wiring in another layer. Method. 6. In the step (c), the proper pattern density is adjusted so that a surface step of the polished surface is within an allowable range based on a thickness of a layer to be polished obtained by the polishing simulation. 6. The dummy pattern according to any one of claims 1 to 5, wherein the value is obtained by back-calculating a pattern density for achieving the target thickness from the target thickness. Design method. 7. In the step (c), when determining the correction pattern density, comparing the appropriate pattern density with the allowable pattern density, if the appropriate pattern density is larger than the allowable pattern density, 7. The dummy pattern designing method according to claim 1, wherein the allowable pattern density is a corrected pattern density. 8. A program for designing a dummy pattern, which is formed on a wiring layer of a semiconductor device and is different from a wiring pattern of the wiring layer, wherein the computer performs a polishing simulation based on a pattern density of the wiring layer, Polishing simulation means for calculating a thickness of a layer to be polished representing a height from a predetermined reference plane to a polished surface in each calculation unit area defined on the chip; Based on the thickness of the polishing layer, the surface step evaluation means to determine whether the surface step of the polished surface is within an allowable range, as a result of the determination by the surface step evaluation means, when it is determined that the outside the allowable range, When dummy patterns are arranged so that the capacitance between wirings generated between a wiring pattern and a dummy pattern is equal to or less than a predetermined value for each calculation unit area The allowable pattern density indicating the upper limit value of the pattern density of the calculation unit area and the appropriate pattern indicating the pattern density of the calculation unit area when the dummy pattern is arranged such that the surface step of the polished surface is within the allowable range. Density and a corrected pattern density determining means for determining a corrected pattern density of the calculation unit area based on the allowable pattern density and the appropriate pattern density, and the pattern density of the wiring layer is determined by the corrected pattern density determining means. Replace with the determined correction pattern density,
The calculation of the thickness of the layer to be polished by the polishing simulation means and the evaluation of the surface step of the polished surface by the surface step evaluation means are repeated by a computer until the surface step of the polished surface is determined to be within an allowable range. ,
A dummy pattern design program for determining a pattern density of each calculation unit area. 9. The computer according to claim 9, further comprising a dummy pattern arranging means for arranging a dummy pattern having a predetermined shape such that a pattern density of each of said calculation unit areas is equal to said determined pattern density. A program for designing a dummy pattern according to claim 8. 10. A design program for a dummy pattern, which is formed on a wiring layer of a semiconductor device and is different from a wiring pattern of the wiring layer, wherein a computer is provided for each calculation unit area defined on a chip. Means for determining an allowable pattern density representing an upper limit of the pattern density when the dummy pattern is arranged so that the capacitance between wirings generated between the pattern and the dummy pattern is equal to or less than a predetermined value; Means for determining an appropriate pattern density representing a pattern density when a dummy pattern is arranged such that the surface step of the surface is within an allowable range; and correcting the corrected pattern density of each calculation unit area with the allowable pattern density of the calculation unit area. And a function for determining the dummy pattern based on the appropriate pattern density. M 11. The allowable pattern density is obtained by extracting a region at least a predetermined distance from a predetermined wiring and forming a dummy pattern so as to fill the entire region.
The program for designing a dummy pattern according to claim 10, wherein the pattern density is a pattern density of each calculation unit area. 12. A process of extracting an area that is at least a predetermined distance from the predetermined wiring, expanding a width of an area representing each wiring according to the predetermined distance, and extracting an area other than the expanded area. 12. The program for designing a dummy pattern according to claim 11, wherein the program is extracted by a logical operation. 13. The design of the dummy pattern according to claim 11, wherein the predetermined wiring includes not only wiring in the same layer as a layer forming the dummy pattern but also wiring in another layer. program. 14. The method according to claim 1, wherein the proper pattern density is the CMP.
A target thickness is set based on the thickness of the layer to be polished determined by the simulation means so that the surface step of the polished surface is within an allowable range, and the target thickness is achieved from the target thickness. 14. The program for designing a dummy pattern according to claim 10, wherein the program is obtained by back-calculating the pattern density. 15. When determining the corrected pattern density of each calculation unit area, comparing the proper pattern density with the allowable pattern density, and determining that the correct pattern density is higher than the allowable pattern density when the correct pattern density is higher than the allowable pattern density. 15. The program for designing a dummy pattern according to claim 10, wherein the pattern density is a corrected pattern density. 16. A computer-readable recording medium on which the program for designing a dummy pattern according to claim 8 is recorded.