JP2002335050A - Nitride semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield by preventing the pattern collapse, etc., without complicating the number of process steps. SOLUTION: A nitride semiconductor device has a buffer layer 11, an n-type clad layer 12, an n-type optical guide layer 13, an active layer 14, a p-type GaN optical guide layer 15, a p-type AlGaN clad layer 16, and a p-type GaN contact layer 17 laminated as nitride semiconductor layers and a current restriction layer 21 formed, e.g. on the surface layer of the optical guide layer 15. The current restriction layer 21 is formed by reactive ion etching the surface layer of the optical guide layer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a nitride semiconductor device, and more particularly to a method for manufacturing a nitride semiconductor device including a step of forming a current confinement layer.

[0002]

2. Description of the Related Art Generally, when a device such as a semiconductor laser device is manufactured, a process is performed so that a current flows only in a part of the element in order to increase luminous efficiency. The process uses lithography technology to form a pattern,
Generally, a process of depositing an insulating film such as an oxide film on the pattern and then performing crystal growth again is generally performed.

[0003]

However, the number of steps in the process has increased, and the yield has deteriorated due to pattern collapse and the like.

[0004]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a nitride semiconductor device which has been made to solve the above problems.

A method for manufacturing a nitride semiconductor device according to the present invention comprises:
In a method for manufacturing a nitride semiconductor device in which a nitride semiconductor layer is laminated and a current confinement layer is formed on at least one of the nitride semiconductor layers, the current confinement layer is formed of the nitride semiconductor layer The surface is formed by performing reactive ion etching on one surface layer.

In the above-described method for manufacturing a nitride semiconductor device, a predetermined region of at least one surface layer of the nitride semiconductor layer is subjected to reactive ion etching. The resulting damaged layer. For example, when the selected nitride semiconductor layer is p-type, the region subjected to the reactive ion etching becomes n-type. Therefore, the n-type region can be used as a current confinement layer. When the crystal surface is treated by reactive ion etching as described above, nitrogen in the crystal is released, and nitrogen vacancies are formed. In this case, since the compound defect including nitrogen vacancies acts on the donor-like layer, the damage layer is considered to be n-type.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the method for manufacturing a nitride semiconductor device according to the present invention will be described with reference to the cross-sectional views in FIG. Further, an example of a manufacturing apparatus suitable for realizing the above-described manufacturing method will be described with reference to a schematic configuration diagram of FIG.

First, an example of a manufacturing apparatus for realizing the embodiment of the present invention will be described with reference to FIG. The manufacturing apparatus shown in FIG. 2 uses metal organic chemical vapor deposition (hereinafter abbreviated as MOCVD).
device 101. MOCVD apparatus 101
Has a reaction chamber 111 for performing MOCVD, and a susceptor 112 on which a substrate 201 to be processed is placed is installed inside the reaction chamber 111. Susceptor 1 in reaction chamber 111
12, a substrate 201, for example, gallium nitride or c-
Al ₂ O ₃ or GaN was stacked on c-Al ₂
O ₃ is placed. This reaction chamber 111 has a reaction tube line 1
21 are connected.

An ammonia source 122 and a hydrogen source 123 are provided. The ammonia source 122 is connected to the reaction tube line 121 via a mass flow controller 124 and a valve 125, and is connected to the abatement apparatus 151 via a valve 126 and a vent line 141 from the mass flow controller 124. The hydrogen source 123 is branched to mass flow controllers 128, 129, 130, and 131 via a hydrogen purifier 127.

[0010] The mass flow controller 128 is connected to the abatement apparatus 151 via a vent line 141. The mass flow controller 129 is directly connected to the reaction tube line 121. The mass flow controller 130 is connected to the reaction tube line 121 via a bubbler 132 and a valve 133. The mass flow controller 130 is connected to the abatement apparatus 151 via the valve 134 and the vent line 141 from the bubbler 132. The mass flow controller 131 includes a bubbler 135 and a valve 136.
The valve 137 and the vent line 14 are connected to the reaction tube line 121 through the bubbler 135.
1 and connected to the abatement apparatus 151.

Further, the reaction chamber 111 is directly connected to the abatement apparatus 151 via the vent line 141.

In the MOCVD apparatus 101, hydrogen gas highly purified by the hydrogen purifying apparatus 127 is supplied into the bubblers 132 and 135 as a carrier gas. Now, it is assumed that gallium nitride: silicon is grown. Bubbler 1 above
32, 135, for example, trimethylgallium [TMG: Ga (C
H ₃ ) ₃ ], and tetraethylsilane is contained as a silicon raw material. By supplying hydrogen gas into these bubblers 132 and 135, these bubblers 13
From each of 2 and 135, a raw material gas corresponding to the vapor pressure is supplied into the reaction chamber 111 through the reaction tube line 121 together with hydrogen gas as a carrier gas.

Ammonia (NH ₃ ) is used as a nitrogen source. Ammonia is supplied from an ammonia source 122 to a mass flow controller 124, and the flow rate is controlled by the mass flow controller 124. And
A reaction tube line 121 is provided by a valve 125 and a valve 126.
Alternatively, the introduction to the vent line 141 is switched.

Switching between the reaction tube line 121 and the vent line 141 for the raw material gas generated from the bubbler 135 can be performed by opening and closing the valves 136 and 137. Switching of the source gas generated from the bubbler 132 between the reaction tube line 121 and the vent line 141 can be performed by opening and closing the valves 133 and 134. The mass flow controllers 128 to 131 control the flow rate of the hydrogen gas supplied from the hydrogen purifier 127.

Next, a first embodiment of the method for manufacturing a nitride semiconductor device according to the present invention will be described with reference to the cross-sectional views of the manufacturing process shown in FIG. As an example, a case of manufacturing a semiconductor laser device using a gallium nitride substrate will be described below.

As shown in FIG. 1A, ammonia (NH ₃ ) is introduced at room temperature at a flow rate of 10 L / min (standard state), and then the substrate temperature is raised to 1000 ° C.
100 ° C., and in this state trimethylgallium (TM
G) is supplied at a flow rate of 30 μmol / min, and tetraethylsilane is supplied at a flow rate of 1.5 nmol / min. At this time, hydrogen is used as a carrier gas at a flow rate of 10 L / min (standard state). Then, gallium nitride: silicon (GaN: Si) is deposited to a thickness of, for example, 4 μm to form the n-type buffer layer 11. Note that monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) can be used instead of the above tetraethylsilane.

Next, trimethyl aluminum (TMA)
Is supplied at a flow rate of 3 μmol / min, and n-type gallium aluminum nitride (AlGaN: Si) is
To form an n-type cladding layer 12.

Thereafter, the supply of TMA is stopped, and for example,
Gallium nitride: silicon (GaN: Si)
The n-type light guide layer 13 is formed by being deposited to a thickness of 0 nm.

Next, the substrate temperature is lowered to 800 ° C., the supply of silicon is stopped, and TMG is left as it is, and trimethylindium (TMI) is added at 30 μmol / min.
And the active layer 14 is formed to a thickness of, for example, 5 nm.

Thereafter, supply of TMI is stopped, cyclopentadienyl magnesium is supplied at a flow rate of 0.5 μmol / min, and GaN: Mg is deposited as a p-type optical guide layer 15 to a thickness of, for example, 0.1 μm.

Next, as shown in FIG.
After the formation of the mold light guide layer 15, the growth is stopped once,
A step of forming a current confinement layer is performed.

First, a silicon oxide film 31 (including a portion shown by a two-dot chain line in the drawing) is formed on the surface of the p-type light guide layer 15.
Is formed, a resist film is formed on the silicon oxide film 31 by a resist coating technique. Then, the resist film is processed by lithography to form a resist mask 32 having a desired shape. Then, by using an etching technique using the resist mask 32, a portion shown by a two-dot chain line in the drawing is removed, and the oxidation is performed. The silicon film 31 is formed, for example, in the <11-00> direction of the p-type light guide layer 15 or the <1
12-0> direction, width 2 μm, period 12 μm, thickness 0.
It is processed into a silicon oxide pattern 33 of 2 μm. After that, the resist mask 32 is removed.

Thereafter, reactive ion etching (RIE) is performed using the silicon oxide pattern 33 as a mask. The conditions for this reactive ion etching include boron trichloride (BCl ₃ ) and chlorine (C
l ₂ ). Specifically, 10c of chlorine
Supply at m ³ / min to 100 cm ³ / min (standard condition). Then, the pressure of the etching atmosphere is set to 1.3 Pa
And the power to generate plasma is 600
It is set to W and ions are extracted with a self-bias of -200 V (DC). The substrate temperature is set at 25 ° C. When the reactive ion etching is performed by setting the conditions as described above, the etching can be performed at a speed of 200 nm / min to 600 nm / min. Thus, the surface treatment is performed to such an extent that the surface of the p-type light guide layer 15 not covered with the silicon oxide pattern 33 is lightly damaged, and the n-type current confinement layer 21 is formed. Specifically, the above surface treatment is performed so that the etching depth is within 0.1 μm. After that, the silicon oxide pattern 33 is removed by dissolving it with, for example, an acid (for example, a hydrofluoric acid aqueous solution).

In the current confinement layer 21, the thickness of the p-type light guide layer 15 is at least 50 nm, preferably 8 nm or more.
It is desirable to form it so as to secure 0 nm or more.
Hereinafter, the p-type light guide layer 15 covered with the silicon oxide pattern and having no current confinement layer 21 is formed.
Region is referred to as a window 22 of the current confinement layer 21.

Thereafter, as shown in FIG. 1C, the substrate on which the current confinement layer 21 is formed is returned to the MOCVD apparatus, and AlGaN: Mg is formed on the p-type optical guide layer 15 on which the current confinement layer 21 is formed. A p-type cladding layer 16 comprising
A p-type contact layer 17 composed of a GaN: Mg layer is sequentially stacked. For example, the substrate temperature is returned to 1000 ° C., and TMG
(Flow rate: 30 μmol / min), trimethyl aluminum (TMA) (flow rate: 3 μmol / min) and cyclopentadienyl magnesium (flow rate: 0.5 μmol / min)
min), and p-type gallium aluminum nitride (AlGaN: Si) is deposited to a thickness of 0.5 μm to form the p-type cladding layer 16. Finally, the supply of TMA is stopped, and a GaN: Mg layer is deposited to a thickness of, for example, 0.1 μm to form the p-type contact layer 17. Thus, the device structure is completed.

In the first embodiment, the p-type light guide layer 1
Since the surface of No. 5 is subjected to the reactive ion etching, the region subjected to the reactive ion etching becomes an n-type damage layer having a composite defect. Therefore, the p-type light guide layer 1
5, an n-type layer having a window 22 is formed, and this functions as the current confinement layer 21. for that reason,
The current does not flow in the current confinement layer 21, but flows only in the window 22. As described above, since the current constriction layer 21 can be formed by the surface treatment by the reactive ion etching, the nitride semiconductor layers from the n-type buffer layer 11 to the p-type contact layer 17 to be laminated have a low defect density and A crystal layer having a small crystal axis shift is obtained. If a device is manufactured with the above-described stacked structure of the nitride semiconductor layers, the manufactured device can have excellent characteristics. Also,
Since the current confinement layer 21 is formed by surface treatment by reactive ion etching, the current confinement layer 21 is formed without complicating the process and without causing pattern collapse.

Next, a case where a current is applied to a device having a current confinement layer formed by the manufacturing method of FIG. 1 is compared with a case where a current is applied to a device where no current confinement layer is formed according to FIG. In FIG. 3, the vertical axis indicates the light output, and the horizontal axis indicates the current.

As shown in FIG. 3, it was found that the device in which the current confinement layer was formed by performing the RIE process could obtain a higher light output with a lower current. This is because the current is confined by forming the current confinement layer and is efficiently converted to light.

Next, a second embodiment of the method for manufacturing a nitride semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS. As an example, a case of manufacturing a semiconductor laser device using a gallium nitride substrate will be described below.

Using the same process as in the first embodiment, as shown in FIG. 4, gallium nitride: silicon (GaN: Si) is deposited to a thickness of, for example, 4 μm to form an n-type buffer layer 11. Form. Next, n-type gallium aluminum nitride (AlGaN: Si) is deposited to a thickness of, for example, 1 μm to form an n-type cladding layer 12. Thereafter, gallium nitride: silicon (GaN: Si) is deposited to a thickness of, for example, 150 nm to form an n-type light guide layer 13. Further, an active layer 14 is formed on the n-type light guide layer 13 to a thickness of, for example, 5 nm.

Thereafter, GaN: Mg is deposited as a p-type light guide layer 15 on the active layer 14 to a thickness of, for example, 0.1 μm. Next, a p-type cladding layer 16 is formed by depositing an AlGaN: Mg layer to a thickness of 0.5 μm.
An aN: Mg layer is deposited to a thickness of, for example, 0.1 μm to form a p-type contact layer 17.

Next, a step of forming a current confinement layer is performed. First, after a silicon oxide film is formed on the surface of the p-type contact layer 17, a resist film is formed on the silicon oxide film by a resist coating technique. Next, after processing the resist film by a lithography technique to form a resist mask having a desired shape, processing the silicon oxide film using an etching technique using the resist mask,
For example, as in the first embodiment, the width is 2 μm and the thickness is 0.1 μm.
A silicon oxide pattern of 2 μm is formed at a period of 12 μm. After that, the resist mask is removed.

Next, reactive ion etching (RIE) using the silicon oxide pattern as a mask is performed. Thereby, the surface treatment is performed to such an extent that the surface of the p-type contact layer 17 not covered with the silicon oxide pattern is slightly damaged, and the n-type current confinement layer 21 is formed. Specifically, when the etching depth is 0.
The above surface treatment is performed so as to be within 1 μm. afterwards,
The silicon oxide pattern is removed by, for example, dissolving with an acid (for example, a hydrofluoric acid aqueous solution). Hereinafter, the region of the p-type contact layer 17 which is covered with the silicon oxide pattern and in which the current confinement layer 21 is not formed is referred to as the current confinement layer 2.
It will be referred to as one window 22. Thus, a device structure is completed.

As described above, since the layer damaged by RIE becomes n-type, an n-type layer having a window 22 is formed on the surface of the p-type contact layer 17, and this is a current confinement layer. Functions as 21. Therefore, the current does not flow in the current confinement layer 21, but flows only in the window 22.

Next, a third embodiment of the method for manufacturing a nitride semiconductor device according to the present invention will be described with reference to the cross-sectional views of the manufacturing process shown in FIG. As an example, a case of manufacturing a semiconductor laser device using a gallium nitride substrate will be described below.

Using the same process as in the first embodiment, as shown in FIG. 5, gallium nitride: silicon (GaN: Si) is deposited to a thickness of, for example, 4 μm to form an n-type buffer layer 11. Form. Next, n-type gallium aluminum nitride (AlGaN: Si) is deposited to a thickness of, for example, 1 μm to form an n-type cladding layer 12. Thereafter, gallium nitride: silicon (GaN: Si) is deposited to a thickness of, for example, 150 nm to form an n-type light guide layer 13. Further, an active layer 14 is formed on the n-type light guide layer 13 to a thickness of, for example, 5 nm.

Thereafter, GaN: Mg is deposited as a p-type light guide layer 15 on the active layer 14 to a thickness of, for example, 0.1 μm. Next, an AlGaN: Mg layer is deposited to a thickness of 0.5 μm to form a p-type cladding layer 16.

Further, a GaN: Mg layer having a thickness of, for example, 0.05 μm
m of the lower layer 17u of the p-type contact layer 17
To form

Next, a step of forming a current confinement layer is performed. First, after a silicon oxide film is formed on the surface of the lower layer 17u of the p-type contact layer 17, a resist film is formed on the silicon oxide film by a resist coating technique. Next, the resist film is processed by a lithography technique to form a resist mask of a desired shape, and then the silicon oxide film is processed by an etching technique using the resist mask, for example, as in the first embodiment. And width 2
μm, 0.2μm thick silicon oxide pattern of 12μm
It is formed in m periods. After that, the resist mask is removed.

Next, reactive ion etching (RIE) using the silicon oxide pattern as a mask is performed. Thereby, the surface treatment is performed to such an extent that the surface of the lower layer 17u of the p-type contact layer 17 not covered with the silicon oxide pattern is slightly damaged, and the n-type current confinement layer 21 is formed. Specifically, the above surface treatment is performed so that the etching depth is within 0.1 μm. Thereafter, the silicon oxide pattern is removed by dissolving it with, for example, an acid (for example, a hydrofluoric acid aqueous solution). Hereinafter, a region of the lower layer 17u of the p-type contact layer 17 in which the current confinement layer 21 is not formed while being covered with the silicon oxide pattern will be referred to as a window 22 of the current confinement layer 21.

Thereafter, a GaN: Mg layer is formed, for example, at 0.05
The p-type contact layer 17 is completed by depositing to a thickness of μm. Thus, a device structure is completed.

As described above, since the layer damaged by RIE becomes n-type, an n-type layer having a window 22 is formed below the p-type contact layer 17, which is a current constriction. It functions as the layer 21. Therefore, the current does not flow in the current confinement layer 21, but flows only in the window 22.

In each of the above embodiments, the current confinement layer 2
1 may be formed in a plurality of stages by a plurality of processes.

Further, the configurations described in the above embodiments can be formed on a sapphire substrate. In this case, after forming the buffer layer on the sapphire substrate,
An n-type contact layer is formed on the buffer layer. afterwards,
The n-type cladding layer 12, the n-type light guide layer 13, the active layer 14, and the p-type light guide layer 15 are formed on the n-type contact layer. Then, the growth of the p-type light guide layer 15 is stopped once, and the n-type current confinement layer 21 is formed. Next, a p-type cladding layer 16 and a p-type contact layer 17 are sequentially laminated on the p-type light guide layer 15 on which the current confinement layer 21 is formed. Next, in order to secure a region for forming an electrode in the n-type contact layer, a part of the stacked body from the p-type contact layer 17 to the middle of the n-type contact layer is removed. Thus, the device structure is completed. Also in this configuration, the same operation and effect as described in the above embodiment can be obtained.

[0045]

As described above, according to the method for manufacturing a nitride semiconductor device of the present invention, a predetermined region of at least one surface layer of the nitride semiconductor layer is subjected to reactive ion etching. The region becomes a damaged layer in which a composite defect has occurred. For example, when the selected nitride semiconductor layer is p-type, the region subjected to the reactive ion etching becomes n-type, so that the current confinement layer can be formed in the n-type region. As described above, the current confinement layer can be formed by the surface treatment using the reactive ion etching, so that the nitride semiconductor layer to be stacked is a crystal layer having a low defect density and a small deviation of the crystal axis. Since a device can be manufactured with such a stacked structure of nitride semiconductor layers, the manufactured device can have excellent characteristics. Further, since the current confinement layer is formed by surface treatment by reactive ion etching, the process can be prevented from being complicated and pattern collapse can be prevented, so that the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process sectional view showing a first embodiment of a method for manufacturing a nitride semiconductor device of the present invention.

FIG. 2 is a schematic configuration diagram illustrating an example of a MOCVD apparatus that realizes an embodiment of the present invention.

FIG. 3 is a diagram showing the relationship between light output and current.

FIG. 4 is a sectional view showing a manufacturing process according to a second embodiment of the method for manufacturing a nitride semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing step of the third embodiment of the method for manufacturing a nitride semiconductor device according to the present invention.

[Explanation of symbols]

 15: p-type light guide layer, 21: current confinement layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F041 AA03 AA41 AA42 CA04 CA34 CA40 CA65 CA74 CB02 5F045 AA04 AB14 AB17 AB32 AC01 AC07 AC08 AC12 AD12 AD14 AF04 AF09 BB08 CA12 DA53 DP07 EC07 EG08 HA13 5F073 AA07 CA05

Claims (4)

[Claims] 1. A method for manufacturing a nitride semiconductor device, comprising stacking a nitride semiconductor layer and forming a current confinement layer in one of the nitride semiconductor layers, wherein the current confinement layer is formed of the nitride A method for manufacturing a nitride semiconductor device, comprising forming at least one surface layer of a semiconductor layer by reactive ion etching. 2. The nitride semiconductor layer includes an n-type clad layer made of an n-type nitride semiconductor layer, an n-type guide layer made of an n-type nitride semiconductor layer, an active layer, and a p-type made of a p-type nitride semiconductor layer. A p-type cladding layer composed of a p-type nitride semiconductor layer and a p-type guide layer, and after forming the p-type guide layer, the current confinement layer is formed in a predetermined region on the surface of the p-type guide layer. 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said nitride semiconductor device is formed by performing reactive ion etching. 3. The nitride semiconductor layer includes an n-type clad layer made of an n-type nitride semiconductor layer, an n-type guide layer made of an n-type nitride semiconductor layer, an active layer, and a p-type made of a p-type nitride semiconductor layer. A p-type cladding layer made of a p-type nitride semiconductor layer, and a p-type contact layer. The current confinement layer is formed by laminating the p-type contact layer. 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said predetermined region of said surface layer is formed by performing reactive ion etching. 4. The nitride semiconductor layer includes an n-type clad layer made of an n-type nitride semiconductor layer, an n-type guide layer made of an n-type nitride semiconductor layer, an active layer, and a p-type made of a p-type nitride semiconductor layer. A p-type cladding layer comprising a p-type nitride semiconductor layer and a p-type cladding layer. The current confinement layer is formed on the p-type cladding layer after the p-type cladding layer is formed. 2. The nitride semiconductor according to claim 1, wherein a nitride semiconductor layer is formed by performing reactive ion etching on a predetermined region of the p-type nitride semiconductor layer, and thereafter, a p-type contact layer is formed. Device manufacturing method.