JP2002335018A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which can manufacture a semiconductor device performing input and output of an optical signal with high efficiency. SOLUTION: In the method for manufacturing a semiconductor device, an interposer substrate 4 in which a via hole 5 is formed is adhered to a carrier substrate 2 on which an electric wiring pattern 1 is formed, and a basic structure of a ball grid array(BGA) package 7 is constituted. An LSI chip 6 and an optical element chip 3 are arranged at prescribed positions on the carrier substrate 2. The optical element chip 3 is sealed with resin 8 transparent to light for optical signal transmitting and receiving to the optical element chip 3. An electrode pad 11 for a solder bump is formed on the interposer substrate 4, and a solder bump 12 is mounted on the electrode pad 11. A position of the electrode pad 11 is so determined that a light emitting part center of the optical element chip 3 or a light receiving part center 10 is set as reference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having an optical signal input / output mechanism used in optical communication technology.

[0002]

2. Description of the Related Art FIG. 3 shows a prior art example of a semiconductor device having an optical signal input / output mechanism (JP-A-11-36651).
No. 2) and schematically shows a cross-sectional structure thereof.

[0003] The semiconductor device according to this prior art is shown in FIG.
As shown in FIG. 2, an LSI chip 6 having a built-in semiconductor integrated circuit, a surface light emitting element and a surface light receiving element (optical element chip 3).
) Is mounted on a ball grid array (BGA) type package 7, and a printed wiring board (not shown) is provided by a solder bump array (arrangement of solder bumps 12) provided on the lower surface of the package 7. Make the electrical connection. Similarly, a microlens array (arrangement of microlenses 9) is provided on the lower surface of the package 7 on which the solder bumps 12 are provided so as to be optically connected to the printed wiring board. The optical element chip 3 and the LSI chip 6 are both mounted on the bottom 17 of the cavity 16 of the BGA type package 7. Cavity 16
Is filled with a resin transparent to light for transmitting and receiving an optical signal, and a microlens 9 is formed on the surface of the resin. An electric wiring layer (not shown) for interconnecting the LSI chip 6, the optical element chip 3, and passive elements (not shown) such as capacitors and chip resistors and the like is formed on the cavity bottom portion 17. And electrical I / O of package 7
The (input / output) is connected to a solder bump electrode pad 11 on the lower surface of the BGA package 7 via an electrical connection via and an inner layer wiring (neither is shown). The LSI chip 6 and the optical element chip 3 are die-bonded to the upper surface of the package 7 and the mounting surface of the capacitor chip (the bottom surface 18 of the cavity) by solder or resin, and the space between them and the mounting surface (the upper surface of the package 7 and the bottom surface 18 of the cavity) is formed. They are connected by wire bonding 19. Further, the electric wiring on the mounting surface (the upper surface of the package 7 and the bottom surface 18 of the cavity) is connected to the electrode pad 11 on the lower surface of the package 7 via the electric wiring of the inner layer of the package 7 and vias for electric connection.

FIG. 4 is a view for explaining a method of manufacturing the BGA type package 7 shown in FIG. The manufacturing process of the package 7 using a general manufacturing method is as follows.

[0005] 1. A carrier substrate 2 for mounting an electric element chip / optical element chip on which an electric wiring pattern 1 is formed is manufactured.

[0006] 2. An interposer substrate 4 having via holes 5 necessary for mounting an optical element chip on the carrier substrate 2 is manufactured. The interposer substrate 4 has solder bump electrode pads 11 formed thereon.

[0007] 3. The interposer substrate 4 is bonded onto the carrier substrate 2 to form a BGA type package 7 (FIG. 4C).
(See (a) of FIG. 4). The via hole 5 in this state corresponds to the cavity 16 shown in FIG.

[0008] 4. An electric element chip and an optical element chip 3 typified by an LSI chip 6 (shown only in FIG. 4C) are placed on the carrier substrate 2 by die bonding or wire bonding with reference to a marker provided on the carrier substrate 2. It is arranged at a predetermined position. The optical element chip 3 is disposed in the via hole 5.

[0009] 5. Chips represented by the optical element chip 3 are sealed with a resin 8 transparent to light for transmitting and receiving an optical signal to and from the optical element chip 3 to obtain a state shown in FIG. .

[0010] 6. The resin 8 in the optical path for transmitting and receiving an optical signal to and from the optical element chip 3 is brought into a state (thickness, flatness, etc.) necessary for forming a microlens 9 described later.
It is processed by means such as polishing.

7. On the solder bump electrode pad 11,
The solder bump 12 is mounted.

8. A microlens 9 is formed on the surface of the resin 8 in the optical path for transmitting and receiving the optical signal, and the state shown in FIG.

Here, an alignment marker (positioning marker) necessary for mounting an electric element chip typified by the LSI chip 6 and an optical element chip 3 is formed on the chip mounting carrier substrate 2. I have. In step 4, the electric element chip and the optical element chip 3 represented by the LSI chip 6 visually recognize the respective alignment markers, and are mounted and arranged at positions determined based on them. Usually, the LSI chip 6 and the optical element chip 3 are mounted and arranged on the carrier substrate 2 by die bonding, and the electrical wiring is completed by wire bonding.

Although flip chip connection has been increasing in recent years, die bond / wire bond connection is overwhelmingly advantageous in terms of cost.

[0015]

However, in the die bonding technique, the mounting accuracy is limited by the accuracy of a mounting machine for mounting a chip on a substrate. Furthermore, when using a solder paste, the chip rises when the solder melts, and even if the chip is placed in an accurate position by the positioning mechanism of the mounting machine that mounts the chip on the board, the chip lifts when the solder melts. This lowers the accuracy of the chip fixing position.

Further, also in the bonding step in the above step 3, a positional shift occurs. Generally, when bonding substrates, a through hole is formed in both substrates, and alignment (positioning) is performed by inserting guide pins. Therefore, a positional shift corresponding to the insertion clearance of the guide pin is inevitable, the positional shift reaches ± several hundred μm, and the positioning accuracy is not high.

Furthermore, a land (a solder bump electrode pad 1) is formed at an end of an electric connection via hole (different from the via hole 5) formed on the interposer substrate 4.
1 is formed, but it is difficult to increase the relative positional accuracy of these. These lands are aligned with the electric connection via hole or the guide pin as a position reference. However, both the electric connection via hole and the guide pin have low positional accuracy for the above-described reason.

As described above, in the conventional semiconductor package technology, a manufacturing method using a general die bonding mounting technology or a bonding and bonding technology is simple and inexpensive, while the solder bump 12 and the optical device chip 3 are not easily manufactured. Cannot be controlled accurately.

The semiconductor device having the optical signal input / output mechanism is mounted on a printed wiring board by solder bumps 12. At this time, since the semiconductor device is aligned and connected on the printed wiring board by a so-called self-alignment action, the position of the solder bump 12 is the largest factor that determines the positional relationship between the semiconductor device and the printed wiring board.

However, as described above, in the conventional method of manufacturing a semiconductor device having an optical signal input / output mechanism, the positional relationship between the solder bump 12 and the optical element chip 3 can be accurately controlled. For this reason, an optical axis shift occurs between the optical input / output portion on the printed wiring board side and the optical input / output portion on the package side, and the optical coupling efficiency is reduced. Further, in the case of a semiconductor device having multi-channel optical input / output, the optical coupling efficiency between the channels varies, so that the light intensity reaching the light receiving element is different, which puts a pressure on the power budget of the optical transmission system. Was.

As described above, the cause of such a decrease in optical coupling efficiency is the use of a die bonding technique with low mounting precision as a mounting method of an optical element, and the use of an electrical connection via or bonding. The position of the solder bump electrode pad 11 connected via the line does not match the position set in advance when viewed with reference to the alignment marker on the carrier substrate 2.

Such an amount of displacement has not been a problem in a conventional semiconductor device having only an electric signal input / output mechanism. This is because electrical connection is maintained as long as the conductors are in contact, even if the position shift occurs. However, the optical coupling efficiency in the above optical connection is very sensitive to misalignment,
At present, in order to increase the optical coupling efficiency, it is indispensable to minimize the displacement and to make the optical axes of light transfer in optical coupling coincide.

In the formation of the microlens 9, the alignment is performed with reference to the solder bump electrode pad 11 and the alignment marker formed on the surface thereof, so that the optical axis between the optical element and the microlens 9 is aligned. There was a problem of deviation.

An object of the present invention is to solve the above-mentioned problem of misalignment occurring in the relative positional relationship between the solder bump and the optical element chip, and to accurately control the relative positional relation between the solder bump and the optical element chip. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device which inputs and outputs optical signals with high efficiency.

[0025]

According to one aspect of the present invention, there is provided a method of bonding an interposer substrate having via holes to a carrier substrate for mounting an element chip. Disposing an optical element chip on the surface of the carrier substrate exposed in the via hole, and sealing the optical element chip with a resin transparent to light for transmitting and receiving an optical signal to and from the optical element chip. Performing a step of forming a solder bump electrode pad on the interposer substrate; and mounting a solder bump on the solder bump electrode pad on the interposer substrate. In the step of forming the solder bump electrode pad thereon, the position of the solder bump electrode pad is determined by the light emission of the optical element chip. To define a central or receiving unit center as a reference constitutes the method of manufacturing a semiconductor device according to claim.

According to a second aspect of the present invention, a microlens is formed at a position defined on the surface of the resin with reference to the center of the light emitting portion or the center of the light receiving portion of the optical element chip. A method of manufacturing a semiconductor device according to claim 1 is provided.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device having an optical signal input / output mechanism according to the present invention is described. As a criterion, the positional relationship between the solder bump and the optical element is accurately controlled by patterning the electrode pad for the solder bump. Instead of using the center directly as a reference, an alignment marker formed on the optical element and having a clear position relative to the center of the light emitting unit or the center of the light receiving unit may be used as a reference. Is regarded as the auxiliary reference, the center of the light emitting unit or the center of the light receiving unit is used as the alignment reference.

Hereinafter, the present invention will be described with reference to embodiments.

FIG. 1 is a diagram illustrating a method of manufacturing a ball grid array (BGA) type package according to an embodiment of the present invention. The manufacturing process of this package is as follows.

1. A carrier substrate 2 for mounting an electric element chip / optical element chip on which an electric wiring pattern 1 is formed is manufactured. This step is the same as step 1 in the above-mentioned conventional technique.

2. The optical element chip 3 is mounted on the carrier substrate 2
The interposer substrate 4 in which the via hole 5 necessary for mounting on the substrate is formed is manufactured. In this step, unlike the step 2 in the above-described conventional technique, the solder bump electrode pad 11 is not formed on the interposer substrate 4. However, it is convenient to previously form the solder bump electrode lands (14 in FIG. 2) in the region including the positions where the electrode pads 11 are formed at this stage. A part of the electrode land 14 becomes the electrode pad 11 by a process 8 described later.

3. The interposer substrate 4 is bonded onto the carrier substrate 2 to form a BGA type package 7 ((c) in FIG. 1).
(See FIG. 1 (a)). This step is the same as step 3 in the above-mentioned prior art.

4. An electric element chip and an optical element chip 3 typified by an LSI chip 6 (shown only in FIG. 1C) are placed on the carrier substrate 2 by die bonding or wire bonding using a marker provided on the carrier substrate 2 as an alignment reference. At a predetermined position. The optical element chip 3 is arranged on the surface of the carrier substrate 2 exposed in the via hole 5. This step is the same as Step 4 in the above-mentioned conventional technique.

5. Chips represented by the optical element chip 3 are sealed with a resin 8 which is transparent to light for transmitting and receiving an optical signal to and from the optical element chip 3 to obtain a state shown in FIG. . This step is the same as step 5 in the above-mentioned prior art.

6. The LSI chip 6 is sealed with a resin 8 '(shown only in FIG. 1C). The material of the resin 8 ′ may be the same as or different from the resin 8. By this step, the lower surface of the BGA type package 7 (the surface on which the LSI chip 6 is arranged) is flattened,
The SI chip 6 is protected. The flattening of the lower surface and the protection of the LSI chip 6 make it easy to perform a patterning operation by a photolithography technique in the subsequent step 8. Note that this step may be performed as one step in combination with the above step 5.

7. The resin 8 in the optical path for transmitting and receiving an optical signal to and from the optical element chip 3 is brought into a state (thickness, flatness, etc.) necessary for forming a microlens 9 described later.
It is processed by means such as polishing. This step is the same as step 6 in the above-described conventional technique.

8. The electrode pads 11 for solder bumps are patterned (formed into a figure) on the interposer substrate 4 using the center of the light emitting portion or the center of the light receiving portion 10 of the optical element chip 3 as an alignment reference. This step is a step characteristic of the present invention, and the details of this step will be described later.

9. On the solder bump electrode pad 11,
The solder bump 12 is mounted. This step is the same as step 7 in the above-mentioned conventional technique.

10. A microlens 9 is formed on the surface of the resin 8 in the optical path for transmitting and receiving the optical signal, and the state shown in FIG. In this case, the micro lens 9 is formed using the center of the light emitting portion or the center 10 of the light receiving portion of the optical element chip 3 as an alignment reference. This step is the same as step 8 in the above-described prior art except that the position where the microlens 9 is formed is determined with the center of the light emitting portion or the center of the light receiving portion 10 of the optical element chip 3 as an alignment reference.

Unlike the prior art, one of the steps characterized by the present invention is the above step 8. That is, in the present invention, the patterning of the solder bump electrode pad 11 for determining the mounting position of the solder bump 12 is performed using the center of the light emitting portion or the center 10 of the light receiving portion of the optical element chip 3 as an alignment reference.

FIG. 2 is a view for explaining the patterning of the solder bump electrode pad 11. As shown in FIG. In the figure, a solder resist 15 having an opening on a solder bump electrode land 14 formed in a region including a portion where a via 13 for electrical connection is provided on an interposer substrate 4.
Is patterned. A portion of the electrode land 14 located below the opening (a portion hatched in FIG. 2)
Are portions corresponding to the solder bump electrode pads 11. As described above, if the electrode lands 14 are formed in advance in the above step 2,
The pattern of the solder resist 15 and the pattern of the solder bump electrode pad 11 (corresponding to the opening of the solder resist 15) can be formed by one patterning. This patterning is performed by photolithography technology, which is characterized by the fact that accurate alignment is possible,
The center 10 of the light emitting part or the light receiving part of the optical element chip 3 and the electrode pad 11 for the solder bump (and the solder resist 1)
5 opening) can be accurately determined. Therefore, as shown in FIG. 2, the solder bumps 1 accurately mounted on the solder bump electrode pads 11 are formed.
The mutual positional relationship between the light emitting portion 2 and the light emitting portion center or the light receiving portion center 10 of the optical element chip 3 is also accurately determined.

Thus, even if the precision of the arrangement of the optical element chip 3 on the carrier substrate 2 is low and the amount of displacement is large, the relative position between the solder bump 12 and the center of the light emitting section or the light receiving section 10 of the optical element chip 3 is maintained. The relative positional relationship between the BGA type package 7 and the printed board is determined by self-alignment via the solder bumps 12, so that the optical axis of the microlens 9 and the optical waveguide on the printed board side are determined. Between the optical axis and the optical axis can be prevented from occurring, and as a result,
The BGA type package 7 is a semiconductor device that inputs and outputs optical signals with high efficiency.

In the patterning process using the photolithography technique, it is essential that the center of the light emitting portion or the center of the light receiving portion 10 of the optical element chip 3 can be observed through the resin 8 by an aligner device. Therefore, the resin 8 for sealing the optical element chip 3 is required to be highly transparent not only in the wavelength of light used by the optical element but also in the visible light wavelength range.

In such a method, the positional deviation between the solder bump electrode lands 14 and the optical element chip 3 is absorbed when the solder bump electrode pads 11 are patterned. Even if the displacement occurs, as shown in FIG.
4 needs to be larger than the pattern of the electrode pads 11.

In the above step 10, when the microlenses 9 are formed on the surface of the resin 8 in the optical path for transmitting and receiving optical signals, the center of the light emitting portion or the center of the light receiving portion 10 of the optical element chip 3 is aligned. The micro lens 9 is formed as a reference. Thereby, the optical axis of the microlens 9 can be aligned with the center of the optical path, and the light use efficiency can be improved.

When the semiconductor device (in this embodiment, the BGA type package 7) having the optical signal input / output mechanism manufactured as described above is mounted on a printed wiring board, the optical waveguide side input / output position is reduced. In this case, it is possible to provide a highly efficient optical coupling system with small channel-to-channel variation.

A semiconductor device having an optical signal input / output mechanism formed according to the embodiment of the present invention includes an LSI chip 6 containing a semiconductor integrated circuit and a plurality of surface light emitting elements (optical element chips 3). The BGA type package 7 accommodates a surface light emitting element configured by arraying and a surface light receiving element configured by arraying a plurality of surface light receiving elements (optical element chips 3) in an array.

The LSI chip 6 and the surface type optical element are first mounted on the chip mounting surface of the BGA package 7 by die bonding, and connected to the electric wiring layer by wire bonding. On the other hand, the BGA package 7 is provided with inner layer wiring so as to be electrically connected from the electric wiring layer to the surface on which the solder bumps 12 are mounted via the electric connection via and the electric wiring pattern 1. After the optical element chip 3 is mounted and arranged on the carrier substrate 2, the transparent resin 8
Resin sealing. It is desirable that the sealing resin 8 is transparent to light used by the optical element and also transparent to visible light. After the sealing resin 8 is cured by heat curing or light curing, flattening polishing is performed. This planarization polishing is performed so as to leave the solder bump electrode lands 14 formed on the lower surface (the upper surface in FIG. 1) of the BGA package 7.

Subsequently, the solder bump electrode pad 11 and the solder resist 15 are patterned with reference to the center of the light emitting portion or the center 10 of the light receiving portion of the optical element chip 3 already mounted and arranged. Since these patterning are photolithography techniques, the mutual positional relationship between the electrode pad 11 and the center of the light emitting portion or the center of the light receiving portion 10 of the optical element chip 3 can be accurately controlled.

The optical element chip 3 is formed on the optical element chip 3 instead of the light emitting section center or the light receiving section center 10 of the optical element chip 3.
The electrode pads 11 for solder bumps and the solder resist 15 may be patterned based on an alignment marker having a fixed relative positional relationship with the center of the light emitting unit or the center of the light receiving unit 10. In this case, if the alignment marker is considered as an auxiliary reference, the patterning is the same as the patterning using the center of the light emitting portion or the center of the light receiving portion 10 of the optical element chip 3 as the alignment reference, and is the same as in the above embodiment. It goes without saying that the action and effect of

Even if an advanced mounting technique such as a flip chip is used, the position of the bump electrode does not exactly match the optical element due to the low positional accuracy at the time of electrical connection via and bonding. The method of manufacturing a semiconductor device is applied in exactly the same manner even when flip-chip mounting is adopted in consideration of high-frequency characteristics, and the same effects as described above are realized.

As is apparent from the above description, according to the present invention, when manufacturing a semiconductor device having an optical signal input / output mechanism, the relative positional relationship between an optical element and a solder bump can be accurately determined. Since the semiconductor device can be manufactured while being held, the mounting accuracy of the optical element can be greatly improved. Therefore, without using expensive technology such as flip chip, using inexpensive technology such as die bonding,
A semiconductor device having a highly efficient optical signal input / output mechanism can be manufactured at low cost.

[0053]

According to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device which inputs and outputs optical signals with high efficiency.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device having an optical signal input / output mechanism according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating patterning of an electrode pad for a solder bump and a solder resist in the embodiment of the present invention.

FIG. 3 is a diagram schematically showing a structure of a conventional semiconductor device having an optical signal input / output mechanism.

FIG. 4 is a diagram schematically illustrating a conventional method of manufacturing a semiconductor device having an optical signal input / output mechanism.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Electric wiring pattern, 2 ... Carrier board, 3 ... Optical element chip, 4 ... Interposer board, 5 ... Via hole,
6 ... LSI chip, 7 ... BGA package, 8, 8 '...
Resin, 9 microlens, 10 light emitting unit center or light receiving unit center, 11 electrode pad for solder bump, 12 solder pad, 13 via, 14 electrode land for solder bump, 15 solder resist, 16 cavity , 17 ...
Cavity bottom, 18: cavity bottom, 19: wire bonding.

Claims (2)

[Claims] A step of adhering an interposer substrate having a via hole to a carrier substrate for mounting an element chip; a step of arranging an optical element chip on a surface of the carrier substrate exposed in the via hole; A step of sealing the optical element chip with a resin transparent to light for transmitting and receiving an optical signal to and from the element chip; a step of forming an electrode pad for solder bumps on the interposer substrate; Mounting a solder bump on an electrode pad, wherein in the step of forming the solder bump electrode pad on the interposer substrate, the position of the solder bump electrode pad is adjusted by the light. A method of manufacturing a semiconductor device, characterized in that the center of the light emitting portion or the center of the light receiving portion of the element chip is determined as a reference . 2. The semiconductor device according to claim 1, wherein a microlens is formed at a position on the surface of the resin which is determined with reference to a center of a light emitting portion or a center of a light receiving portion of the optical element chip. Method.