JP2002334995A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the structure of a TFT being optimum to the drive conditions of a pixel section and a drive circuit using a small number of photomasks. SOLUTION: First to third semiconductor films are formed on a first insulation film; first to third electrodes having a first shape are formed on the first to third semiconductor films; a one conductivity-type impurity region, having first concentration, is formed in the first to third semiconductor films by first doping treatment with the first to third electrodes having the first shape as a mask; first to third electrodes, having a second shape are formed by the first to third electrodes having the first shape; a one conductivity-type impurity region that overlaps with the second electrode with the second shape and has second concentration is formed in the second semiconductor films by a second doping treatment; a one conductivity-type impurity region having third concentration is formed in the first and second semiconductor films; and fourth and fifth conductive type impurity regions which are opposite to the one conductivity-type ones are formed in the third semiconductor film by third doping treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device using a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor film having a crystal structure formed on a substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art In various semiconductor devices such as a television receiver, a personal computer, and a cellular phone, each having a built-in semiconductor element, a display for displaying characters and images is indispensable as a means for humans to recognize information. ing. A CRT is known as a typical display conventionally used, but recently, a flat panel display (flat panel display) represented by a liquid crystal display device has been used to reduce the weight and size of an electronic device. Its share is increasing dramatically.

As one form of the flat panel display, there is known an active matrix driving system in which a TFT is provided for each pixel or dot and a video signal is displayed by sequentially writing data signals. The TFT is an essential element for realizing the active matrix driving method.

[0004] Most TFTs are manufactured using amorphous silicon, but since the TFTs cannot operate at high speed, they have been used only as switching elements provided for each dot. A data line side driving circuit that outputs a video signal to a data line and a scanning line side driving circuit that outputs a scanning signal to a scanning line include TAB (Tape Automated Bonding) and C
It is covered by an external IC (driver IC) mounted by OG (Chip on Glass).

However, as the pixel density increases, the pixel pitch becomes narrower, and it is considered that there is a limit to the method of mounting the driver IC. For example, assuming UXGA (1200 × 1600 pixels), the RGB color system requires 6000 connection terminals even if simply estimated. An increase in the number of connection terminals causes an increase in the probability of occurrence of contact failure. In addition, the area (frame area) in the peripheral portion of the pixel portion increases, which causes a reduction in the size and appearance of a semiconductor device using the semiconductor device as a display.
From such a background, the necessity of a display device integrated with a driving circuit has become clear. By integrally forming the pixel portion and the driving circuits on the scanning line side and the data line side on the same substrate, the number of connection terminals can be drastically reduced, and the area of the frame region can be reduced.

However, the driving circuit is a high driving ability (the on current, I _on) while it is required to improve the reliability to prevent deterioration due and hot carrier effect, the pixel unit is low off-current (I _off) is determined Have been. As a TFT structure for reducing an off current value, a lightly doped drain (LDD) structure is known. In this structure, an LDD region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. Also, as an effective structure for preventing the deterioration of the on-current value due to hot carriers, an LDD structure in which a part of an LDD region overlaps with a gate electrode (hereinafter, gate-draft structure).
in Overlapped LDD is abbreviated to GOLD).

[0007]

A TFT is manufactured by laminating a semiconductor film, an insulating film, or a conductive film while etching into a predetermined shape using a photomask. However, according to the requirements of the pixel portion and each drive circuit, the TF
If the number of photomasks is simply increased in order to optimize the structure of T, the manufacturing process becomes complicated and the number of processes inevitably increases.

An object of the present invention is to solve such a problem, and to optimize a TF suitable for driving conditions of a pixel portion and a driving circuit.
An object of the present invention is to provide a technique for realizing the structure of T with a small number of photomasks.

[0009]

In order to solve the above problems, the present invention provides a two-layered gate electrode having a different length in the channel length direction and a longer first layer in contact with the gate insulating film. The n-channel type TFT in the drive circuit portion uses the gate electrode having the two-layer structure to form the source / drain region and the LDD region in a self-aligned manner. Is used to form the source and drain regions and the LDD regions in a non-self-aligned manner. Further, the LDD region of the n-channel TFT in the drive circuit portion is provided at a position overlapping with the gate electrode, and the LDD region is provided outside the gate electrode (does not overlap with the gate electrode) in the n-channel TFT of the pixel portion. Structure.
The two types of LDD regions and the source and drain regions having different arrangement relationships from the gate electrode are formed by two doping processes.

As described above, in the method for manufacturing a semiconductor device according to the present invention, the first to third semiconductor films separated from each other are formed on the first insulating film, and the first to third semiconductor films are formed. A first electrode, a first electrode, a third electrode, and a third electrode having a first shape are formed on the first electrode, a third electrode, and a third electrode, respectively.
Using the electrode as a mask, a first concentration one-conductivity-type impurity region is formed in the first semiconductor film to the third semiconductor film by the first doping process, and the second electrode is formed from the first shape first electrode to the third electrode.
Forming a first electrode to a third electrode having a second shape, forming a second concentration one-conductivity-type impurity region overlapping with the second electrode having the second shape in the second semiconductor film by a second doping process;
A third concentration one conductivity type impurity region is formed in the semiconductor film and the second semiconductor film, and the third doping process causes the third semiconductor film to have a fourth impurity region and a fifth impurity region having a conductivity type opposite to the one conductivity type.
And a step of forming an impurity region. That is, an LDD and a source or drain region are formed in a self-aligned manner by combining an etching process and a doping process for forming a gate electrode of a TFT.

Further, as another configuration, a first semiconductor film to a third semiconductor film separated from each other are formed on a first insulating film, and a first electrode having a first shape is formed on the first semiconductor film. A first-concentration one-conductivity-type impurity region is formed on the first semiconductor film using the first-shaped first electrode as a mask, and is formed on the second semiconductor film and the third semiconductor film. A first shape second electrode and a third electrode are formed with a second insulating film interposed therebetween, and the first shape second electrode and the third electrode are etched to form a second shape.
Forming a second electrode and a third electrode having a second shape, forming a second concentration one-conductivity-type impurity region overlapping the second electrode having a second shape in the second semiconductor film by a second doping process; A third concentration one-conductivity-type impurity region is formed in the semiconductor film and the second semiconductor film, and a third doping process causes the third semiconductor film to have a fourth impurity region and a fifth impurity having a conductivity type opposite to the one-conductivity type. It is characterized by having a step of forming a region.

According to such a manufacturing method, an n-channel TFT formed in a drive circuit can be formed by an LDD overlapping with a gate electrode.
Are formed in a self-aligned manner. This LDD can be performed in the same doping step at the same time as the source or drain region by doping using the thickness difference (step) of the gate electrode. On the other hand, an n-channel TFT formed in a pixel portion is formed by using an LDD which does not overlap with a gate electrode by using a mask.

The term "semiconductor device" as used in the present invention refers to any device that functions by utilizing semiconductor characteristics, such as a display device represented by a liquid crystal display device having a built-in TFT, a semiconductor integrated circuit (microprocessor, signal processing circuit). Or a high-frequency circuit).

[0014]

[First Embodiment] An embodiment of the present invention will be described with reference to FIGS. Here, a pixel portion and a TFT of a driving circuit provided near the pixel portion are provided over the same substrate.
A method for simultaneously manufacturing (an n-channel TFT and a p-channel TFT) will be described in detail.

In FIG. 1A, a substrate 101 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature in this embodiment mode may be used.

First, a first insulating film 102 is formed on a substrate 101,
103 is formed. Although shown here with a two-layer structure,
Of course, only one layer may be used. The semiconductor films 104 to 107 are formed using a semiconductor having a crystal structure. This is obtained by crystallizing the amorphous semiconductor film formed on the first insulating film. After the amorphous semiconductor film is deposited, it is crystallized by heat treatment or laser light irradiation. Without limitation on the material of the amorphous semiconductor film, preferably silicon or silicon germanium _{(Si x Ge 1-x;} 0 <x <1, typically, x = 0.0
01-0.05) It is formed of an alloy or the like.

In order to crystallize the amorphous semiconductor film by irradiating a laser beam, a pulse oscillation type or continuous oscillation gas laser or solid laser is applied. An excimer laser such as KrF, ArF, or XeCl is applied as a gas laser. YAG, YVO ₄ , YLF, YAlO ₃
Cr, Nd, Er, Ho, Ce, Co, T
A laser oscillation device using a crystal doped with i or Tm is applied. The fundamental wavelength of the oscillation wavelength varies depending on the material to be doped, but oscillates at a wavelength of 1 μm to 2 μm. To crystallize the amorphous semiconductor film, a laser beam having a wavelength in the visible region to the ultraviolet region is applied to selectively absorb the laser beam in the semiconductor film, and the second to fourth harmonics of the fundamental wave are applied.
Preferably, harmonics are applied. Typically, the second harmonic (532 nm) of a Nd: YVO ₄ laser oscillation device (fundamental wave 1064 nm) is used for crystallization of the amorphous semiconductor film. In addition, a gas laser oscillation device such as an argon laser oscillation device and a krypton laser oscillation device can be applied.

As a crystallization method, a metal element having a catalytic action on crystallization of a semiconductor such as nickel may be added for crystallization. For example, after a nickel-containing solution is held on an amorphous silicon film, dehydrogenation (500 ° C., 1 hour) and thermal crystallization (550 ° C., 4 hours) are performed to further improve crystallinity. For this purpose, a second harmonic of continuous wave laser light selected from a YAG laser, a YVO ₄ laser and a YLF laser is applied.

Next, a second insulating film 108 covering the semiconductor films 104 to 107 is formed. The second insulating film 108 is formed using an insulator containing silicon by a plasma CVD method or a sputtering method. Its thickness is 40-150 nm. Semiconductor film 1
The second insulating film formed to cover 04 to 107 is used as a gate insulating film of a TFT manufactured in this embodiment mode.

A conductive film is formed on the second insulating film 108 to form a gate electrode and a wiring. In the present invention, a gate electrode is formed by stacking two or more conductive films. The first conductive film 109 formed on the second insulating film 108 is formed of a nitride of a refractory metal such as molybdenum or tungsten, and the second conductive film 110 formed thereon is formed of a refractory metal or a refractory metal such as aluminum or copper. It is formed of a low-resistance metal or polysilicon. Specifically, one or more nitrides selected from W, Mo, Ta, and Ti are selected as the first conductive film, and W, Mo, Ta, and T are selected as the second conductive film.
One or more alloys selected from i, Al, and Cu, or n-type polycrystalline silicon is used.

Next, as shown in FIG. 1B, resist masks 111 to 114 are formed, and a first etching process is performed on the first conductive film and the second conductive film. By this etching process, the first shape electrode 1 having a tapered end portion
16 to 118 and the first shape wirings 114 and 115 are formed. The taper is formed at 45 to 75 degrees. The surface of the second insulating film 122 that is not covered with the first shape electrodes 116 to 118 and the first shape wirings 114 and 115 is etched to about 20 to 50 nm to form a thinned region.

The first doping process is performed by an ion implantation method or an ion doping method of implanting ions without mass separation. Doping is the first shape of the electrodes 116-118
Is used as a mask to form first conductivity type impurity regions 123 to 126 in the semiconductor films 104 to 107. The first concentration is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ .

Next, a second etching process is performed as shown in FIG. 2A without removing the resist masks 111 to 114. In this etching process, the second conductive films are anisotropically etched to form second shape electrodes 127 to 129 and second shape wirings 130 and 131. Second shape electrode 12
The surface of the second insulating film, which is not covered with the wirings 130 and 131 and the second shape wirings 130 and 131, is etched and thinned by about 20 to 50 nm.

Thereafter, a mask 133 covering the entire semiconductor film 104, a mask 134 covering the second shape electrode 129 on the semiconductor film 106, and a mask 134 covering the semiconductor film 107 are provided.
Is formed and a second doping process is performed. A second doping process is performed to form a second concentration one conductivity type impurity region in the semiconductor film 105 and a third concentration one conductivity type impurity region in the semiconductor films 105 and 106.

The second concentration one-conductivity type impurity region 135 is
It is formed in a self-aligned manner at a position overlapping with the first conductive film 128a constituting the second shape electrode 128. Since the impurity added by the ion doping method is added by passing through the first conductive film 128a, the number of ions reaching the semiconductor film is reduced, and is necessarily lower than that of the third concentration n-type impurity region. . Its concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .
The third concentration impurity regions 136 and 137 are 1 × 10 ^20.
An n-type impurity is added at a concentration of about 1 × 10 ²¹ / cm ³ .

Next, as shown in FIG. 3A, a resist mask 138 is formed, and a third doping process is performed. As a result of the third doping treatment, the semiconductor film 104 has an impurity region 139 having a conductivity type opposite to the fourth concentration of one conductivity type and an impurity region 140 having a fifth concentration having a conductivity type opposite to the one conductivity type.
To form The impurity region of a conductivity type opposite to the fourth one conductivity type is formed in a region overlapping with the second shape electrode 127, and is formed in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. Elements are added. This impurity concentration becomes an impurity concentration that can function as an LDD. The fifth concentration is set so that the impurity element is added to 140 in a concentration range of 2 × 10 ^{20 to} 3 × 10 ²¹ / cm ³ .

Through the steps described above, regions in which impurities for controlling valence electrons are added to the respective semiconductor films are formed. The second shape electrodes 127 to 129 serve as gate electrodes. In addition, the second shape wiring 130 is one electrode forming a storage capacitor in the pixel portion. Further, the second shape wiring 131 forms a data line in the pixel portion.

Next, a third insulating film 143 is formed by a plasma CVD method or a sputtering method. Third insulating film 143
Is formed using a silicon oxynitride film, a silicon oxide film, or the like.

Thereafter, as shown in FIG. 3B, a step of activating the impurity element added to each semiconductor film is performed. This activation is performed using a furnace annealing furnace or a rapid thermal annealing (RTA) method. The temperature of the heat treatment is 400 to 700 ° C. in a nitrogen atmosphere, typically 45 ° C.
Perform at 0-500 ° C. In addition, the second YAG laser
A laser annealing method using a harmonic (532 nm) can also be applied. In order to perform activation by laser light irradiation, the semiconductor film is irradiated with this light using the second harmonic (532 nm) of a YAG laser. Of course, not only the laser light but also the RTA method using a lamp light source is the same, and the semiconductor film is heated by radiation of the lamp light source from both sides or the substrate side of the substrate.

Thereafter, as shown in FIG.
The fourth insulating film 144 made of silicon nitride is
Formed to a thickness of 100 nm and 4 using a clean oven
A heat treatment at 10 ° C. is performed, and the semiconductor film is hydrogenated with hydrogen released from the silicon nitride film.

Next, a fifth insulating film 145 made of an organic insulating material is formed on the fourth insulating film 144. The reason for using the organic insulator material is to flatten the outermost surface of the fifth insulating film. Then, a contact hole penetrating the third to fifth insulating films is formed by etching. In this etching process, the third and fifth insulating films of the external input terminal are also removed. Then, wirings 146 to 149 formed by stacking a titanium film and an aluminum film, pixel electrodes 151, scanning lines 152, connection electrodes 150, and wirings 153 connected to external input terminals are formed.

In the above steps, if the one conductivity type impurity region is n-type and the impurity region opposite to the one conductivity type is p-type, the p-channel TFT 200 and the first n-type
A driver circuit 205 including the channel TFT 201 and a pixel portion 206 including the second n-channel TFT 203 and the capacitor portion 204 can be formed. An insulating film formed of the semiconductor film 107 and the second insulating film 122;
It is formed of the first shape capacitor wiring 130.

The p-channel TFT 20 of the driving circuit 205
In a region 0, a fifth concentration p-type impurity region 14 is formed outside the channel formation region 154 and the second electrode 127 forming the gate electrode.
0 (region functioning as source region or drain region)
And a fourth concentration p-type impurity region (LDD) overlapping the second electrode 127.

The first n-channel TFT 201 has a second concentration n-type impurity region 124 (LD) overlapping the channel formation region 155 and the second shape electrode 128 forming the gate electrode.
D) and a third concentration n-type impurity region 135 functioning as a source region or a drain region. The length of the LDD in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. The configuration of such an LDD is
The main purpose is to prevent TFT deterioration due to the hot carrier effect. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed using the n-channel TFT and the p-channel TFT. In particular, the structure of the first n-channel TFT 201 is suitable for a buffer circuit with a high driving voltage, for the purpose of preventing deterioration due to the hot carrier effect.

The second n-channel TFT 2 of the pixel unit 206
03 has a channel formation region 156, a first concentration one conductivity type impurity region 125 formed outside the second shape electrode 129 forming a gate electrode, and a third one conductivity type impurity region serving as a source region or a drain region. It has an impurity region 136. In the semiconductor film 107 functioning as one electrode of the capacitor portion 204, impurity regions 141 and 142 of a conductivity type opposite to one conductivity type are formed.

In the pixel portion 206, reference numeral 151 denotes a pixel electrode, and reference numeral 150 denotes a connection electrode for connecting the data line 131 and the third concentration n-type impurity region 136 of the semiconductor film 106. Reference numeral 152 denotes a gate wiring, which is not shown in the figure, and is connected to the second-shaped electrode 129 functioning as a gate electrode.

As described above, according to the present invention, the first n-channel TFT formed of the one conductivity type impurity region having the LDD overlapping the gate electrode and the second n-channel TFT not overlapping the gate electrode are provided.
It is possible to form an n-channel TFT on the same substrate. The appropriate arrangement of these TFTs can be determined in accordance with circuits having different operating conditions such as a driving circuit portion and a pixel portion. On the other hand, a p-channel TFT is formed with an LDD that overlaps with a gate electrode.

The drive circuit section 20 formed in the present embodiment
5. The substrate including the pixel portion 206 is referred to as an active matrix substrate for convenience. Using such an active matrix substrate, a display device driven by active matrix can be formed. In this embodiment, since the pixel electrode is formed of a light-reflective material, a reflective display device can be formed by applying the present invention to a liquid crystal display device. From such a substrate, a liquid crystal display device or a light emitting device in which a pixel portion is formed using an organic light emitting element can be formed.

Second Embodiment Another embodiment of the present invention will be described below with reference to FIGS. Here, a pixel portion and a driving circuit TFT (an n-channel TFT and a p-channel TFT) provided around the pixel portion are provided over the same substrate.
Will be described in detail.

In FIG. 7A, a substrate 301, first insulating films 302 and 303, semiconductor films 304 to 307, a second insulating film 308, a first conductive film 309, and a second conductive film 310 are the same as those in the embodiment. It is assumed that

In FIG. 7B, masks 311 and 312 are formed. The mask 311 is a mask that covers the driving circuit portion, and the mask 312 is a mask that is formed in the pixel portion. In this state, a first etching process is performed, and the first conductive film and the second conductive film are etched to form first-shaped electrodes 313 and first-shaped wirings 314 and 315 (these are first conductive films). Films 313a to 315a and second conductive film 3
13b to 315b). Next, a first doping process is performed to add one conductivity type impurity to the semiconductor films 306 and 307, thereby forming the first concentration one conductivity type impurity regions 316 and 313.
Form 60.

After removing the masks 311 and 312, FIG.
As shown in FIG. 3A, a mask 317 which covers the first shape electrode 313 and the first shape wirings 314 and 315 is formed. Further, masks 318 to 320 are formed in the drive circuit portion, and the first shape electrode 3 is formed in the drive circuit portion by a second etching process.
21 to 323 are formed.

The first etching process and the second etching process both etch the first conductive film and the second conductive film,
A taper of 45 to 75 degrees is formed at the end.

Following the second etching process, FIG.
A third etching process is performed as shown in FIG. The third etching process is for selectively etching the second conductive film, and the second shape electrodes 324 to 326 are formed. The electrode of the second shape is in a state in which a protrusion is formed by the first conductive films 324a to 326a.

Using the electrodes 324 and 325 of the second shape, the first conductive films 324 a and 325 a and the second conductive film 324 are formed.
Utilizing the difference in film thickness between B and 325b, impurity regions of one conductivity type are formed in the semiconductor films 304 and 305 by the second doping process. Second concentration one conductivity type impurity regions 330, 3
Numeral 31 is formed at a position overlapping the second shape electrode, and the third concentration one conductivity type impurity regions 327 and 328 are formed in regions outside thereof. Further, a third concentration one conductivity type impurity region 329 is also formed in the semiconductor film 306.

Thereafter, as shown in FIG. 9A, masks 332 and 333 are formed, and an impurity of a conductivity type opposite to the one conductivity type is added to the semiconductor film 304 by a third doping process to form a fourth mask. An impurity region 335 having a concentration opposite to the one conductivity type and an impurity region 334 having a fifth concentration and a conductivity type opposite to the one conductivity type are formed. Further, the impurity region 33 of the conductivity type opposite to the one conductivity type of the fifth concentration is also formed in the semiconductor film 307.
6 is formed.

Thereafter, the third insulating film 3 is formed in the same manner as in the first embodiment.
37 is formed, and activation treatment of impurities added to the semiconductor film is performed.

Thereafter, as shown in FIG. 10, a fourth insulating film 338 is formed, and a heat treatment at 410 ° C. is performed to hydrogenate the semiconductor film. Next, a fifth insulating film 339 made of an organic insulating material is formed over the fourth insulating film 338. The reason for using the organic insulator material is to flatten the outermost surface of the fifth insulating film. Then, the third to fifth layers are etched.
A contact hole penetrating the insulating film is formed. Wiring 3
40 to 343, a pixel electrode 345, a gate line 346, and wirings 344 and 347 are formed.

In the above steps, if the one conductivity type impurity region is n-type and the impurity region opposite to the one conductivity type is p-type, the p-channel TFT 400 and the first n-type
A driver circuit 405 including the channel TFT 401 and a pixel portion 406 including the second n-channel TFT 403 and the capacitor portion 404 can be formed. An insulating film formed of the semiconductor film 307 and the second insulating film 361;
It is formed of the first shape capacitor wiring 314.

The p-channel TFT 40 of the driving circuit 405
In FIG. 5, the impurity region 332 of the conductivity type opposite to the one conductivity type of the fourth concentration is located at a position overlapping the channel formation region 348 and the second electrode 324 forming the gate electrode, and the fifth concentration is located outside the second electrode 324. It has an impurity region 333 of a conductivity type opposite to the one conductivity type.

The first n-channel TFT 401 has a second concentration of one conductivity type impurity region 331 overlapping the channel formation region 349 and the second shape electrode 325 forming the gate electrode.
(LDD region) and a third-concentration one-conductivity-type impurity region 328 functioning as a source region or a drain region. The length of the LDD in the channel length direction is 0.5 to 2.5.
μm, preferably 1.5 μm. LD like this
The configuration of the D region is mainly based on the hot carrier effect TFT
The purpose is to prevent the deterioration of the. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed using the n-channel TFT and the p-channel TFT. In particular, the structure of the first n-channel TFT 401 is suitable for a buffer circuit with a high drive voltage, for the purpose of preventing deterioration due to the hot carrier effect.

The second n-channel TFT 4 of the pixel portion 406
03 includes a channel formation region 350, a first concentration one conductivity type impurity region 316 formed outside the first shape electrode 313 forming a gate electrode, and a third concentration one concentration impurity region 316 functioning as a source region or a drain region. Conductivity type impurity region 32
9. In the semiconductor film 307 functioning as one electrode of the capacitor portion 404, an impurity region 336 having a conductivity type opposite to the first conductivity type of the fifth concentration is formed.

As described above, in this embodiment, the TFTs having different LDD structures are formed by making the structures of the gate electrode of the drive circuit portion and the gate electrode of the pixel portion different. The LDD overlapping with the gate electrode is formed in a self-aligned manner, and can be accurately formed without using a photomask.

[0054]

[Embodiment 1] An embodiment of the present invention is described below with reference to FIG.
This will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and a TFT (an n-channel TFT and a p-channel TFT) of a driver circuit provided around the pixel portion over the same substrate will be described in detail.

In FIG. 1A, a substrate 101 is made of aluminum.
Noborosilicate glass is used. On this substrate 101, the first
An insulating film is formed. In this embodiment, SiH_Four, NH_Threeas well as
N_TwoFirst silicon oxynitride film formed by using O as a reaction gas
50 nm, SiH _FourAnd N_TwoO as the reaction gas
100 nm of the second silicon oxynitride film 103
To a thickness of.

The semiconductor films 104 to 107 are formed of a semiconductor having a crystal structure. This is formed by forming a non-crystalline semiconductor film on the first insulating film and then using a known crystallization method. In this embodiment, after an amorphous silicon film is deposited to a thickness of 50 nm, an excimer laser beam is condensed linearly by an optical system, and is irradiated for crystallization. The power density of the laser beam is 300 mJ / cm ² and the thickness is 500 μm.
A linear laser beam of m is irradiated over the entire surface of the amorphous silicon film while being superimposed at a rate of 90 to 98%.

As another means, a continuous oscillation type YVO
_Fourth laser may be used to convert to a second harmonic by a wavelength conversion element, and may be crystallized by scanning an energy beam of 10 W at a speed of 1 to 100 cm / sec.

After the crystallization, boron is added to the semiconductor film by an ion doping method as an acceptor-type impurity in order to control the threshold voltage of the TFT. The concentration to be added may be appropriately determined by the practitioner.

The polycrystalline silicon film thus formed is divided into islands by etching, and
107 is formed. A 110-nm-thick silicon oxynitride film formed by a plasma CVD method using SiH ₄ and N ₂ O is formed thereon as the second insulating film 108.

Further, a 30 nm thick tantalum nitride film is formed as the first conductive film 109 on the second insulating film 108 by a sputtering method, and a 300 nm thick tungsten film is formed as the second conductive film 110.

The thickness of the tantalum nitride film is determined in consideration of the doping efficiency of phosphorus used as an n-type impurity in the ion doping method (or the ability of the tantalum nitride film to block phosphorus). FIG. 30 shows the phosphorus concentration distribution when the thickness of the tantalum nitride film is changed to 15 to 45 nm while keeping the gate insulating film thickness constant. The accelerating voltage in doping is 90 keV. The concentration of phosphorus implanted into a semiconductor film changes depending on the thickness and material of a film (gate insulating film or tantalum nitride film) thereover. FIG. 31 shows a profile obtained by converting the thickness of the tantalum nitride film into the thickness of the gate insulating film. Thus, when the thickness of the tantalum nitride film as viewed from the ability to block phosphorus is converted into the thickness of the gate insulating film, it becomes 2.4 to 2.66 times. In other words, it can be seen that the tantalum nitride film has a higher phosphorus blocking ability even if it is thinner.

The thickness of the tantalum nitride film is determined in consideration of the resistance value and the anti-doping ability.
Referring to FIGS. 30 and 31, it can be considered that 15 nm to 300 nm is the most suitable range.

Next, as shown in FIG. 1B, masks 111 to 114 are formed using a photosensitive resist material. Then, a first etching process is performed on the first conductive film 109 and the second conductive film 110. IC for etching
A P (Inductively Coupled Plasma) etching method is used. The etching gas is not limited, but CF ₄ , Cl _2, and O ₂ are used for etching the W film and the tantalum nitride film. Each gas flow rate is 25: 2
5:10, 500W to coil type electrode at 1Pa pressure
RF (13.56 MHz) power is applied to perform etching. In this case, 150W also on the substrate side (sample stage)
(13.56 MHz), and a substantially negative self-bias voltage is applied. Under the first etching condition, the W film is mainly etched into a predetermined shape.

Thereafter, the etching gases are CF ₄ and Cl ₂
And the respective gas flow ratios are 30:30, and 1
At a pressure of Pa, a 500 W RF (13.5
(6 MHz) Power is supplied to generate plasma, and etching is performed for about 30 seconds. 2 on substrate side (sample stage)
Apply 0 W RF (13.56 MHz) power and apply a substantially negative self-bias voltage. The mixed gas of CF ₄ and Cl ₂ etches the tantalum nitride film and the W film at substantially the same rate. Thus, the first shape electrodes 116 to 118 having the tapered ends and the first shape wirings 114 and 115 are provided.
To form The taper is formed at 45 to 75 degrees. still,
In order to perform etching without leaving a residue on the second insulating film, it is preferable to increase the etching time by about 10 to 20%. Second insulating film 122 not covered by first shape electrodes 116 to 118 and first shape wirings 114 and 115
Is thinned by etching about 20 to 50 nm on the surface.

The first doping process is performed by an ion doping method in which ions are implanted without performing mass separation. Doping is performed by using the first shape electrodes 116 to 118 as a mask, using phosphine (PH ₃ ) gas diluted with hydrogen or phosphine gas diluted with a rare gas, and forming the semiconductor films 104 to 118.
At 107, first concentration n-type impurity regions 123 to 126 are formed. The phosphorus concentration of the first concentration n-type impurity region formed by this doping is set to 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ .

Next, without removing the masks 111 to 114, a second etching process is performed as shown in FIG. Using CF ₄ , Cl _2, and O _{2 as} etching gases, the respective gas flow ratios were set to 20:20:20, and 500 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa. To generate plasma to perform etching. 20 W RF (13.56 MHz) on the substrate side (sample stage)
Power is applied and a lower self-bias voltage is applied than in the first etching process. The W film used as the second conductive film is etched under these etching conditions. Thus, the W film is anisotropically etched to form electrodes 127 to 129 of the second shape.
Then, wirings 130 and 131 of the second shape are formed. Second shape electrodes 127 to 129 and second shape wires 130 and 13
The surface of the second insulating film that is not covered with 1 is etched by about 20 to 50 nm and becomes thin.

Thereafter, a mask 133 covering the entire semiconductor film 104, a mask 134 covering the second shape electrode 129 on the semiconductor film 106, and a mask 134 covering the semiconductor film 107 are provided.
Is formed and a second doping process is performed. A second doping process is performed to form a second concentration n-type impurity region in the semiconductor film 105 and a third concentration n-type impurity region in the semiconductor films 105 and 106. The ion doping method is performed using phosphine at a dose of 1.5 × 10 ¹⁴ / cm ³ and an acceleration voltage of 100 keV.

The second concentration n-type impurity region 135 is
It is formed in a self-aligned manner at a position overlapping with the first conductive film 128a constituting the shaped electrode 128. Since the impurity added by the ion doping method is added through the first conductive film 128a, the impurity concentration is much lower than that of the third concentration n-type impurity region, and is 1 × 10 ¹⁶ to 1 × 10 ^17. / cm ³ concentration.
The third concentration impurity regions 136 and 137 are 1 × 10 ^20.
Phosphorus is added to a concentration of about 1 × 10 ²¹ / cm ³ .

Next, as shown in FIG.
38, and a third doping process is performed. For doping, diborane (B ₂ H ₆ ) gas diluted with hydrogen or diborane gas diluted with a rare gas is used.
Impurity region 139 and fifth concentration p-type impurity region 14
0 is formed. The fourth p-type impurity region is the second shape electrode 1
27, and is formed in a region overlapping with 1 × 10 ¹⁸
Boron is added in a concentration range of about 1 × 10 ²⁰ / cm ³ , and boron is added to the fifth impurity region 140 in a concentration range of 2 × 10 ^{20 to} 3 × 10 ²¹ / cm ³ . The fifth concentration p-type impurity region 142 and the fourth concentration p-type impurity region 141
Is formed on the semiconductor film 107 forming a storage capacitor in the pixel portion.

Through the steps described above, regions to which phosphorus or boron is added are formed in the respective semiconductor films. The second shape electrodes 127 to 129 serve as gate electrodes. In addition, the second shape wiring 130 is one electrode forming a storage capacitor in the pixel portion. Further, the second shape wiring 131 forms a data line in the pixel portion.

Next, a third insulating film 143 having a thickness of 50 nm is formed using a silicon oxynitride film by a plasma CVD method. Thereafter, as shown in FIG. 3B, the semiconductor film is irradiated with this laser light using the second harmonic (532 nm) of a YAG laser in order to activate the impurity element added to each semiconductor film. I do.

Thereafter, as shown in FIG.
The fourth insulating film 144 made of silicon nitride is formed to a thickness of 50 nm by the D method.
And heat-treated at 410 ° C. using a clean oven to hydrogenate the semiconductor film with hydrogen released from the silicon nitride film.

Next, a fifth insulating film 145 is formed on the fourth insulating film 144 using acrylic. Then, a contact hole is formed. In this etching process, the third and fifth insulating films of the external input terminal are also removed. Then, wirings 146 to 146 formed by stacking a titanium film and an aluminum film are formed.
149, pixel electrode 151, scanning line 152, connection electrode 15
0, a wiring 153 connected to the external input terminal is formed.

As described above, the driving circuit 205 having the p-channel TFT 200 and the first n-channel TFT 201 on the same substrate, and the second n-channel TFT 203
And a pixel portion 206 having a capacitor portion 204 can be formed. The capacitance portion 204 includes the semiconductor film 107 and the second insulating film 1
The insulating film 22 is formed of a first-shaped capacitor wiring 130.

The p-channel TFT 20 of the driving circuit 205
In a region 0, a fifth concentration p-type impurity region 14 is formed outside the channel formation region 154 and the second electrode 127 forming the gate electrode.
0 (region functioning as source region or drain region)
And a fourth concentration p-type impurity region overlapping the second electrode 127.

The first n-channel TFT 201 has a second concentration n-type impurity region 124 (LD) overlapping the channel formation region 155 and the second shape electrode 128 forming the gate electrode.
D) and a third concentration n-type impurity region 135 functioning as a source region or a drain region. The length of the LDD in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. The configuration of such an LDD region is intended mainly to prevent TFT deterioration due to the hot carrier effect. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed using the n-channel TFT and the p-channel TFT. In particular, the structure of the first n-channel TFT 201 is suitable for a buffer circuit with a high driving voltage, for the purpose of preventing deterioration due to the hot carrier effect.

The second n-channel type TFT 2 of the pixel unit 206
03 includes a channel formation region 156, a first concentration n-type impurity region 125 formed outside a second shape electrode 129 forming a gate electrode, and a third concentration n-type impurity region serving as a source region or a drain region. It has an impurity region 136. Further, p-type impurity regions 141 and 142 are formed in the semiconductor film 107 functioning as one electrode of the capacitor portion 204.

In the pixel portion 206, reference numeral 151 denotes a pixel electrode, and reference numeral 150 denotes a connection electrode for connecting the data line 131 and the third concentration n-type impurity region 136 of the semiconductor film 106. Reference numeral 152 denotes a gate wiring, which is not shown in the figure, and is connected to the second-shaped electrode 129 functioning as a gate electrode.

FIG. 5 shows a top view of the pixel portion 206. FIG. FIG.
FIG. 4 shows a top view of almost one dot, and the reference numerals shown in FIG.
And have something in common. Further, the cross-sectional structure taken along line AA ′ corresponds to FIG. In the pixel structure in FIG. 5, by forming the gate wiring and the gate electrode on different layers, the gate wiring and the semiconductor film can overlap with each other, and a function as a light-blocking film is added to the gate wiring. Further, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light, so that the formation of the light shielding film (black matrix) can be omitted. As a result, it is possible to improve the aperture ratio as compared with the related art.

As described above, the present invention makes it possible to form an n-channel TFT having an LDD overlapping with a gate electrode and an n-channel TFT that does not overlap on the same substrate. The appropriate arrangement of these TFTs can be determined in accordance with circuits having different operating conditions such as a driving circuit portion and a pixel portion. At this time, the p-channel type T
FT is based on a single drain structure.

FIG. 6 is a circuit block diagram showing an example of the circuit configuration of the active matrix substrate. Pixel portion 601 formed by incorporating TFT, data signal line driving circuit 6
02, a scanning signal line driving circuit 606 is formed.

The data signal line driving circuit 602 includes a shift register 603, latches 604 and 605, and other buffer circuits. A clock signal and a start signal are input to the shift register 603, and a digital data signal and a latch signal are input to the latch. The scanning signal line driving circuit 606 also includes a shift register, a buffer circuit, and the like. Although the number of pixels of the pixel portion 601 is arbitrary, in the case of XGA, 1024 × 768 pixels are provided.

Using such an active matrix substrate, a display device driven by active matrix can be formed. In this embodiment, since the pixel electrode is formed of a light-reflective material, a reflective display device can be formed by applying the present invention to a liquid crystal display device. From such a substrate, a liquid crystal display device or a light emitting device in which a pixel portion is formed using an organic light emitting element can be formed. Thus, an active matrix substrate corresponding to a reflective display device can be manufactured.

Embodiment 2 Another embodiment of the present invention will be described below with reference to FIGS. This embodiment also describes a method for simultaneously manufacturing a pixel portion and a TFT (a n-channel TFT and a p-channel TFT) of a driver circuit provided around the pixel portion over the same substrate. Substrate 3 in FIG.
01, first insulating films 302 and 303, semiconductor films 304 to 3
07, the second insulating film 308, the first conductive film 309, and the second conductive film 310 are the same as those in the first embodiment.

In FIG. 7B, masks 311 and 312 are formed. The mask 311 is a mask that covers the driving circuit portion, and the mask 312 is a mask that is formed in the pixel portion. In this state, the first etching process is performed, and the first shape electrode 3 is formed.
13, forming first shape wirings 314 and 315 (these are first conductive films 313a to 315a and second conductive films 31
3b to 315b). The etching conditions are the same as in the first etching in the first embodiment. Then the first
A doping process is performed, and phosphorus is added to the semiconductor films 306 and 307 by an ion doping method to form first concentration n-type impurity regions 316 and 360. The phosphorus concentration of the first concentration n-type impurity region is set to 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ .

After removing the masks 311 and 312, FIG.
As shown in FIG. 3A, a mask 317 which covers the first shape electrode 313 and the first shape wirings 314 and 315 is formed. Further, masks 318 to 320 are formed in the drive circuit portion, and the first shape electrode 3 is formed in the drive circuit portion by a second etching process.
21 to 323 are formed. The conditions of the second etching process are the same as those of the first etching process of this embodiment.

Subsequently, a third etching process is performed as shown in FIG. The third etching process is for selectively etching the W film formed as the second conductive film. As a result, it is possible to form the second shape electrodes 324 to 326 in which the projections formed by the first conductive films 324a to 326a are formed. This etching condition can be performed under the same condition as the second etching process of the first embodiment.

Using the electrodes 324 and 325 of the second shape
The first conductive films 324a and 325a and the second conductive film 324
b, the second doping process using the difference in film thickness of 325b
To add n-type impurities to the semiconductor films 304 and 305.
Form a pure region. PH diluted to 5% with hydrogen_ThreeFor
The dose is 1.6 × 10¹⁴/cm^ThreeAnd the accelerating voltage is 1
By performing the process at 00 keV,
Two concentration n-type impurity regions 330 and 331 and a third concentration n
Type impurity regions 327 and 328 can be formed.
The second concentration n-type impurity regions 330 and 331 have the second shape.
Formed at a position overlapping with the electrode, and due to the presence of the first conductive film
The concentration of phosphorus added is 1 × 10¹⁶~ 1 × 10 ¹⁷/cm^ThreeTona
You. The third concentration n-type impurity regions 327 and 328
And the concentration of phosphorus to be added is 1 × 10²⁰~ 1
× 10^{twenty one}/cm^ThreeAnd Also, the third concentration is applied to the semiconductor film 306.
The n-type impurity region 329 is formed.

Then, as shown in FIG. 9A, masks 332 and 333 are formed, boron is added to the semiconductor film 304 by a third doping process, and a fourth concentration p-type impurity region 335 and a fourth concentration are formed. A five-concentration p-type impurity region 334 is formed. Also, a fifth concentration p-type impurity region 336 is formed in the semiconductor film 307.

The subsequent steps are performed in the same manner as in the first embodiment. A third insulating film 337 is formed, and activation of impurities added to the semiconductor film is performed. Thereafter, as shown in FIG.
38 is formed, and heat treatment at 410 ° C. is performed to hydrogenate the semiconductor film. Next, a fifth insulating film 339 made of an organic insulating material is formed over the fourth insulating film 338. Then, a contact hole is formed by an etching process. Wiring 3
40 to 343, a pixel electrode 345, a gate line 346, and wirings 344 and 347 are formed.

As described above, the driving circuit 405 having the p-channel TFT 400 and the first n-channel TFT 401 on the same substrate and the second n-channel TFT 403
And a pixel portion 406 having a capacitor portion 404 can be formed. The capacitor 404 is composed of the semiconductor film 307 and the second insulating film 3
An insulating film formed by 61 and a first shape capacitor wiring 314 are formed.

The p-channel TFT 40 of the driving circuit 405
In FIG. 5, the impurity region 332 of the conductivity type opposite to the one conductivity type of the fourth concentration is located at a position overlapping the channel formation region 348 and the second electrode 324 forming the gate electrode, and the fifth concentration is located outside the second electrode 324. It has an impurity region 333 of a conductivity type opposite to the one conductivity type.

The first n-channel TFT 401 has a second concentration of one conductivity type impurity region 331 overlapping the channel formation region 349 and the second shape electrode 325 forming the gate electrode.
(LDD region) and a third-concentration one-conductivity-type impurity region 328 functioning as a source region or a drain region. The length of the LDD in the channel length direction is 0.5 to 2.5.
μm, preferably 1.5 μm. LD like this
The configuration of the D region is mainly based on the hot carrier effect TFT
The purpose is to prevent the deterioration of the. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed using the n-channel TFT and the p-channel TFT. In particular, the structure of the first n-channel TFT 401 is suitable for a buffer circuit with a high drive voltage, for the purpose of preventing deterioration due to the hot carrier effect.

The second n-channel TFT 4 of the pixel portion 406
03 includes a channel formation region 350, a first concentration one conductivity type impurity region 316 formed outside the first shape electrode 313 forming a gate electrode, and a third concentration one concentration impurity region 316 functioning as a source region or a drain region. Conductivity type impurity region 32
9. In the semiconductor film 307 functioning as one electrode of the capacitor portion 404, an impurity region 336 having a conductivity type opposite to the first conductivity type of the fifth concentration is formed.

As described above, in this embodiment, the TFTs having different LDD structures are formed by differentiating the structures of the gate electrode of the drive circuit portion and the gate electrode of the pixel portion. The LDD overlapping with the gate electrode is formed in a self-aligned manner, and can be accurately formed without using a photomask. Thus, an active matrix substrate corresponding to a reflective display device can be manufactured.

[Embodiment 3] In this embodiment, the configuration of an active matrix substrate for forming a transmission type display device will be described with reference to FIG. FIG. 11 illustrates a configuration of the pixel portion 406 of the active matrix substrate formed in Embodiment 2. The second n-channel TFT 403 and the capacitor 404 are formed in the same manner as in the second embodiment.

FIG. 11A shows the fourth insulating film 338 and the fifth insulating film 338.
This shows a state in which a contact hole is formed after the formation of the insulating film 339, and the transparent electrode 370 is formed in a predetermined pattern on the fifth insulating film 339. The transparent power transmission film 370 is formed to a thickness of 100 nm. Indium oxide, tin oxide, zinc oxide, or a compound of these oxides can be used as the transparent conductive film. Further, a transparent conductive film 371 is also formed on the terminal portion.

Next, as shown in FIG. 11B, the electrodes 373 and 374 connected to the transparent electrode 370 and the gate line 37
5. The connection electrode 372 is formed. These are formed by stacking a 100 nm titanium film and a 300 nm aluminum film. With such a structure, an active matrix substrate corresponding to a transmission type display device is formed. Note that the configuration of the present embodiment can be applied to the active matrix substrate of the first embodiment.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix driven liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described with reference to FIGS.

After obtaining the active matrix substrate in the state shown in FIG. 11B, an alignment film 383 is formed on the active matrix substrate, and a rubbing process is performed. Although not shown, before forming the alignment film 383, an organic resin film such as an acrylic resin film may be patterned to form a columnar spacer at a desired position for maintaining a substrate interval. . Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, the counter electrode 38 is placed on the counter substrate 380.
1 is formed thereon, an alignment film 382 is formed thereon, and a rubbing process is performed. The counter electrode 381 is formed of ITO. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are bonded with a sealant (not shown). A filler is mixed in the sealant, and the two substrates are bonded together at a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material 385 is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material.

Thus, the active matrix driven liquid crystal display device shown in FIG. 12 is completed. Here, the example using the transmission type active matrix substrate manufactured in Embodiment 3 is shown, but the liquid crystal display device is similarly used even when the reflection type active matrix substrate manufactured in Embodiment 1 or 2 is used. Can be completed.

[Embodiment 5] FIG. 13 is an example showing a configuration of a pixel portion in an active matrix driving type light emitting device using the present invention. N-channel type T of pixel section 450
As the FT 203 and the p-channel type TFT 200, those manufactured by the steps of Embodiment 1 are applied. Fifth insulating film 5
The surface of No. 01 is made dense by plasma treatment with nitrogen or an inert gas. Typically, an argon plasma treatment is applied, and densification is achieved by forming an ultrathin film mainly containing carbon on the surface. After that, a contact hole is formed and a wiring is formed. The wiring is formed using titanium, aluminum, or the like.

In the pixel section 450, the data line 502 is connected to the source of the n-channel TFT 203, and the wiring 503 on the drain is connected to the gate electrode of the p-channel TFT 203. The source side of the p-channel TFT 200 is connected to the power supply wiring 505, and the drain side electrode 504 is connected to the anode of the light emitting element 451.

The light emitting device in this embodiment is configured by arranging organic light emitting elements in a matrix. Organic light emitting device 4
Reference numeral 51 denotes an anode, a cathode, and an organic compound layer formed therebetween. The anode 506 is formed after forming a wiring by using ITO. The organic compound layer is formed by combining a hole-transporting material having a relatively high hole mobility, an electron-transporting material, and a light-emitting material. They may be formed in layers, or may be formed by mixing.

The organic compound material is formed as a thin film layer having a total thickness of about 100 nm. Therefore, it is necessary to improve the flatness of the surface of ITO formed as the anode. When the flatness is poor, the cathode is short-circuited with the cathode formed on the organic compound layer in the worst case. As another means for preventing this, a method of forming an insulating layer 508 having a thickness of 1 to 5 nm can be adopted. As the insulating layer 508, polyimide, polyimide amide, polyamide, acrylic, or the like can be used.

The cathode includes a cathode 510 formed using a material such as an alkali metal or an alkaline earth metal such as MgAg or LiF. The detailed structure of the organic compound layer 509 is arbitrary.

Since the organic compound layer 509 and the cathode 510 cannot be subjected to a wet process (etching with a chemical solution, washing with water, etc.), the organic compound layer 509 and the cathode 510 are formed of a photosensitive resin material on the organic insulating film 501 in accordance with the anode 506. Partition layer 50
7 is provided. The partition layer 507 is formed so as to cover an end of the anode 506. Specifically, the partition layer 507 is formed by applying a negative resist and having a thickness of about 1 to 2 μm after baking. Alternatively, photosensitive acrylic or photosensitive polyimide can be used.

For the cathode 510, a material containing magnesium (Mg), lithium (Li) or calcium (Ca) having a small work function is used. Preferably, MgAg (M
An electrode made of a material obtained by mixing g and Ag at a ratio of Mg: Ag = 10: 1) may be used. In addition, MgAgAl electrode, Li
An Al electrode and a LiFAl electrode are mentioned. Further, as an upper layer, an insulating film 511 made of silicon nitride or a DLC film is formed with a thickness of 2 to 30 nm, preferably 5 to 10 nm. The DLC film can be formed by a plasma CVD method, and can be formed to cover the end portion of the partition layer 507 with good coverage even at a temperature of 100 ° C. or lower. DLC
The internal stress of the film can be reduced by mixing a small amount of argon, and can be used as a protective film. The DLC film includes oxygen, CO, C
Since it has high gas barrier properties such as O ₂ and H ₂ O, it is suitable as the insulating film 511 used as a barrier film.

In FIG. 13, the n-channel TFT 203 used for switching has a multi-gate structure, and the p-channel TFT 200 used for current control has an LDD overlapping the gate electrode. According to the present invention, TFTs having different LDD structures can be formed in the same step. A preferable application example to a light emitting device is shown in FIG. 13, and a TFT having a different LDD structure according to a function in a pixel portion (an n-channel TF for switching with sufficiently low off current)
T203 and p for current control that is strong against hot carrier injection
Channel type TFT 200) can be formed. As a result, a light-emitting device having high reliability and capable of displaying a good image (high operating performance) can be obtained.

FIG. 14 is a view showing a structure of a light emitting device having such a pixel portion 450 and a driving circuit 460. An organic resin 513 is filled on an insulating film 512 formed in the pixel portion 450, and the substrate 513 is sealed. are doing. A seal member may be provided at the end to further improve the airtightness. A flexible printed circuit (FPC) is mounted on the terminal portion 453.

Here, the configuration of the active matrix type self-luminous device of this embodiment will be described with reference to the perspective view of FIG.
The active matrix driving light emitting device of this embodiment includes a pixel portion 602, a scanning line driving circuit 603, and a data line driving circuit 604 formed on a glass substrate 601. The switching TFT 605 of the pixel portion is an n-channel TFT, and is arranged at an intersection of a gate wiring 606 connected to the gate driver circuit 603 and a source wiring 607 connected to the source driver circuit 604. The drain region of the switching TFT 605 is connected to the gate of the current control TFT 608.

Further, the data line side of the current controlling TFT 608 is connected to a power supply line 609. In the structure as in this embodiment, the power supply line 609 is supplied with a ground potential (earth potential). An organic light emitting element 610 is connected to a drain region of the current controlling TFT 608. A predetermined voltage (10 to 12 V in this embodiment) is applied to the cathode of the organic light emitting device 610.

The FPC 61 serving as an external input / output terminal
1 includes input / output wirings (connection wirings) 612 and 613 for transmitting signals to the drive circuit, and input / output wirings 614 connected to the power supply line 609. As described above, the pixel portion is formed by combining the TFT and the organic light emitting device, and the light emitting device can be completed.

[Embodiment 6] An embodiment of a method for manufacturing a semiconductor film used in Embodiment 1 or 2 will be described with reference to FIGS. In FIG. 16, after a metal element having a catalytic action is added to the entire surface of a semiconductor film having an amorphous structure and crystallized,
This is a method of performing gettering.

In FIG. 16A, the material of the substrate 701 is not particularly limited, but barium borosilicate glass, aluminoborosilicate glass, quartz, or the like can be preferably used. The first surface of the substrate 701
SiH ₄ , NH ₃ , N _{2 by} plasma CVD as an insulating film
The first silicon oxynitride film 702 made of O
a second layer made of SiH ₄ and N ₂ O.
A silicon oxynitride film 703 having a thickness of 100 nm is used. The first insulating film is provided so that the alkali metal contained in the glass substrate does not diffuse into the semiconductor film formed thereover. The first insulating film can be omitted when quartz is used as the substrate.

The semiconductor film 704 having an amorphous structure formed over the first insulating film uses a semiconductor material containing silicon as a main component. Typically, an amorphous silicon film or an amorphous silicon germanium film is applied, and the plasma C
10 to 10 by VD method, low pressure CVD method, or sputtering method
It is formed to a thickness of 0 nm. In order to obtain high-quality crystals, the concentration of impurities such as oxygen and nitrogen contained in the semiconductor film 704 having an amorphous structure is preferably reduced to 5 × 10 ¹⁸ / cm ³ or less. These impurities are factors that hinder crystallization of the amorphous semiconductor, and also increase the density of trapping centers and recombination centers even after crystallization. for that reason,
In addition to using a high-purity material gas, it is preferable to use an ultra-high vacuum-compatible CVD apparatus provided with a mirror surface treatment (electric field polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.

Thereafter, the semiconductor film 70 having an amorphous structure
On the surface of No. 4, a metal element having a catalytic action to promote crystallization is added. Metal elements having a catalytic action to promote crystallization of a semiconductor film include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), and rhodium (R).
h), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (A
u) and the like, and one or more selected from them can be used. Typically, nickel is used, and a nickel acetate salt solution containing 1 to 100 ppm by weight of nickel is applied by a spinner to form the catalyst-containing layer 705. In this case, in order to improve the familiarity of the solution, as a surface treatment of the semiconductor film 704 having an amorphous structure, an extremely thin oxide film is formed with an aqueous solution containing ozone, and the oxide film is formed with hydrofluoric acid and hydrogen peroxide. After forming a clean surface by etching with a mixed solution of the above, an ultrathin oxide film is formed by treating again with an ozone-containing aqueous solution. Since the surface of a semiconductor film such as silicon is hydrophobic in nature, a nickel acetate solution can be uniformly applied by forming an oxide film in this manner.

Of course, the catalyst containing layer 705 is not limited to such a method, and may be formed by a sputtering method, an evaporation method, a plasma treatment, or the like. Further, the catalyst containing layer 705 may be formed before forming the semiconductor film 704 having an amorphous structure, that is, on the first insulating film.

[0120] A heat treatment for crystallization is performed while the semiconductor film 704 having an amorphous structure and the catalyst-containing layer 705 are kept in contact with each other. Examples of the heat treatment method include a furnace annealing method using an electric heating furnace, a halogen lamp,
Rapid thermal annealing using a metal halide lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp, etc.
ing) method (hereinafter referred to as RTA method). Considering productivity, it is considered preferable to employ the RTA method.

In the case of performing the RTA method, a heating lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds.
It is repeated 1 to 10 times, preferably 2 to 6 times. Although the light emission intensity of the lamp light source is arbitrary, the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably 650 to 75 ° C.
Heat to about 0 ° C. Even at such a high temperature, the semiconductor film is only heated instantaneously, and the substrate 700 itself is not distorted and deformed. Thus, the semiconductor film having the amorphous structure is crystallized, and the semiconductor film 7 having the crystal structure shown in FIG.
06 can be obtained, but crystallization by such treatment can be achieved only by providing a catalyst-containing layer.

When the furnace annealing method is used as another method, one hour at 500 ° C. prior to the heat treatment.
Heat treatment for about an hour is performed to release hydrogen contained in the semiconductor film 704 having an amorphous structure. Then, crystallization is performed by performing a heat treatment at 550 to 600 ° C., preferably 580 ° C. for 4 hours in a nitrogen atmosphere using an electric furnace. Thus, a semiconductor film (first semiconductor film) 706 having a crystal structure illustrated in FIG. 16B is formed.

In order to further increase the crystallization ratio (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, the semiconductor film 706 having a crystal structure is irradiated with laser light. It is also effective. Excimer laser light having a wavelength of 400 nm or less, or a second or third harmonic of a YAG laser is used as the laser. In any case, a pulse laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is transmitted by an optical system to 100 to 4 Hz.
Laser processing may be performed on the semiconductor film 706 having a crystal structure with a concentration of 00 mJ / cm ² and an overlap ratio of 90 to 95%.

The catalyst element (here, nickel) remains in the thus obtained semiconductor film 706 having a crystal structure. Although it is not uniformly distributed in the film, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ as an average concentration. Of course, T
Although various semiconductor elements including FT can be formed, the element is removed by gettering by a method described below.

First, as shown in FIG. 16C, a thin barrier layer 707 is formed on a surface of a semiconductor film 706 having a crystal structure. The thickness of the barrier layer is not particularly limited, but may be simply replaced with a chemical oxide formed by treatment with ozone water. Alternatively, chemical oxides can be similarly formed by treating with an aqueous solution in which a hydrogen peroxide solution is mixed with sulfuric acid, hydrochloric acid, nitric acid or the like. As another method, the plasma treatment in an oxidizing atmosphere or the oxidation treatment by generating ozone by ultraviolet irradiation in an oxygen-containing atmosphere may be performed. Also, using a clean oven,
The barrier layer may be formed by heating to about 200 to 350 ° C. to form a thin oxide film. Alternatively, an oxide film of about 1 to 5 nm may be deposited as a barrier layer by a plasma CVD method, a sputtering method, an evaporation method, or the like.

A semiconductor film 708 having a thickness of 25 to 250 nm is formed thereon by a plasma CVD method or a sputtering method. Typically, argon is sputtered using argon to a concentration of 0.
It is formed of an amorphous silicon film containing 01 to 20 atomic%. Since the semiconductor film 708 is removed later, it is preferable that the film be a low-density film in order to increase the etching selectivity with respect to the semiconductor film 706 having a crystal structure. When a rare gas element is added to the amorphous silicon film and the rare gas element is simultaneously taken into the film, a gettering site can be formed.

The rare gas elements include helium (He), neon (Ne), argon (Ar), and krypton (K
r) or one or more selected from xenon (Xe). The present invention is characterized in that these rare gas elements are used as an ion source to form a gettering site and are implanted into a semiconductor film by an ion doping method or an ion implantation method. There are two meanings to implant ions of these rare gas elements. One is to form a dangling bond by implantation to give a strain to the semiconductor film, and the other is to give a strain by implanting the ion between lattices of the semiconductor film. Injection of an inert gas ion can simultaneously satisfy both of them, but in particular, the latter includes argon (Ar), krypton (Kr), and xenon (Xe).
It is remarkably obtained when an element having a larger atomic radius than silicon is used.

In order to surely achieve the gettering, it is necessary to perform a heat treatment thereafter. The heat treatment is performed by a furnace annealing method or an RTA method. When the furnace annealing method is used, 450 to 600 ° C. in a nitrogen atmosphere
For 0.5 to 12 hours. When the RTA method is used, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and the lighting is repeated 1 to 10 times, preferably 2 to 6 times. Although the light emission intensity of the lamp light source is arbitrary, the semiconductor film is
The heating is performed to 00 ° C, preferably to about 700 to 750 ° C.

In the gettering, the catalytic element in the region to be gettered (capture site) is released by thermal energy and moves to the gettering site by diffusion. Therefore, gettering depends on the processing temperature, and the higher the temperature, the faster the gettering proceeds. FIG.
As shown by the arrow in (E), the direction in which the catalytic element moves is a distance of about the thickness of the semiconductor film, and the gettering is completed in a relatively short time.

It should be noted that even with this heat treatment, 1 × 10 ²⁰ / c
The semiconductor film 708 containing a rare gas element at a concentration of m ³ or more does not crystallize. This is considered to be because the rare gas element is not re-emitted even in the above-mentioned processing temperature range and remains in the film to inhibit crystallization of the semiconductor film.

After that, the amorphous semiconductor 708 is selectively etched and removed. As an etching method, C
Dry etching without plasma using IF ₃ or wet etching with an alkaline solution such as an aqueous solution containing hydrazine or tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NOH) can be performed. At this time, the barrier layer 707 functions as an etching stopper. Further, the barrier layer 707 may be removed with hydrofluoric acid thereafter.

Thus, as shown in FIG. 16E, a semiconductor film 710 having a crystal structure in which the concentration of the catalytic element has been reduced to 1 × 10 ¹⁷ / cm ³ or less can be obtained. The semiconductor film 710 having a crystal structure thus formed is formed as a thin rod-shaped or thin flat rod-shaped crystal by the action of a catalytic element, and each crystal grows in a specific direction when viewed macroscopically. The semiconductor film 710 having a crystal structure manufactured in this embodiment can be applied to the semiconductor film described in Embodiment 1 or 2.

[Embodiment 7] FIG. 17 shows another method for gettering the catalyst element remaining in the semiconductor film 706 having the crystal structure obtained in Embodiment 8. A 150 nm thick silicon oxide film for a mask is formed over the semiconductor film 706 having a crystalline structure, a resist mask 712 is formed, and the silicon oxide film is etched to form a mask insulating film 7.
Get 11. After that, a rare gas element, or a rare gas element and phosphorus, or only phosphorus is injected into the semiconductor film 706 having a crystal structure by an ion doping method, so that a gettering site 713 is formed.

Thereafter, as shown in FIG. 17B, 450 to 6 in a nitrogen atmosphere by a furnace annealing method.
Heat treatment is performed at 00 ° C. for 0.5 to 12 hours. By this heat treatment, the catalyst element remaining in the semiconductor film 706 having a crystal structure can move to the gettering site 713 and be concentrated.

After that, the mask insulating film 711 and the gettering sites are removed by etching, whereby a semiconductor film 710 having a crystal structure can be obtained. The semiconductor film 710 having a crystal structure manufactured in this embodiment can be applied to the semiconductor film described in Embodiment 1 or 2.

[Embodiment 8] In Embodiment 6, a 1-10 nm silicon nitride film can be used as the first insulating film formed on the substrate 701. FIG. 29 shows the formation of a semiconductor film 706 having a crystal structure, a barrier layer 707, a semiconductor film 708, and a semiconductor film 709 to which a rare gas element is added, which are manufactured in the same manner as in Embodiment 6 using such a first insulating film 720. This shows a state in which gettering is performed by heat treatment. Since a catalyst element such as nickel has a property of being trapped in oxygen or in the vicinity of oxygen, by forming the first insulating film with a silicon nitride film, the catalyst element can be removed from the semiconductor film 706 having a crystal structure to the semiconductor film 708 or a rare metal. It can be easily moved to the semiconductor film 709 to which a gas element is added.

[Embodiment 9] With the widespread use of liquid crystal televisions and the like and the increase in screen size, the problem of wiring delay in data lines and gate lines in the pixel portion cannot be ignored. For example, the pixel structure shown in the first embodiment is
Although the aperture ratio can be improved, since the data line is formed of the same material as the gate electrode, it is necessary to consider a problem of wiring delay as well as an increase in screen size.

For example, when the pixel density is VGA, 480 gate wirings and 640 source wirings are formed, and XG
In the case of A, 768 gate wirings and 1024 source wirings are formed. When the screen size of the display area is 13 inches, the length of the diagonal is 340 mm, and
In the case of the inch class, it is 460 mm. In this embodiment, the problem of the delay time is solved in such a display device.
Also, a method for minimizing the area required for wiring will be described.

The gate electrode of the TFT shown in this embodiment is formed by laminating at least two kinds of conductive films as shown in Embodiment Mode 1 or Embodiment 1. Although Al and Cu, which are preferably used as low-resistance materials, have high conductivity, heat resistance and corrosion resistance are poor, so some consideration is required.

Specifically, a nitride metal material such as tantalum nitride or titanium nitride, a high melting point metal material such as Mo or W, or the like is used for the first conductive film in contact with the gate insulating film to prevent diffusion of Al and Cu. Use a material with a barrier property to block.
As the second conductive film, Al or Cu is used, and a third conductive film such as Ti or W is formed thereon. This is a consideration for reducing the contact resistance with the wiring formed in the upper layer.
This is because l and Cu are relatively easily oxidized.

FIG. 18 shows an example in which a W film is formed as the first conductive film, an Al film is formed as the second conductive film, and a Ti film is formed as the third conductive film to form a gate electrode, a data line, and a capacitance line. The configurations of the driving circuit unit 205 and the pixel unit 206 are the same as those in the first embodiment.

In the first etching process, when an ICP etching apparatus is used, BCl ₃ , Cl ₂ ,
Etching is performed at a pressure of 1.2 Pa using O ₂ (flow rate ratio: 65: 10: 5). A high frequency power is applied to the substrate side so as to be substantially negatively biased. Under these conditions, Al is etched, and the etching gas is CF ₄ , Cl ₂ , O
₂ (flow rate ratio: 25:25:10), and the W film is etched.

In the second etching, BCl ₃ and Cl ₂ (flow rate ratio: 20:60) are used as an etching gas, and a high frequency power is applied to the substrate side so as to be substantially negatively biased. As a result, Al and Ti are selectively etched to form second shape electrodes 127 to 129 and second shape wirings 130 to 132 shown in FIG. 18 (these are first conductive films 127 e to 132 e). , The second conductive film 127
f to 132f and the third conductive films 127g to 132g).

In FIG. 18, the wiring resistance can be sufficiently reduced by forming both the data line 131 and the gate line using Al. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.
Further, Cu is suitable for increasing the current density flowing in the wiring such as the power supply line of the light emitting device described in Embodiment 5.
The Cu wiring has a feature that its resistance to electromigration is higher than that formed using Al.

[Embodiment 10] The 1nth embodiment shown in Embodiment 1 or 2
A channel TFT is an enhancement type and a depletion type by adding an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) to a semiconductor to be a channel formation region. Can be made separately. Also, n-channel type T
When forming an NMOS circuit by combining FTs, or when forming an enhancement type TFT (hereinafter referred to as EEM).
A combination of an enhancement type and a depletion type (hereinafter referred to as an EDMO circuit).
S circuit).

Here, an example of the EEMOS circuit is shown in FIG.
FIG. 19B shows an example of the EDMOS circuit. FIG.
In (A), reference numerals 31 and 32 denote enhancement type n-channel TFTs (hereinafter, referred to as E-type NTFTs). In FIG. 19B, reference numeral 33 denotes an E-type N
TFT, 34 is a depletion type n-channel type TFT
(Hereinafter, referred to as D-type NTFT). Note that FIG.
In (A) and (B), VDH is a power supply line to which a positive voltage is applied (positive power supply line), and VDL is a power supply line to which a negative voltage is applied (negative power supply line). The negative power supply line may be a ground potential power supply line (ground power supply line).

Further, the EEMOS shown in FIG.
FIG. 20 illustrates an example in which a shift register is manufactured using a circuit or the EDMOS circuit illustrated in FIG. FIG.
At 0, 40 and 41 are flip-flop circuits. Reference numerals 42 and 43 denote E-type NTFTs and E-type NTFs.
The clock signal (CL) is input to the gate of T42,
A clock signal (CL bar) having an inverted polarity is input to the gate of the E-type NTFT 43. The symbol indicated by 44 is an inverter circuit. As shown in FIG. 20B, the EEMOS circuit shown in FIG.
The EDMOS circuit shown in FIG. 9B is used. Therefore, the driving circuits of the liquid crystal display device are all n-channel TFTs.
It is also possible to configure with.

[Embodiment 11] In this embodiment, an example of a circuit configuration example of an active matrix driven display device will be described. In particular, in this embodiment, a case where the source-side drive circuit and the gate-side drive circuit are all formed by the E-type NTFT described in Embodiment 10 will be described with reference to FIGS. In the present invention, a decoder using only an n-channel TFT is used instead of the shift register.

FIG. 24 shows an example of a gate-side drive circuit. In FIG. 21, reference numeral 1000 denotes a decoder of the gate-side drive circuit, and 1001 denotes a buffer unit of the gate-side drive circuit.
Note that the buffer unit indicates a portion where a plurality of buffers (buffer amplifiers) are integrated. The buffer refers to a circuit that performs driving without giving the influence of the subsequent stage to the preceding stage.

First, the gate side decoder 1000 will be described. Reference numeral 1002 denotes an input signal line of the decoder 1000 (hereinafter, input signal line).
A1 and A1 bars (A1 bar)
, A2 and A2 bars (signals with inverted polarity of A2),... An, An bars (signals with inverted polarity of An). That is, it can be considered that 2n selection lines are arranged. The number of selection lines is determined by the number of gate lines output from the gate-side drive circuit. For example, in the case of having a pixel portion for VGA display, there are 480 gate lines, so that a total of 18 selection lines for 9 bits (corresponding to n = 9) are required. The selection line 1002 transmits the signal shown in the timing chart of FIG. As shown in FIG. 22, when the frequency of A1 is 1, the frequency of A2 is ^2-1 times, the frequency of A3 is ^2-2 times, and A
The frequency of n becomes 2- ^(n-1) times.

Reference numeral 1003a denotes a first stage NAND circuit (also referred to as a NAND cell), and 1003b denotes a second stage NA circuit.
The ND circuit 1003c is an n-th stage NAND. NA
The number of ND circuits required is equal to the number of gate wirings, and here n is required. That is, in the present invention, the decoder 1000
Consists of a plurality of NAND circuits.

Also, NAND circuits 1003a to 1003c
, The n-channel TFTs 1004 to 1009 are combined to form a NAND circuit. Note that actually 2
n TFTs are used for the NAND circuit 1003. The gate of each of the n-channel TFTs 1004 to 1009 is connected to a select line 1002 (A1, A1 bar, A2, A2).
2 bar... An, An bar).

At this time, in the NAND circuit 1003a, an n-channel type TF having a gate connected to one of A1, A2... An (these are referred to as positive selection lines).
T1004 to T1006 are connected in parallel with each other, connected to the negative power supply line (V _DL ) 1010 as a common source, and connected to the output line 1011 as a common drain. Further, n-channel TFTs 1007 to 1009 having gates connected to any of A1 bar, A2 bar... An bar (these are referred to as negative selection lines) are connected in series with each other, and are located at circuit ends. The source of the n-channel TFT 1009 is a positive power supply line (V _DH ) 1012.
And the drain of the n-channel TFT 1007 located at the other circuit end is connected to the output line 1011.

As described above, in the present invention, the NAND circuit includes n n-channel TFTs connected in series and n n-channel TFTs connected in parallel. However, in the n NAND circuits 1003a to 1003c, all combinations of the n-channel TFT and the selection line are different. That is, only one output line 1011 is always selected, and the output line 1011 is
A signal is input such that 11 is selected in order from the end.

Next, the buffer section 1001 is formed by a plurality of buffers 1013a to 1013c corresponding to the NAND circuits 1003a to 1003c, respectively. However, the buffers 1013a to 1013c may have the same structure.

The buffers 1013a to 1013c are formed using n-channel TFTs 1014 to 1016. The output line 1011 from the decoder is an n-channel type TF
Input as a gate of T1014 (first n-channel TFT). The n-channel TFT 1014 uses a positive power supply line (V _DH ) 1017 as a source and a gate wiring 1018 following the pixel portion as a drain. Also, n-channel type TFT
1015 (second n-channel TFT) has a positive power supply line (V _DH ) 1017 as a gate and a negative power supply line (V _DL ) 1017.
19 is a source, and a gate wiring 1018 is a drain.

That is, in the present invention, the buffer 1013
a to 1013c are connected in series to the first n-channel TFT (n-channel TFT 1014) and the first n-channel TFT, and the second n-channel TFT (n-channel TFT 1015) having the drain of the first n-channel TFT as a gate. )including.

The n-channel TFT 1016 (3n
The channel type TFT) has a reset signal line (Reset) as a gate, a negative power supply line (V _DL ) 1019 as a source, and a gate wiring 1018 as a drain. Note that the negative power line (V
_DL ) 1019 may be a ground power supply line (GND).

At this time, the channel width (W1) of the n-channel TFT 1015 and the n-channel TFT 101
4 has a relationship of W1 <W2. Note that the channel width is the length of a channel formation region in a direction perpendicular to the channel length.

The operation of the buffer 1013a is as follows. First, when a negative voltage is applied to the output line 1011, the n-channel TFT 1014 is turned off (a channel is not formed). On the other hand, the voltage of the negative power supply line 1019 is applied to the gate wiring 1018 because the n-channel TFT 1015 is always on (state in which a channel is formed).

[0161] When a positive voltage is applied to the output line 1011, the n-channel TFT 1014 is turned on. At this time, the channel width of the n-channel TFT 1014 is n
Since the channel width is larger than the channel width of the channel type TFT 1015, the potential of the gate wiring 1018 is
014 side, and as a result, the positive power supply line 101
7 is applied to the gate wiring 1018. Therefore,
The gate wiring 1018 has a positive voltage (a voltage at which an n-channel TFT used as a switching element of a pixel is turned on) when a positive voltage is applied to the output line 1011.
And a negative voltage (a voltage at which an n-channel TFT used as a switching element of a pixel is turned off) is always output when a negative voltage is applied to the output line 1011.

Note that the n-channel TFT 1016 is used as a reset switch for forcibly pulling down the gate wiring 1018 to which a positive voltage is applied to a negative voltage. That is,
When the selection period of the gate wiring 118 ends. A reset signal is input to apply a negative voltage to the gate wiring 1018. However, the n-channel TFT 1016 can be omitted.

The gate lines are sequentially selected by the gate-side drive circuit having the above operation. Next, the configuration of the source side driver circuit is shown in FIG. The source driver circuit illustrated in FIG. 26 includes a decoder 1021, a latch 1022, and a buffer unit 1023. Note that the decoder 102
1 and the configuration of the buffer unit 1023 are the same as those of the gate-side drive circuit, and thus description thereof is omitted here.

In the case of the source-side drive circuit shown in FIG. 23, the latch 1022 includes a first-stage latch 1024 and a second-stage latch 1025. Also, the first-stage latch 1
The 024 and the second-stage latch 1025 each have a plurality of unit units 1027 formed by m n-channel TFTs 1026a to 1026c. Decoder 102
The output line 1028 from 1 is input to the gates of m n-channel TFTs 1026a to 1026c forming the unit unit 1027. Note that m is an arbitrary integer.

For example, in the case of VGA display, the number of source wirings is 640. When m = 1, 640 NAND circuits are required, and 20 selection lines (corresponding to 10 bits) are required. However, if m = 8, the necessary N
There are 80 AND circuits, and 14 selection lines are required (7
(equivalent to bits). That is, if the number of source wirings is M, the number of required NAND circuits is (M / m).

N-channel TFTs 1026a to 1026c
Are video signal lines (V1, V2... Vk) 10
29. That is, when a positive voltage is applied to the output line 1028, the n-channel TFTs 1026a to
26c is turned on, and a video signal corresponding to each is captured. The video signal thus captured is held in capacitors 1030a to 1030c connected to the respective n-channel TFTs 1026a to 1026c.

The second stage latch 1025 also has a plurality of unit units 1027b, and the unit unit 1027b is formed of m n-channel TFTs 1031a to 1031c. The gates of the n-channel TFTs 1031a to 1031c are all connected to the latch signal line 1032, and when a negative voltage is applied to the latch signal line 1032, the n-channel TFTs 1031a to 1031c are turned on all at once.

As a result, capacitors 1030a-103
0c is changed to an n-channel TFT 10
Capacitor 103 connected to each of 31a to 1031c
3a to 1033c and buffer 1023
Is output to. Then, the signal is output to the source wiring 1034 via the buffer as described with reference to FIG. The source wirings are sequentially selected by the source-side drive circuit having the above operation.

As described above, by forming the gate-side drive circuit and the source-side drive circuit only with the n-channel type TFT, the pixel portion and the drive circuit are all n-channel type TFTs.
It can be formed by FT. The configuration of this embodiment is
It can be applied to the drive circuit of the active matrix substrate of the first or second embodiment.

[Embodiment 12] In this embodiment, another example of the circuit configuration of an active matrix driven display device will be described. In particular, in this embodiment, all of the source-side drive circuit and the gate-side drive circuit are of the p-channel type T
This is a case where only FT is used. A decoder using a p-channel TFT is used instead of a general shift register. FIG. 24 illustrates an example of a gate-side drive circuit.

In FIG. 24, 1200 is a decoder of the gate side drive circuit, and 1201 is a buffer section of the gate side drive circuit. Note that the buffer unit indicates a portion where a plurality of buffers (buffer amplifiers) are integrated. The buffer refers to a circuit that performs driving without giving the influence of the subsequent stage to the preceding stage.

First, the gate side decoder 1200 will be described. Reference numeral 1202 denotes an input signal line of the decoder 1200 (hereinafter, referred to as an input signal line).
A1 and A1 bars (A1 bar)
, A2 and A2 bars (signals with inverted polarity of A2),... An, An bars (signals with inverted polarity of An). That is, it can be considered that 2n selection lines are arranged.

The number of selection lines is determined by the number of gate lines output from the gate side drive circuit. For example, in the case of having a VGA display pixel portion, the number of gate wirings is 480, so that 9 bits (equivalent to n = 9)
Requires a total of 18 selection lines. The selection line 1202 transmits the signal shown in the timing chart of FIG. As shown in FIG. 25, when the frequency of A1 is 1, the frequency of A2 is ^2-1 times, the frequency of A3 is ^2-2 times, and the frequency of An is 2- ^(n-1) times.

Reference numeral 1203a denotes a first stage NAND circuit (also referred to as a NAND cell), and 1203b denotes a second stage NA circuit.
The ND circuit 1203c is an n-th stage NAND. NA
The number of ND circuits required is equal to the number of gate wirings, and here n is required. That is, in the present invention, the decoder 1200 is used.
Consists of a plurality of NAND circuits.

Also, NAND circuits 1203a to 1203c
Are formed by combining p-channel TFTs 1204 to 1209 to form a NAND circuit. Note that actually 2
n TFTs are used for the NAND circuit 1203. The gate of each of the p-channel TFTs 1204 to 1209 is connected to a selection line 1202 (A1, A1 bar, A2, A2).
2 bar... An, An bar).

At this time, in the NAND circuit 1203a, a p-channel type TF having a gate connected to one of A1, A2... An (these are referred to as positive selection lines).
T1204 to T1206 are connected in parallel with each other, are connected to a positive power supply line (V _DH ) 1210 as a common source, and are connected to an output line 1211 as a common drain. Also, p-channel TFTs 1207 to 1209 having gates connected to any of A1 bar, A2 bar... An bar (these are referred to as negative selection lines) are connected in series with each other and located at the circuit end. The source of the p-channel TFT 1209 is a negative power supply line (V _DL ) 1212.
And the drain of the p-channel TFT 1207 located at the other circuit end is connected to the output line 1211.

As described above, in the present invention, the NAND circuit includes n one-conductivity type TFTs (here, p-channel type TFTs) connected in series and n one-type conductivity type TFTs (here, n-type TFTs) connected in parallel. p-channel TFT).
However, in the n NAND circuits 1203a to 103c, the combinations of the p-channel TFTs and the selection lines are all different. That is, only one output line 1211 is always selected, and the output line 1
A signal is input such that 211 is selected in order from the end.

Next, the buffer 1201 is connected to the NAND circuit 1
A plurality of buffers 1 corresponding to each of 203a to 1203c
213a to 1213c. However, the buffers 1213a to 1213c may have the same structure.

The buffers 1213a to 1213c are p-channel TFTs 1214 to 121 as one conductivity type TFTs.
6 is formed. Output line 1211 from the decoder
Is a p-channel TFT 1214 (first one conductivity type TFT)
Is input as a gate. p-channel type TFT121
Reference numeral 4 designates a ground power supply line (GND) 1217 as a source and a gate wiring 1218 as a drain. Also, p-channel type T
The FT 1215 (second one conductivity type TFT) is connected to the ground power supply line 12.
17 is a gate, a positive power supply line (V _DH ) 1219 is a source, and a gate wiring 1218 is a drain, and is always on.

That is, in the present invention, the buffer 1213
a to 1213c are first one conductivity type TFTs (p-channel type TFs).
T1214) and a second one-conductivity TFT (p-channel TFT 1215) connected in series to the first one-conductivity TFT and having the drain of the first one-conductivity TFT as a gate.
including.

A p-channel TFT 1216 (third one conductivity type TFT) has a reset signal line (Reset) as a gate, a positive power supply line 1219 as a source, and a gate wiring 121.
8 is a drain. Note that the ground power supply line 1217 may be a negative power supply line (however, a power supply line for applying a voltage that turns on a p-channel TFT used as a switching element of a pixel).

At this time, the channel width (referred to as W1) of the p-channel TFT 1215 and the p-channel TFT 121
4 has a relationship of W1 <W2. Note that the channel width is the length of a channel formation region in a direction perpendicular to the channel length.

The operation of the buffer 1213a is as follows. First, when a positive voltage is applied to the output line 1211, the p-channel TFT 1214 is in an off state (a state in which no channel is formed). On the other hand, the voltage of the positive power supply line 1219 is applied to the gate wiring 1218 because the p-channel TFT 1215 is always on (a state where a channel is formed).

However, when a negative voltage is applied to the output line 1211, the p-channel TFT 1214 is turned on. At this time, since the channel width of the p-channel TFT 1214 is larger than the channel width of the p-channel TFT 1215, the potential of the gate wiring 1218 is pulled by the output of the p-channel TFT 1214, and as a result, the voltage of the ground power supply line 1217 is reduced. It is added to the gate wiring 1218.

Therefore, the gate line 1218 is connected to the output line 1
When a negative voltage is applied to 211, a negative voltage (a voltage that turns on a p-channel TFT used as a pixel switching element) is output, and when a positive voltage is applied to output line 1211, the output is always positive. A voltage (a voltage at which a p-channel TFT used as a switching element of a pixel is turned off) is output.

Note that the p-channel TFT 1216 is used as a reset switch for forcibly raising the gate wiring 1218 to which a negative voltage is applied to a positive voltage. That is,
When the selection period of the gate wiring 1218 ends. A reset signal is input to apply a positive voltage to the gate wiring 1218.
However, the p-channel TFT 1216 can be omitted.

The gate lines are sequentially selected by the gate-side drive circuit having the above operation. Next, the configuration of the source side driver circuit is shown in FIG. The source driver circuit shown in FIG. 26 includes a decoder 1301, a latch 1302, and a buffer 1303. Note that the decoder 1301
The configuration of the buffer 1303 is the same as that of the gate-side drive circuit, and a description thereof will not be repeated.

In the case of the source-side drive circuit shown in FIG. 25, the latch 1302 includes a first-stage latch 1304 and a second-stage latch 1305. Also, the first-stage latch 1
The 304 and the second-stage latch 1305 each have a plurality of unit units 1307 formed by m p-channel TFTs 1306a to 1306c. Decoder 130
The output line 1308 from 1 is input to the gates of m p-channel TFTs 1306a to 1306c forming the unit unit 1307. Note that m is an arbitrary integer.

For example, in the case of VGA display, the number of source wirings is 640. When m = 1, 640 NAND circuits are required, and 20 selection lines (corresponding to 10 bits) are required. However, if m = 8, the necessary N
There are 80 AND circuits, and 14 selection lines are required (7
(equivalent to bits). That is, if the number of source wirings is M, the number of required NAND circuits is (M / m).

The p-channel type TFTs 1306a to 1306a-
The sources of 1306c are video signal lines (V1, V2,.
Vk) 1309. That is, when a negative voltage is applied to the output line 1308, the p-channel type TFT 130
6a to 1306c are turned on, and video signals corresponding to each of them are captured. The video signals thus captured are held in capacitors 1310a to 1310c connected to the p-channel TFTs 1306a to 1306c, respectively.

The second-stage latch 1305 also has a plurality of unit units 1307b, and the unit unit 1307b is formed of m p-channel TFTs 1311a to 1311c. The gates of the p-channel TFTs 1311a to 1311c are all connected to the latch signal line 1312. When a negative voltage is applied to the latch signal line 1312, the p-channel TFTs 1311a to 1311c are turned on all at once.

As a result, capacitors 1310a-131
0c is changed to a p-channel type TFT 13
Capacitor 131 connected to each of 11a to 1311c
3a to 1313c and buffer 1303
Is output to. Then, the signal is output to the source wiring 1314 via the buffer as described with reference to FIG. The source wirings are sequentially selected by the source-side drive circuit having the above operation.

As described above, by forming the gate-side drive circuit and the source-side drive circuit only with the p-channel type TFT, the pixel portion and the drive circuit are all p-channel type TFTs.
It can be formed by FT. Therefore, in manufacturing an active matrix type electro-optical device, the yield and throughput of the TFT process can be significantly improved, and the manufacturing cost can be reduced. The configuration of this embodiment can be applied to the drive circuit of the active matrix substrate of the first or second embodiment.

[Embodiment 13] Various semiconductor devices can be manufactured by using the present invention. Such semiconductor devices include a video camera, a digital camera, a goggle-type display device (head-mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook personal computer, a game device, a portable information terminal ( A mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), and an image reproducing device provided with a recording medium. FIGS. 19 and 20 show specific examples of these semiconductor devices.

FIG. 27A shows a monitor of a desktop personal computer or the like.
It is composed of a support 3302, a display portion 3303, and the like.
As the display portion 3303, the liquid crystal display device driven by the active matrix described in Embodiment 8 or the light emitting device described in Embodiment 9 can be applied. Further, another integrated circuit can be formed by applying the TFT of the present invention. It is. As described above, a monitor such as a desktop personal computer can be completed by using the present invention.

FIG. 27B shows a video camera, which includes a main body 3311, a display portion 3312, an audio input portion 3313, operation switches 3314, a battery 3315, and an image receiving portion 331.
6 and so on. As the display portion 3312, an active matrix liquid crystal display device described in Embodiment 8 or a light-emitting device described in Embodiment 9 can be applied. Further, another integrated circuit can be formed using the TFT of the present invention. It is. Thus, a video camera can be completed using the present invention.

FIG. 27C shows a part (one side on the right) of the head mount display, which includes a main body 3321, a signal cable 3322, a head fixing band 3323, and a projection section 332.
4, including an optical system 3325, a display unit 3326, and the like. As the display portion 3326, the active matrix liquid crystal display device described in Embodiment 8 or the light emitting device described in Embodiment 9 can be applied. Further, another integrated circuit can be formed using the TFT of the present invention. It is. Thus, a head mounted display can be completed using the present invention.

FIG. 27D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, recording medium (DVD, etc.) 3332, operation switch 33
33, a display section (a) 3334, a display section (b) 3335, and the like. The display portion (a) 3334 mainly displays image information, and the display portion (b) 3335 mainly displays character information. The display portions 3334 and 3335 are each an active matrix liquid crystal display device or an embodiment described in Embodiment 8. The light emitting device indicated by 9 is applicable, and other integrated circuits can be formed by applying the TFT of the present invention. Thus, an image reproducing apparatus can be completed using the present invention.

FIG. 27E shows a goggle type display device (head mounted display), which includes a main body 3341, a display portion 3342, and an arm portion 3343. Display portion 3342
Is applicable to the active matrix driven liquid crystal display device described in Embodiment 8 or the light emitting device described in Embodiment 9.
Further, other integrated circuits can be formed by applying the TFT of the present invention. Thus, a goggle type display device can be completed using the present invention.

[0200] FIG. 27F shows a notebook personal computer, which includes a main body 3351, a housing 3352, and a display portion 3.
353, a keyboard 3354, and the like. Display unit 3353
Is applicable to the active matrix driven liquid crystal display device described in Embodiment 8 or the light emitting device described in Embodiment 9.
Further, other integrated circuits can be formed by applying the TFT of the present invention. Thus, a notebook personal computer can be completed using the present invention.

FIG. 28A shows a cellular phone, which includes a display panel 2701, an operation panel 2702, and a connection portion 2703.
The display panel 2701 is provided with a display device 2704 represented by a liquid crystal display device or an EL display device, an audio output unit 2705, an antenna 2709, and the like.
An operation panel 2702 is provided with an operation key 2706, a power switch 2702, a voice input unit 27008, and the like. As the display portion 2704, an active matrix liquid crystal display device described in Embodiment 8 or a light-emitting device described in Embodiment 9 can be used. Further, another integrated circuit can be formed using the TFT of the present invention. It is. Thus, a mobile phone can be completed using the present invention.

FIG. 28B shows a sound reproducing device, specifically, a car audio.
2. Including operation switches 3413 and 3414. Display 3
Reference numeral 412 denotes the active matrix liquid crystal display device described in Embodiment 8 or the light emitting device described in Embodiment 9 can be applied. In addition, other integrated circuits can be formed by applying the TFT of the present invention. . As described above, a sound reproducing device, specifically, a car audio can be completed by using the present invention.

FIG. 28C shows a digital camera, which includes a main body 3501, a display section (A) 3502, an eyepiece section 3503,
An operation switch 3504, a display portion (B) 3505, and a battery 3506 are included. As the display portions 3502 and 3505, the liquid crystal display device driven by the active matrix described in Embodiment 8 or the light emitting device described in Embodiment 9 can be applied, and other integrated circuits can be formed by applying the TFT of the present invention. Is also possible. Thus, a digital camera can be completed using the present invention.

As described above, the applicable range of the present invention is extremely wide, and can be applied to various electronic devices. or,
The electronic device according to the present embodiment can be realized by using a configuration including any combination of the first to twelfth embodiments.

[0205]

As described above, according to the present invention, n-channel TFTs and p-channel TFTs having different LDD structures can be formed on the same substrate in the same step.
Using such an active matrix substrate, a liquid crystal display device or a display device having a light-emitting layer over the same substrate can be formed.

Although the reduction in the number of photomasks leads to an improvement in productivity, the present invention is not limited to this.
By optimizing the LDD structure of the channel type TFT, the reliability and operation characteristics of the active matrix substrate can be improved at the same time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 5 is a top view illustrating a structure of a pixel portion of an active matrix substrate corresponding to a reflective display device.

FIG. 6 illustrates a circuit configuration of an active matrix substrate.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a transmission display device.

FIG. 12 is a cross-sectional view illustrating a structure of a transmissive liquid crystal display device.

FIG. 13 is a cross-sectional view illustrating a structure of a pixel portion of a light-emitting device.

FIG. 14 is a cross-sectional view illustrating a structure of a light-emitting device.

FIG. 15 is a perspective view illustrating a configuration of an active matrix substrate.

FIG. 16 illustrates a manufacturing process of a semiconductor film having a crystal structure.

FIG. 17 illustrates a manufacturing process of a semiconductor film having a crystal structure.

FIG. 18 is a cross-sectional view illustrating a structure of an active matrix substrate of the present invention.

FIG. 19 illustrates a configuration of an NMOS circuit.

FIG. 20 illustrates a structure of a shift register.

FIG. 21 is a diagram illustrating a configuration of a gate line driver circuit formed using an n-channel TFT.

FIG. 22 is a diagram illustrating a timing chart of a decoder input signal.

FIG. 23 illustrates a configuration of a data line driver circuit formed using n-channel TFTs.

FIG. 24 illustrates a configuration of a gate line driver circuit formed using p-channel TFTs.

FIG. 25 is a diagram illustrating a timing chart of a decoder input signal.

FIG. 26 illustrates a configuration of a data line driver circuit formed using p-channel TFTs.

FIG. 27 illustrates an example of a semiconductor device.

FIG 28 illustrates an example of a semiconductor device.

FIG 29 illustrates a manufacturing process of a semiconductor film having a crystal structure.

FIG. 30 is a graph showing a doping profile of phosphorus through a gate insulating film and a tantalum nitride film.

FIG. 31 is a graph in which the thickness of a tantalum nitride film is converted into a gate insulating film and fitted, and the result obtained by multiplying by a constant times is shown.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 29/78 616A 29/43 27/08 321A 29/62 GF term (Reference) 2H092 JA24 MA14 MA17 MA27 NA27 5F048 AC04 BA16 5F110 AA16 BB02 BB04 CC02 DD01 DD02 DD03 DD05 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE09 EE14 EE15 EE23 EE28 EE44 FF04 FF28 FF30 GG01 GG02 GG13 H12 GG13 GG13 GG13 GG13 HL11 HL12 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN34 NN35 NN40 NN44 NN73 NN78 PP01 PP02 PP03 PP04 PP05 PP06 PP10 PP13 PP29 PP34 PP35 QQ01 QQ04 QQ08 QQ11 QQ19 QQ23 QQ28

Claims (7)

[Claims] A first semiconductor film, a second semiconductor film, and a third semiconductor film which are separated from each other on the first insulating film; and wherein the first semiconductor film, the second semiconductor film, and the third semiconductor film are separated from each other. A second insulating film is formed on the first semiconductor film, the second semiconductor film, and the third semiconductor film.
An electrode and a third electrode are formed, and the first semiconductor film, the second semiconductor film, and the third semiconductor are subjected to a first doping process using the first shape of the first electrode, the second electrode, and the third electrode as a mask. Forming a first concentration of one conductivity type impurity region on the film;
Forming a first electrode, a second electrode, and a third electrode having a shape;
Doping treatment forms a second concentration one conductivity type impurity region overlapping the second shape second electrode in the second semiconductor film, and a third concentration one conductivity type impurity region in the first semiconductor film and the second semiconductor film. By forming an impurity region and performing a third doping process,
Forming a fourth impurity region and a fifth impurity region having a conductivity type opposite to one conductivity type in the third semiconductor film. 2. A step of forming a second insulating film on a first semiconductor film, a second semiconductor film, and a third semiconductor film formed on a first insulating film, and a step of forming a second insulating film on the second insulating film. Stacking a first conductive film and a second conductive film, and etching the first conductive film and the second conductive film by a first etching process to form the first semiconductor film, the second semiconductor film, and the third semiconductor film; Forming a first electrode, a second electrode, and a third electrode having a first shape corresponding to the above, and forming the first semiconductor film, the second semiconductor film, and the third semiconductor film by a first doping process. Forming a first-concentration one-conductivity-type impurity region and etching the first shape first electrode, the second electrode, and the third electrode by a second etching process to form a second shape first electrode; Forming a first electrode, a second electrode, and a third electrode; and performing a second doping process on the second semiconductor film. Forming a third concentration one conductivity type impurity region in the first semiconductor film and the second semiconductor film, and forming a third concentration one conductivity type impurity region in the first semiconductor film and the second semiconductor film; Forming a fourth impurity region and a fifth impurity region having a conductivity type opposite to that of one conductivity type. 3. A first semiconductor film, a second semiconductor film, and a third semiconductor film separated from each other on a first insulating film, and a first electrode having a first shape is formed on the first semiconductor film. Is formed via a second insulating film, and a first concentration one conductivity type impurity region is formed in the first semiconductor film using the first electrode having the first shape as a mask. The first on the semiconductor film
A second electrode and a third electrode having a second shape are formed through the second insulating film, and the second electrode and the third electrode having the first shape are etched to form a second electrode and a third electrode having a second shape. Is formed, and a second concentration one-conductivity-type impurity region overlapping with the second shape second electrode is formed in the second semiconductor film by a second doping process. 3
Forming a fourth impurity region and a fifth impurity region of a conductivity type opposite to the one conductivity type in the third semiconductor film by a third doping process by forming an impurity region having a concentration of one conductivity type. A method for manufacturing a semiconductor device. 4. A step of forming a second insulating film on the first semiconductor film, the second semiconductor film, and the third semiconductor film formed on the first insulating film, and forming a second insulating film on the second insulating film. Forming a first conductive film and a second conductive film, and etching the first conductive film and the second conductive film by a first etching process to form a first electrode having a first shape on the first semiconductor film; The process of
Forming a first-concentration one-conductivity-type impurity region in the first semiconductor film by using the first shape-shaped first electrode as a mask by a first doping process; Forming a second electrode and a third electrode of a first shape on the second semiconductor film and the third semiconductor film by etching a second conductive film; and performing a third etching process to form a second electrode of the first shape. Forming a second shaped second electrode and a third electrode by etching the electrode and the third electrode; and forming a second concentration one conductivity type impurity region in the second semiconductor film by a second doping process. Forming a third-concentration one-conductivity-type impurity region in the first semiconductor film and the second semiconductor film; and performing a third doping process on the third semiconductor film to form a third-conductivity-type second conductivity-type impurity region. Four impurity region and fifth impurity region The method for manufacturing a semiconductor device comprising the steps of forming a. 5. The method according to claim 1, wherein the first conductive film is formed of a compound of one or more kinds selected from Ta, W, Ti, and Mo and nitrogen. 2
A method for manufacturing a semiconductor device, wherein the conductive film is formed using one or more alloys selected from Ta, W, Ti, and Mo. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive film is formed of a film containing silicon as a main component. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive film is formed of a film containing aluminum or copper as a main component.