JP2002334016A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for saving electric power in the upstream phase of design mainly for a CMOS microprocessor in order to efficiently reduce the power consumption of a semiconductor integrated circuit. SOLUTION: This microprocessor is equipped with an instruction cache for program storage and a control mechanism which stores a part of a program which is executed possibly repeatedly in the instruction cache with priority.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction cache control system for a microprocessor having an instruction cache therein.

[0002]

2. Description of the Related Art A conventional technique will be described below. For simplicity, the cache configuration is determined by the lower X bits of the program address (X is the number of bits according to the cache size; X is 10 if the cache size is 1 Kbyte).
It is assumed that the cache entry in which the program is stored is uniquely determined by the direct map method. However, the same applies to the set associative / full associative method.

FIG. 4 shows a general example of a hierarchical memory for storing a program executed by a microprocessor. Although a program ROM may exist, it is omitted in this figure. Also, the secondary cache in the figure is a dedicated secondary cache bus and uses a CPU (Central Process
ng Unit) instead of being directly connected to the CPU bus, or there may be no secondary cache. The memory size of each hierarchy has the following relationship: main memory> secondary cache> instruction cache, and it is usually impossible to copy all programs on main memory to the cache and make them resident.

A microprocessor is a program counter (PC) that holds an instruction address of a program being executed.
While executing instructions from the address indicated by, they are sequentially executed. If the instruction is already in the instruction cache, it is read from the instruction cache and used. Otherwise, the instruction is fetched from an external memory (main memory or secondary cache in FIG. 4) and newly stored in the instruction cache. . At this time, not only the instruction required at the present time but also a plurality of continuous instructions (instructions for one line of the cache) including the instruction are transferred to the instruction cache. If the corresponding one line is in the secondary cache, a transfer from the secondary cache to the instruction cache occurs, otherwise, a transfer from the main memory to the instruction cache. In the latter case, this one-line instruction is usually copied to the secondary cache. The newly fetched instruction is stored in the cache entry corresponding to that address, but the instruction previously stored in the entry is overwritten and disappears.

A memory element used for a main memory or the like has a large capacity but a low speed, so that a speed gap with a high-speed microprocessor becomes a problem. In order to reduce the gap, providing a small-capacity, high-speed cache memory as a buffer is a memory hierarchy. In a hierarchical memory configuration, the contents held by a layer having a smaller capacity are basically a subset of the contents of a layer having a larger capacity.

Therefore, one entry of the cache is exclusively associated with a plurality of entries of a higher-capacity hierarchy. FIG. 5 shows this state. The area of one line of the cache with the same color in the memory on the large capacity side is stored in the same entry on the small capacity side. That is, instructions whose displacements in the block of the large-capacity memory are located at the same address compete for the same entry in the small-capacity memory. If the entries are different, data of different blocks in the large-capacity memory may exist simultaneously in the small-capacity memory.

Next, the operation will be described. FIG. 6 shows a very simplified arrangement of the program of each process in a general multi-process operating environment. Nested loops and branches are omitted. As aforementioned,
Instructions whose displacements within a block are located at the same address compete for the same cache entry. It should be noted that dotted arrows and circled numbers in the figure indicate locations and order of process switching. Hereinafter, the execution of the program and the state of the cache will be described with reference to FIG.

In the environment shown in FIG. 6, when the process 0 is started, the code of the process 0 stored in the main storage block 0 is sequentially copied to the cache as the CPU executes the program. When the loop A is executed for the first time, the code is copied from the main memory to the cache. However, since the code is executed while being stored in the cache for a while, the code of the loop A is fetched again to the main memory. It does not take on.

Eventually, process switching occurs during execution of loop A of process 0, and process 1 is activated. By the code fetch of the process 1, the code of the process 0 in which the offset addresses within the block overlap is discarded from the cache. Loop B in process 1
Is executed at a certain timing during execution of the program, and the program execution returns to the loop A of the process 0 again.

When process 0 is reactivated, a significant portion of the code in loop A has been discarded from the cache by process 1 and the code must be fetched again externally. When the process switching occurs after the process of the loop A in the process 0 is completed, and the process is passed to the process 1, the loop B previously stored in the cache is discarded by the process 0 in the same manner as described above. No. 1 needs to copy the loop B from the outside to the cache again.

Similarly, while the newly activated process changes the cache state of the previous process,
Process switching,... Occur, and the program execution in the multi-process environment is performed.

[0012]

Problems to be solved by the present invention in the prior art will be described below. As described in the operation of the related art, in an environment where a plurality of processes are processed in parallel, processing proceeds while disturbing the cache state of another process. Since not all programs can reside in the cache, it is inevitable that another code part is discarded from the cache (replacement) in order to put a certain code part in the cache.
In this example, the code that is executed only once discards the code in the loop of another process from the cache. In general, most of the program execution time is spent in a small portion of the loop, and most of the remaining code is executed only once. Such code is disposable and has little performance advantage in storing it in the instruction cache. Further, if the disposable code replaces the valid loop portion code, the loop portion code will later cause a cache miss and must be refetched and copied to the cache. In other words, the presence of a portion that occupies the majority of the program and has little effect by storing it in the cache suppresses the cache hit rate and requires extra power consumption for external refetching. There was a problem.

Further, if the hit rate of the instruction cache is to be improved over a plurality of processes, a large-capacity cache memory must be mounted, which is not preferable in terms of chip cost and power consumption. was there. While the previous example was a problem between different processes in a multi-process environment, the same can occur in cases such as function calls within a single process.

In the above description, the cache structure of the direct map is premised. However, the frequency of occurrence of the above-described problem is reduced in a structure having a higher association (such as set associative). However, not only does the same problem not disappear, but there is also a problem that increasing the degree of association of the cache leads to a complicated circuit and an increase in delay time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to efficiently reduce the power consumption of a semiconductor integrated circuit. And a means for reducing power consumption.

[0016]

SUMMARY OF THE INVENTION A microprocessor according to the present invention includes an instruction cache for storing a program, and a control mechanism for preferentially storing a part of a program that may be repeatedly executed in the instruction cache. It is a thing.

[0017] Further, the program executed by the microprocessor is inside a loop, the CPR of the microprocessor indicating the depth of the loop, and a machine language instruction for setting the contents of the CPR to an arbitrary value. And with.

Further, a machine language instruction is inserted at the entrance of the loop structure of the program and increases the content of CPR by 1 to indicate that the following is inside the loop.

At the end of the loop in the program, a condition determining instruction or a conditional branch instruction for determining whether to repeat the loop or exit from the loop. If the condition for exiting the loop is satisfied, the content of CPR is set to 1 It is provided with a machine language instruction having a function of decreasing only.

An instruction cache (having a function of holding a head instruction address) for one line of the instruction cache is provided at a stage preceding the instruction cache, and performs the following operation when an instruction cache miss occurs. It has a control system.・ CPR content is 0
In the case of (indicating that the program portion is unlikely to be repeatedly executed), at the time of an instruction cache mishit, for example, an instruction for one line fetched from a main memory or the like is stored only in the instruction buffer, and If the value of CPR does not become other than 0 due to execution of the instruction in the instruction buffer, the one line is not stored in the instruction cache. If the value of CPR becomes other than 0 in the instruction buffer, the contents of the instruction buffer are read. Copy to cache. ・ If the contents of CPR are other than 0 (indicating that it is a program part that may be repeatedly executed),
When an instruction cache mishit occurs, the newly fetched one-line instruction is immediately stored in the instruction cache.

A microprocessor provided with a hierarchical cache memory (location may be inside or outside the processor). If the content of CPR is 0, when the instruction cache misses, for example, the main memory The instruction for one line fetched from the instruction buffer is stored only in the instruction buffer, and C is executed by executing the instruction in the instruction buffer.
If the value of PR is not 0, the one line is not stored in the instruction cache but is immediately stored in the secondary cache.

Further, by setting the internal control register or the like, it is possible to switch the mode between execution and non-execution of the mechanism according to the fifth or sixth aspect.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. The present invention is characterized by solving the above problems at a minimum cost while making the most of the prior art. In other words, the goal is to minimize the increase in the circuit scale of the microprocessor and to make the compiler and programs as conscious of the effects of the hardware changes as possible. For this reason, the configuration of the present invention is mostly the same as the conventional technology.

FIGS. 1 to 3 show the first embodiment.
FIG. 2 is a diagram showing an example of CPR (Caching-Priority-Register), FIG. 2 is a diagram showing a relationship between program execution and changes in loop flags (contents of CPR), and FIG. 3 is an explanatory diagram of cache control using CPR.

FIG. 1 shows an example of the CPR according to the second aspect of the present invention. In this example, the entity as CPR is the lower 16 bits of the 32-bit register shown in the figure. The most significant bit (bit 31) is a bit indicating whether or not to enable the cache control using CPR according to claim 5, and the bit 32 is whether or not to enable the control according to claim 7. This is a bit which indicates one embodiment of the present invention.

The contents of the register shown in FIG. 1 change as follows. (1) The initial values are all 0. (2) An arbitrary value is set in the register of FIG. 1. The valid bit of the register of FIG. 1 is set by a program using the instruction described in claim 2, and the cache control using CPR is enabled. (3) In the program simplified in FIG. 2, the instruction according to claim 3 is inserted by a compiler or the like immediately before entering the loop portion, and the CPR is entered at the time of entering the loop.
Becomes 1. (4) When a branch instruction (such as a function call) is executed inside a loop except for a conditional branch instruction for repeating the loop, C
The contents of the PR do not change. (5) If another loop appears inside the loop,
The same operation as in (3) is performed, and the value of CPR increases by one.

(6) If a process different from the program in the loop is started due to the occurrence of an exception or a process change during the execution of the loop, the current CPR is saved by the program or a hardware mechanism and newly started. Is changed to a value of CPR suitable for the performed processing. When the process returns to the inside of the original loop, the contents of the stored CPR are restored.

(7) As an instruction for determining whether or not to repeat the loop, a condition determination instruction or a conditional branch instruction for reducing the content of CPR by 1 according to the result of the condition determination by a compiler or the like is used. When the loop condition is satisfied and the loop is repeated, the contents of the CPR do not change, and the program jumps to the entrance of the loop (immediately after the instruction inserted at (3)). If the condition for exiting the loop is satisfied, the content of CPR is reduced by 1 and the subsequent instruction is executed.

(8) The loop nests very deeply with a very special program (or runaway due to a bug),
The CPR shown in FIG. 1 may overflow.
For such a case, one of the following means is implemented.・ Maximum value of CPR (for example, 0xFFFF), minimum value (0x0000)
Is determined and implemented as a register that does not increase above the maximum value and does not decrease below the minimum value. -When CPR overflows / underflows, exception processing is started and appropriate processing is performed in the handler program.

FIG. 3 is an explanatory diagram of cache control using CPR, and is a model in which only a portion related to the present invention in a microprocessor is cut out. The "instruction buffer" in the figure is as shown in claim 5. The prefetch buffer is a buffer for prefetching a new instruction sequence expected to be used in the near future from the outside of the microprocessor, but may not be provided depending on the system. The instruction fetch unit has a control function for realizing claims 5 and 6 of the present invention, in addition to the function of the instruction fetch unit in the prior art.

Although FIG. 3 assumes a system in which the microprocessor and the secondary cache are directly connected by a dedicated secondary cache bus, as described above, the secondary cache is connected to the CPU bus or the like. In some systems, there is no secondary cache. In a system in which the secondary cache does not exist or the microprocessor cannot control the secondary cache, claim 6 of the present invention is invalid.

Under the control of the CPR as described above, the contents of the CPR change, for example, as shown in FIG. That is, the initial value of CPR when a certain program is started is 0, and when entering a loop portion during execution of the program, the value of CPR becomes 1 by the instruction inserted immediately before the loop portion. When another loop is nested in the loop, the value of CPR is similarly increased by the instruction according to claim 3. Upon exiting the loop, the value of CPR is reduced by the instruction of claim 4. As described above, the value of CPR repeatedly increases and decreases, and the value of CPR becomes a value other than 0 only during the execution of the inside of the loop, and becomes 0 during the execution of the part other than the loop. The manner of changing the CPR at the time of an operation (function call, exception, etc.) not appearing in FIG. 2 is as described above.

Next, the operation according to the fifth and sixth aspects of the present invention using the CPR and the instruction buffer will be described. If an instruction to be executed is already stored in the instruction cache while the microprocessor is executing the program, the instruction is read from the instruction cache and executed. If the instruction to be executed does not exist in the instruction cache, it is determined whether or not an instruction sequence of one cache line including the target instruction exists in the secondary cache. From, otherwise from main memory etc.
An instruction sequence for one line is taken into the microprocessor via the PU bus. The newly fetched instruction sequence is stored in the instruction buffer via the prefetch buffer. When the instruction buffer is empty, as shown by the dotted line in FIG.
There may be a control for bypassing the prefetch buffer and storing an instruction sequence fetched from outside in the instruction buffer.

If the content of the CPR is not 0 at the timing when the microprocessor takes in the instruction sequence from the outside into the instruction buffer (ie, if the loop is being executed),
The instruction fetch unit controls to copy the instruction sequence to the instruction cache. When the instruction sequence was fetched from outside, the content of CPR was 0, but if the content of CPR became non-zero during execution of the instruction in the instruction buffer, the content of the instruction buffer is also copied to the instruction cache. If a valid instruction sequence is already stored in the instruction cache entry to which the contents of the instruction buffer are to be copied, it is discarded. The instruction sequence copied to the instruction cache is also copied to the secondary cache.

If the contents of CPR are 0 throughout the execution of an instruction in the instruction buffer, the instruction sequence in the instruction buffer is not copied to the instruction buffer. Until a new instruction sequence is taken into the instruction buffer, the instruction buffer functions in the same manner as an instruction cache for one line, but the contents up to that point are discarded at the timing when the new instruction sequence is stored. However, in the case of a system having a secondary cache controlled by a microprocessor as shown in FIG. 3, instead of discarding the contents of the instruction buffer without copying it to the instruction cache, copying it to the secondary cache,
The next time the same instruction sequence is required, the speed is increased as compared with the case of retrieving from the main memory (claim 6 of the present invention).

The above operation can be suppressed by the function according to claim 7 of the present invention. V of the register shown in FIG.
If claim 7 is realized with 1, V2 bits, V
The control according to claim 5 is suppressed when 1 is cleared, and the control according to claim 6 is suppressed when V2 is cleared,
Cache control as in the prior art is performed.

When only the fifth aspect of the present invention is applied, if a process switching occurs during execution of a part which is not copied to the instruction cache, it is once taken into the instruction buffer when the processing of the original process is continued. There is a problem that the instructions for one line must be fetched again from the outside. Also, if there is a program which is not loop-structured as a whole but is started many times, the same applies to a portion other than the loop-structured portion. These are compensations for the effects obtained by the present invention, but the damage can be reduced by claim 6 of the present invention. Also, it can be said that it is a trivial problem compared to the effect obtained otherwise. When executing a program in which the disadvantages of claim 5 cannot be ignored, the problem can be avoided by making the operation of the microprocessor conventional, by the mechanism of claim 7 of the present invention.

In the above-described operation of the present invention, when the code size of the loop portion is much larger than the cache size, the above-mentioned effects are not exerted as compared with the prior art, and they are equal. . However, in such a case, the operation method of the CPR is changed so that the CPR is set to 0 in a portion of the loop that is executed only once, and the same operation as described above is performed in the loop, so that the inside of the loop is changed. By storing the loop in the cache with priority, the above-mentioned effect can be partially obtained. In a huge loop,
In order to control the cache more efficiently, for example, JP-A-4-333929 and JP-A-10-55308
It is necessary to use a mechanism such as that disclosed in Japanese Patent Application Laid-Open No. H10-209139. In this case, the hardware becomes significantly more complicated than the present invention.

Embodiment 2 In the above description, the cache configuration of the direct map is premised. However, the configuration of the set associative / full associative can obtain a further effect. Further, the maximum effect can be obtained with the support of the compiler such that the loop portion of the program is arranged at an address which does not compete for the same cache entry.

The performance improvement obtained by the present invention, for example, similar to that of JP-A-6-243036 may have a small degree, but has the effect of reducing the hardware cost. Further, according to the present invention, when the compiler inserts an instruction for controlling the cache of the loop portion, it is only necessary to perform a uniform operation for each loop portion, so that the load on the compiler is lighter than that of the prior art. There is also an effect.

Further, there is an effect that a program whose execution frequency is low but fetch overhead cannot be ignored can be preferentially stored in the cache. For example, in the case of interrupt processing that requires high-speed execution in a real-time system, by controlling the CPR in the interrupt handler, even if it is not actually inside the loop, control is performed so that the entire interrupt processing part is stored in the cache with priority. Is also possible.

[0042]

According to the present invention, in order to effectively utilize the instruction cache having a limited capacity, the program of the loop portion is preferentially stored in the instruction cache, thereby improving the hit rate of the instruction cache. As a result, there is an effect that the performance of the microprocessor is improved. Further, since the number of instruction fetches from the outside is reduced, there is also an effect of reducing power consumption of the microprocessor. Further, since a hit rate equivalent to that of the related art can be realized with a smaller cache capacity, there is an effect of reducing the cost of the microprocessor, and also in this respect, there is an effect of reducing power consumption.

According to the invention of claim 7, according to claim 1,
On the contrary, in a special environment in which the disadvantages are caused by the implementation of the inventions of the sixth to sixth aspects, the expression of the above-described invention is suppressed, and the same operation as that of the related art is effectively eliminated. Claims 1 to 5 in various aspects.
There is also an effect that the effect of No. 6 can be quantitatively evaluated.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating Embodiment 1 and illustrates an example of CPR.

FIG. 2 is a diagram showing the first embodiment and is a diagram showing a relationship between program execution and a change in a loop flag (contents of CPR).

FIG. 3 shows the first embodiment and is an explanatory diagram of cache control using CPR.

FIG. 4 is a diagram illustrating a conventional technique, and is a diagram illustrating a hierarchical structure of a general memory related to program storage.

FIG. 5 is a diagram showing a conventional technique, and is a diagram showing correspondence of entries between hierarchical memories.

FIG. 6 is a diagram illustrating a conventional technique, and is a diagram illustrating an example of code arrangement under a multi-process operation environment.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 9/38 310 G06F 9/38 310A

Claims (7)

[Claims] 1. A cache memory for storing a program (hereinafter referred to as an instruction cache), and a control mechanism for storing a part of a program which may be repeatedly executed in the instruction cache with priority. And a microprocessor. 2. A microprocessor internal register (hereinafter referred to as C) which indicates that a program being executed by the microprocessor is inside a loop and indicates the depth of the loop.
PR; called Caching-Priority-Register) and CP
A machine language instruction for setting the content of R to an arbitrary value. 3. A microprocessor provided with a machine language instruction inserted at the entrance of a loop structure of a program to increase the content of CPR by one to indicate that the following is inside a loop. 4. At the end of the loop in the program, a conditional judgment instruction or a conditional branch instruction for judging whether to repeat the loop or to exit from the loop. If the condition for exiting the loop is satisfied, the content of CPR is set to 1 A microprocessor having a machine language instruction having a function of decreasing only. 5. An instruction cache which has an instruction buffer for one line of the instruction cache (provided with a function of holding a leading instruction address) at a stage preceding the instruction cache and performs the following operation when an instruction cache mishit occurs. A microprocessor characterized by having a control method.-When the content of CPR is 0 (indicating that the program portion is unlikely to be repeatedly executed), when the instruction cache mishits, for example, the main memory is used. The fetched instruction for one line is stored only in the instruction buffer, and the value of CPR becomes 0 by executing the instruction in the instruction buffer.
Otherwise, the one line is not stored in the instruction cache, but is disposable. If the value of CPR is not 0 in the instruction buffer, the contents of the instruction buffer are copied to the instruction cache. Is other than 0 (indicating a program part that may be repeatedly executed), when an instruction cache mishit occurs, the newly fetched one-line instruction is immediately stored in the instruction cache. 6. A microprocessor provided with a hierarchical cache memory (location may be inside or outside of the processor). If the content of CPR is 0, an instruction cache miss occurs, for example, in a main memory. The instruction for one line fetched from the instruction buffer is stored only in the instruction buffer. If the value of CPR does not become other than 0 due to the execution of the instruction in the instruction buffer, the one line is not stored in the instruction cache. A microprocessor stored in a secondary cache. 7. By setting an internal control register or the like,
A microprocessor capable of performing mode switching between execution and non-execution of the mechanism according to claim 5 or 6.