JP2002333934A - Inter-frame failure informing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inform an adjacent frame of a failure of power source disconnection detected by a frame. SOLUTION: A power source disconnection signal transmitting buffer 101 of an inter-frame bus interface card (inter-frame I/F) 61 normally outputs 'L', and when a power source disconnection of an inter-frame I/F 62 of a frame 2 is detected by a power source disconnection detecting part 82, the gate terminal of a power source disconnection signal transmitting buffer 102 is closed. The output of the power source disconnection signal transmitting buffer 102 of the inter-frame I/F 62 is turned into 'H' according to pull-up PU in an inter-frame I/F in the next stage, and the power source disconnection signal receiving buffer of the inter-frame I/F in the next stage is informed of this. The failure processing by the power source disconnection is executed in the inter-frame I/F in the next stage, and the output of the power source disconnection signal transmitting buffer is held to be 'H'. This state is continued until an inter-frame I/F 6n in the final stage, and a power source disconnection signal receiving buffer 201 of the inter-frame I/F 61 of a frame 1 is informed of 'H'. The power source disconnection signal receiving buffer 201 closes the gate terminal of a clock output buffer 301, and stops the transmission of any clock from a clock source 601.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame failure notification system, and more particularly to a chassis (hereinafter, "frame") having a plurality of units and power supply means for supplying power to these units. ) Relates to a system for notifying an inter-building fault in a bus system sequentially connected to a bus.

[0002]

2. Description of the Related Art Conventionally, in a bus system in which a plurality of units connected in a bus and connected in multiple stages are sequentially connected in a bus system, when a certain unit is powered off and a failure occurs, the power supply is installed in the unit. Although a function for detecting a disconnection failure was provided, an independent path for notifying the failure to a rack connected to the next stage was not provided. Therefore, when a failure occurs due to power interruption in a certain frame, the inter-frame bus interface card in the unit configuring the frame detects this and notifies the higher-level bus system control unit via the bus line. Was.

In the bus system control section, the path of the inter-bus interface card is switched from the active system when the power system is normal to the standby system when the power system is abnormal for all the frames constituting the bus system through the bus line. Notification of switching is performed. For this reason, in a multistage-connected bus system, an instruction for a failure process such as system switching due to a power failure occurring on an adjacent rack has been notified only from an upper-level bus system control unit and has been dealt with.

[0004]

However, in the above-mentioned conventional bus system, there is no means for notifying an adjacent rack of a power failure, so that the power failure detected by the inter-bus interface card is superordinated. After the notification to the bus system control unit, a certain processing time is required from when the bus system control unit recognizes the power interruption fault to when the fault processing is performed. Particularly, in a bus system in which a plurality of racks are sequentially connected by a bus to perform bus communication, even if a power failure occurs in an adjacent rack, only a notification is given from the bus system control unit. However, there is a problem that it cannot be dealt with immediately.

[0005] In addition, since it takes time to switch the system due to a power failure, a state in which the power supply voltage is unstable for a certain period of time continues. During this time, transmission of transmission data and clock data itself is not stopped, so that there is a problem in that unstable levels of clock data and incorrect transmission data are transmitted. That is, even if a power failure occurs, it cannot be dealt with immediately, and wasteful data and clocks are transmitted.

Accordingly, the present invention has been made to solve the problems of the prior art, and it is an object of the present invention to quickly perform a failure process due to a power failure and to perform an unstable process when the failure process is performed. It is an object of the present invention to provide an excellent inter-chassis fault notification system that prevents transmission of clock data of a level and erroneous transmission data.

[0007]

According to the present invention, a housing (hereinafter referred to as a "frame") having a plurality of units and power supply means for supplying power to these units is provided.
A frame failure notification system in a bus system that is sequentially connected to a bus, wherein each of the frames includes a detection unit configured to detect a disconnection of the power supply, and responds to the disconnection detection performed by the detection unit, and transmits the detection result to a bus. And a notifying unit for notifying the connected next stage of the frame.

[0008] At least one of the frames has clock supply means for supplying a clock to the bus system, and controls the clock supply to be stopped in response to a notification from the notification means. It is characterized by further including means.

[0009] The power supply means, the detection means, the notification means, and the control means are provided in a cross bus interface card in the unit, and the rack is a data switch. It is characterized by the following.

The operation of the present invention will be described. Means for detecting power interruption and means for notifying the detection result to the rack connected to the next stage are provided in the inter-frame bus interface card provided in each of the plurality of racks constituting the bus system. Upon receiving this notification, the inter-frame bus interface card of the next stage recognizes that the power of the previous stage has been cut off, and instructs a plurality of units constituting the own stage to perform a failure process, The next stage is notified to that effect. Further, the same processing is performed on the next stage, and finally, a failure due to power interruption is notified to a higher-order frame. A clock supply source for transmitting a clock to the entire bus system is provided in the inter-frame bus interface card of the upper frame, and this clock is supplied based on a power-off notification notified from the last stage of the bus system. Is controlled to stop sending. As a result, even if a power failure occurs, fault processing is immediately performed, and unnecessary clock component transmission is suppressed.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a system for notifying a trouble between frames according to an embodiment of the present invention. In FIG. 1, a rack 1 composed of a plurality of units 11 to 15 connected to each other by a bus line 10,
A plurality of units 21 connected to each other by a bus line 20
To 25, and a frame 3 including a plurality of units 31 to 35 connected to each other by a bus line 30 are sequentially bus-connected.

Each of the units 11 to 14, 21 to 24 and 31 to 34 constituting the rack 1, the rack 2, and the rack 3
Bus interface cards 41 to 4
3 and the line bus interface cards 51 to 53 are mounted.

Further, the unit 15 of the frame 1 includes a frame bus interface card 61 and a system control card 7, and the unit 25 of the frame 2 includes a frame bus interface card 62 and a line bus interface card 52.
In the unit 35 of the frame 3, an inter-frame bus interface card 63 and a line bus interface card 53 are mounted respectively.

The bus interface card 61 of the frame 1 and the bus interface card 62 of the frame 2 are connected by the bus line 100 to the bus interface card 62 of the frame 2 and the bus interface card 63 of the frame 3. Is connected by a bus line 200, and the inter-frame bus interface card 63 of the frame 3 and the inter-frame bus interface card 61 of the frame 1 are connected to each other by a bus line 300. Although FIG. 1 shows a case in which three racks are connected as a bus system, the number of connected racks can be arbitrarily set up to a maximum of eight.

Further, the system control card 7 of the rack 1 controls a failure detection of the entire bus system, a stop of the service, a switching, and the like. Terminals (not shown) are connected to the line interface cards 51 to 53 of each unit, and the terminals communicate with each other by performing communication between the line interface cards 51 to 53. That is, each frame 1
Reference numeral 3 denotes a data exchange which exchanges data between terminals. The method of communication between the bus interface cards 61, 62, and 63 shown in FIG. 1 is generally well known, and is not directly related to the present invention. Omitted.

Next, referring to FIG. 2, there is shown a connection state of the crossover bus interface card constituting the crossover failure notification system of the present invention. In FIG. 2, the present system is composed of n units of a rack 1 to a rack n, and the rack n is a last rack of the system. In FIG. 2, the same parts as those in FIG. 1 are indicated by the same reference numerals.

In FIG. 2, the inter-frame bus interface card 61 of the frame 1 includes units 11 to 15 constituting the frame 1.
A power supply 71 for supplying power to the power supply, a power-off detection unit 81 for detecting the power-off of the power supply 71, an alarm unit 602 for issuing a warning when the power-off detection is detected from the power-off detection unit 81, and a power-off detection unit 81 Power-off signal transmission buffer 101 for notifying a power-off signal from the power supply, a clock source 601 for supplying a clock to the entire system, and a power-off signal for receiving a power-off signal notified from the last stage of the bus system It comprises a receiving buffer 201, a pull-up (PU) 91 connected to its input, and a clock output buffer 301 for controlling clock supply from a clock source 601.

The bus interface cards 62 to 6n between the frames 2 to n have the same configuration, and power sources 72 to 7n for supplying power to the units constituting the respective frames.
And a power-off detecting section 8 for detecting the power-off of the power supplies 72 to 7n.
2 to 8n and a power-off signal transmission buffer 102 to notify a power-off signal from the power-off detection units 82 to 8n to the next stage.
10n, power-off signal receiving buffers 202 to 20n for receiving a power-off signal notified from a previous stage rack, and pull-up (PU) 92 to 9n connected to the inputs of the power-off signal receiving buffers 202 to 20n. It is composed of

Further, the input of the power cut-off signal transmission buffer 101 of the frame bus interface card 61 of the frame 1 is connected to the ground, and the output is connected to the input of the power cut signal reception buffer 202 of the frame bus interface card 62 of the frame 2. It is connected. The output of the power-off detection unit 81 is connected to the gate terminal of the power-off signal transmission buffer 101. The input of the power-off signal receiving buffer 202 is set to PU9 so that the input of the buffer does not become high impedance.
2, it is pulled up to its own power supply 72.

The power-off detecting sections 81 to 8n are connected to the power supply 7
1 to 7n are normal, a value obtained by dividing the output voltage of each of the power supplies 71 to 7n at a predetermined ratio is used as the power-off signal transmission buffer 1.
Each of the buffers is turned on by outputting to the gate terminal of 01 to 10n, and when the power supply 71 to 7n is cut off, the divided voltage value is not output.
The gate terminal of n is closed and each buffer is off.

The output of the power-off signal receiving buffer 202 of the frame bus interface card 62 of the frame 2 is output inside the frame bus interface card 62,
And the inputs of the power-off signal transmission buffer 102. In addition, the clock output buffer 301 of the frame bus interface card 61 of the frame 1
Are connected to the inter-frame bus interface cards 62 to 6n, and a clock is supplied to each frame.

The output of the power-off detection unit 82 is connected to the gate terminal of the power-off signal transmission buffer 102, and the output of the power-off signal transmission buffer 102 is used to receive the power-off signal of the next stage bus interface card. Connected to input of buffer. The input of the power-off signal receiving buffer 201 of the frame bus interface card 61 of the frame 1 is connected to the frame bus interface card 6n of the last stage n, and outputs the power-off signal notified from the power-off signal transmission buffer 10n. Receive. The output of the power-off signal receiving buffer 201 is connected to the inside of the inter-frame bus interface card 61, that is, to the units 11 to 15 constituting the frame 1.

Next, the operation of the cross-over fault notification system according to one embodiment of the present invention will be described in detail with reference to FIG. First, in the present system, if no power failure occurs, any of the power failure detection units 81 to 81 of the frames 1 to n
8n, the power-off signal is not detected, so that the power-off signal transmission buffers 101 to 10n are turned on, and the “L” level output from the power-off signal transmission buffer 101 of the inter-bus interface card 61 of the frame 1 is in the middle. The logic is not changed and sent to the frames 2 to n as they are.
It returns to the rack 1 again at the L "level state.

Here, for example, when a power interruption occurs in the frame 2 and the interruption of the power supply 72 is detected by the power interruption detecting section 82, the gate terminal of the power interruption signal transmission buffer 102 is closed. Is turned off, and the “L” level output from the power-off signal transmission buffer 101 is not transmitted to the power-off signal transmission buffer 102 and thereafter, and the “L” level is connected to the input of the power-off signal reception buffer of the next stage. As a result of the up (PU), the output line of the power-off signal transmission buffer 102 becomes “H” level, and is input to the power-off signal reception buffer of the next interstage bus interface card.

In the next stage, the change in the input logic of the power-off signal receiving buffer recognizes that a power-off failure has occurred in the frame 2, and the output of the power-off signal receiving buffer recognizes that the power-off signal has occurred. Move the unit to failure processing. In the frames after the frame 2, since the power supply of the frame itself is not turned off, the power-off signal transmission buffer remains in the ON state, but the final state is changed due to a change in the input logic of the power-off signal reception buffer. All the frames up to the stage n and the stage 1 shift to the failure processing.

The "H" level output of the power-off signal transmission buffer 10n of the final stage frame n is output from the power-off signal reception buffer 201 of the inter-frame bus interface card 61 of the frame 1.
, And the “H” level is also output to the output of the power-off signal reception buffer 201. The power cutoff signal receiving buffer 201 is connected to the clock output buffer 3.
01 gate terminal is closed. As a result, the clock output buffer 301 is turned off, and the clock supply from the clock source 601 to the frames 2 to n is stopped.

Next, a case where a power failure occurs in the rack 1 will be described. The rack 1 is a rack for controlling the system, and the inter-frame bus interface card 61 of the rack 1 is connected to the system control card 7 for detecting a failure of the entire system as described above. Here, the CPU 70 in the system control card 7 periodically sends an alarm
Is performed, and when a warning from the alarm unit 602 is detected, or when there is no response from the alarm unit 602 for a predetermined time, it is determined that the power supply 71 of the rack 1 has been turned off.
The gate terminal of the power-off signal transmission buffer 101 is closed according to the detection result of the power-off signal detection unit 81 to turn off the power-off signal transmission buffer 101, and the logic level of the output line of the power-off signal transmission buffer 101 is set to “H”. Thereafter, the operations performed in the inter-frame bus interface cards of the frames 2 to n are the same as those in the case where the power is cut off in the frame 2 as described above, and thus the detailed description is omitted.

FIG. 3 shows a timing chart in the case where a power failure occurs in the frame 2 in the frame failure notification system of FIG. Referring to FIG.
The output, the output of the power-off signal transmission buffer 102, and the output of the clock output buffer 301 indicate the timing of the portions corresponding to 1 to 3 in FIG. In the frame bus interface card 62 of the frame 2, the power supply 72
Occurs, the output of the power supply 72 continues to be unstable as the voltage decreases, and eventually reaches 0V. At this time, when the power-off detecting unit 82 detects the power-off,
Since the gate of the power-off signal transmission buffer 102 is closed and the power-off signal transmission buffer 102 is turned off, the power-off signal is generated by a pull-up (PU) connected to the input of the power-off signal reception buffer in the next stage. Transmission buffer 102
Changes from “L” to “H”.

Then, the "H" level of this power-off signal is notified to the frame bus interface card of the frame 2 and subsequent frames, and the frame bus interface card 6n of the last stage n.
Then, the process returns to the frame bus interface card 61 of the frame 1.
Further, the power-off signal receiving buffer 201 of the frame 1
When recognizing the “H” level, the clock output buffer 301
Clock output buffer 30 to close the gate terminal of
1 is turned off, and the clock output of the clock output buffer 301 is stopped.

As described above, according to the present invention, the notification of the power-off is sent to the bus interface card between the frames adjacent to the frame in which the power-off occurred, so that the fault detection and the fault processing can be performed quickly. In addition, since the clock supply is stopped after the power failure occurs, it is possible to prevent transmission of an unnecessary clock or erroneous data.

It should be noted that the present invention is not limited to the above-described embodiment, but can be appropriately modified within the scope of the technical idea of the present invention. For example, in the above-described embodiment, the rack 1 is provided with a function of controlling the entire system, but it is also possible to provide a control function on any rack constituting the system.

Further, in the above embodiment, the power supply failure is notified by closing the gate of the output buffer and converting the logic level in the middle of the frame constituting the system. It is obvious that the present invention is not limited to the output buffer circuit as long as it can be notified on the frame of the present invention, and that the present invention can be realized by using other circuits.

[0033]

As described above, according to the present invention, when a power-down failure is detected in any of a plurality of frames constituting a bus system, the power-down signal transmission buffer in the inter-bus interface card is reset. This is notified to the power-off signal reception buffer in the bus interface card of the next stage via the next stage, and is notified sequentially to all the frames constituting the bus system. In all of the frames, there is an effect that it is possible to immediately shift to the failure processing without waiting for an instruction from the upper bus system control unit.

Further, according to the present invention, the clock supply source of the bus system is provided based on the power-off failure notification notified from the power-off signal transmission buffer in the last-stage overhead bus interface card constituting the bus system. Is stopped, transmission of unstable clock data or erroneous transmission data at the time of occurrence of a power failure can be stopped.

[Brief description of the drawings]

FIG. 1 is a block diagram of an inter-system fault notification system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a connection state of an inter-bus interface card of the present invention.

FIG. 3 is a timing chart when a power failure occurs in the present invention.

[Explanation of symbols]

1, 2, 3, 7 System control card 10, 20, 30, 100, 200, 300 Bus line 11, 12, 13, 14, 15, 21, 22, 23, 2
4, 25, 31, 32, 33, 34, 35 Units 41, 42, 43 Bus interface card between units 51, 52, 53 Line interface card 61, 62, 63 Bus interface card between frames 70 CPU 71, 71, 7n Power supply 81, 82, 8n Power-off detection section 91, 92, 9n Pull-up (PU) 101, 102, 10n Power-off signal transmission buffer 201, 202, 20n Power-off signal reception buffer 301 Clock output buffer 601 Clock source 602 Alarm section

Claims (4)

[Claims] An enclosure in a bus system in which a housing (hereinafter, referred to as a “frame”) having a plurality of units and power supply means for supplying power to these units is sequentially connected to a bus. A notification system, wherein each of the racks is a detection unit configured to detect a disconnection of the power supply;
Notifying means for notifying the detection result to a next frame connected to the bus in response to the disconnection detection by the detecting means. 2. A control, wherein at least one of the racks has a clock supply unit for supplying a clock to the bus system, and controls to stop supplying the clock in response to a notification from the notification unit. The system according to claim 1, further comprising means. 3. The unit according to claim 1, wherein the power supply unit, the detection unit, the notification unit, and the control unit are provided in an inter-bus interface card in the unit. A system for notifying faults between frames. 4. The system according to claim 1, wherein the rack is a data exchange.