JP2002329767A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of substrate per an unit volume of cassette of a vertical heat treatment apparatus. SOLUTION: When taking in/out the substrate from the cassette by a robot arm, a relative position between the substrate and the substrate remained in the cassette is taken here to be always in a state as shown in Fig. 1 (c). When in such a relative position, since the distance between the substrate 101 and the substrate 103 does not become smaller than the distance between the substrate d (Fig. 1 (e)), the transfer equipment can have an allowance and the distance between the substrates can be made smaller. Meanwhile, when the relative position between the substrate and the remained in the cassette is in a state as shown in Fig. 1 (d), the distance between the substrates becomes smaller than the distance d between the substrates, therefore, the transfer equipment can not have an allowance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using an apparatus for carrying a heat treatment by accommodating a large-area substrate by transport. There are two types of apparatuses for performing heat treatment: one for performing heat treatment with a plurality of substrates adjacent to each other in the vertical direction, and one for performing heat treatment with multiple substrates adjacent to each other in the horizontal direction. The present invention relates to a method for performing heat treatment in a state where a plurality of heat treatments are adjacent to each other in a direction.

[0002]

2. Description of the Related Art Generally, a heat treatment step is indispensable in a semiconductor device manufacturing process. The heat treatment step includes a thermal oxidation step of the semiconductor film, a crystallization step of the semiconductor film, and a hydrogenation step. A vertical heat treatment apparatus is often used in this heat treatment step. A vertical heat treatment apparatus used in a manufacturing process of a semiconductor device performs a process in which a plurality of substrates on which a semiconductor film is formed are arranged in a vertical direction, and thus is called by such a name. In the present specification, the vertical direction does not have to exactly match the direction of gravity. A vertical heat treatment apparatus which is apparently inclined with respect to the direction of gravity has also been devised. The plurality of substrates are adjacent at a certain interval,
Usually, this spacing is similarly designed between any substrates. In this case, the perpendiculars of the substrates coincide with the vertical direction, and when the plurality of substrates arranged from above are viewed from above the substrates, all the substrates appear to overlap. Although there is a similar apparatus called a horizontal heat treatment apparatus, this apparatus performs processing by arranging a plurality of substrates in a horizontal direction. In this case, the perpendicular of the substrate coincides with the horizontal direction.

[0003] A vertical heat treatment apparatus is preferably used in a semiconductor device manufacturing process because the size of a footprint is suppressed as compared with a horizontal heat treatment apparatus. In general, the price per unit area of a clean room is very high, so that a device with a small footprint is required for cost reduction. Also, the vertical type has a feature that impurities are less likely to be mixed into the heat treatment chamber.

An overview of a vertical heat treatment apparatus will be described with reference to FIG. In order to prevent impurities from being mixed, a room where the substrate is heat-treated is formed of a quartz tube 201, around which a heater unit 202 is disposed. The heater unit can raise the temperature of the substrate to a desired temperature. Below the quartz tube 201 is a quartz boat 203 for accommodating the substrate, and below it, a quartz table 2.
04 is arranged.

[0005] The quartz boat 203 has a plurality of projections formed thereon for supporting the substrates. The plurality of substrates can be accommodated in the quartz boat by holding the substrates on these projections. A quartz table 204 is provided below the quartz boat 203, and is usually arranged in a quartz tube at a portion where the temperature is not uniform. Substrate is quartz boat 20
Then, the quartz boat 203 is moved upward by the boat elevator unit 205 and stored in the quartz tube. When the quartz boat moves to the top, the inside of the quartz tube is sealed. Thereby, the atmosphere in the heating area can be controlled. In addition, the quartz tube is placed in the high pressure vessel 206.
, It is possible to control the pressure inside the quartz tube.

In order to take the substrate in and out of the quartz boat, a transfer method using a robot is generally employed. That is, a method is generally adopted in which a substrate is placed on a robot arm and carried into and out of a quartz boat one by one. In addition, what accommodates the substrate as represented by the quartz boat is referred to as a cassette in this specification. Examples of apparatuses using a cassette include a transfer machine, a vertical heat treatment apparatus, and a substrate cleaning apparatus.

[0007]

The size of a glass substrate used in a mass production factory of semiconductor devices formed on the glass substrate is, for example, 300 × 400 mm, or 60 × 400 mm.
It is 0 × 720 mm, and the thickness is about 0.3 to 1.1 mm. The thickness of the glass substrate tends to be reduced due to demands for weight reduction and cost reduction of the substrate, and the standard thickness in the future is considered to be about 0.4 to 0.8 mm.
Therefore, in order to transfer such an extremely thin large-area substrate on the robot arm, it is necessary to design an apparatus in consideration of the warpage of the substrate. In fact, when a large-area substrate is transported using a robot arm, it can be seen that the substrate is greatly bent. Therefore, when storing the substrates in the quartz boat, adjacent substrates will come into contact with each other unless the distance between the substrates is made large to some extent. However, if the distance between the substrates is too large, either the height of the ceiling of the clean room becomes too high, or the number of substrates that can be processed at one time in the vertical heat treatment apparatus becomes too small. In any case, these problems lead to high costs. In general, the heat treatment step in the process of manufacturing a semiconductor device has a very high cost per process, so that an improvement in processing capacity leads to a large cost reduction.
The present invention provides a technique necessary for increasing the number of substrates that can be accommodated in an apparatus by further reducing the distance between the substrates.

[0008]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems by improving the procedure for transferring a substrate. Or,
The above problem is solved by devising the shape of the robot arm and the shape of the cassette in which the substrates are stored. The present invention will be described with reference to FIG. Generally, when the substrate 101 is held by the robot arm 102, warpage occurs due to the weight of the substrate. The amount of this warpage is defined as t1. (FIG. 1A) A substrate 103 similar to the substrate 101 is placed on a quartz boat 10.
When the substrate is accommodated in the substrate, the substrate is warped due to its own weight. The amount of this warpage is defined as t2. (Fig. 1 (b))
The substrate 103 is held by the protrusion 105. The thickness of the robot arm is set to t3.

Here, a case is considered in which substrates are stored in a quartz boat in order from the top. In this case, this corresponds to FIG. 1 (d), and the center between the substrate stored immediately before and the substrate to be stored next comes very close due to the warpage of the substrate. It is necessary to increase the width more than when there is no warpage. Assuming that the distance between adjacent substrates when the maximum number of substrates is put in the quartz boat 104 is d, when the substrates are stored in order from above, the distance between the substrates is d− (t1
+ t2). FIG. 1E shows the distance d between the substrates. Here, the inter-substrate distance d is usually a constant value, but if there is a different inter-substrate distance, it is defined by their minimum value. Therefore, d> t1 + t2 (1) must be satisfied. In general, as the substrate becomes larger and the substrate becomes thinner, t1 + t2
Is larger, so that conditional expression (1) is more restrictive. At present, the size of each side of a glass substrate used in a mass production site is about 600 × 720 mm, and the thickness is about 0.4 to 0.8 mm. For example, the size of each side is 600 × 720 mm. When a glass substrate having a thickness of 0.7 mm is used, t1 = 5 mm and t2 = 10 mm.
These values largely depend on the width of the robot arm and the length of the projection 105 of the quartz boat. However, the width of the robot arm is about 100 mm, and the length of the projection 105 of the quartz boat is several mm to several tens of mm. It was considered as the case. At this time, conditional expression (1) satisfies d> 15 mm. Due to the operation of the machine, there must be enough room above and below the robot arm when loading and unloading substrates. When the substrates are loaded in order from above the quartz boat, a margin required above the substrate on the robot arm is D1, and a margin below the substrate on the robot arm is D2. (FIG. 7 (a)) Since it is preferable that both D1 and D2 have at least about 5 mm, the distance d between the substrates is d.
It is better to set 15 + 5 + 5 = 25 mm or more. D1, D2
Depends greatly on the operation accuracy of the robot, so that the higher the accuracy, the smaller the value. It is needless to say that D1 and D2 are preferably as small as possible from the gist of the present invention. That is, conditional expression (1) is further restricted, and d> t1 + t2 + D1 + D2 (2).

On the other hand, when substrates are stored in order from below the quartz boat, this corresponds to FIG. 1C, and d is limited by the following equation. That is, d> t3 (3).

Since t3 is generally about 5 to 10 mm, the conditional expression (3) is less restrictive than the case of the conditional expression (1). In addition, since the value of t3 becomes smaller as the strength of the arm increases, the limit of the conditional expression is further reduced. Therefore, if the substrates are stored in order from the bottom of the quartz boat, and if the distance between the substrates satisfies conditional expression (3), the distance d between the substrates can be reduced, the number of substrates that can be stored in the quartz boat increases. And
Processing efficiency is improved. In order to have a margin above and below the substrate as considered in the conditional expression (1), the expression (3) is restricted, and d> t3 + d1 + d2 (4).

Here, when the substrates are carried out in order from above the quartz boat, a margin required above the robot arm is defined as d1, and a margin required below the robot arm is defined as d2. (FIG. 7B) Both d1 and d2 should be at least about 5 mm. Since d1 and d2 greatly depend on the operation accuracy of the robot, the values can be reduced as the accuracy increases. From the gist of the present invention, d1,
Needless to say, d2 is preferably as small as possible. Here, due to the structure of the transfer device, d1 + d2 is D1 + D
It can be considered almost the same as 2.

From the above considerations, the present invention is characterized in that the substrates are sequentially carried out from above the cassette and that the substrates are carried in from below the cassette.

Therefore, from the equations (2) and (4), the distance d between the substrates that can be set only by the present invention is t1 + t2 + D1 + D2 = t1 + t2 + d1 + d2>d> t3 + d1 + d2 ... (5)

In order to make d2 as small as possible, it is advisable to devise the shape of the robot arm. This will be described with reference to FIG. In order to make d2 smaller, the lower surface of the robot arm 218 may have a curvature 1 convex outward. That is, in this case, when carrying in / out the substrate with the robot arm 218, the robot arm 2
18 and the robot arm 218
Since the probability of contact with decreases, d2 can be designed smaller. The curvature 1 may be equal to the curvature of the substrate held by the protrusion 105. In addition, in order to reduce the probability of a substrate transfer error, the curvature of the warp of the substrate held by the robot arm and the curvature protruding outward on the upper surface of the robot arm are matched with each other, so that the When the contact area with the arm is increased, the frictional force is dispersed in the substrate, and the substrate is hardly damaged, which is preferable. In addition, when the contact area is large, the transfer of the substrate takes a stable period, so that the transfer can be performed with higher accuracy. Therefore,
d1 and d2 can be designed to be small. Details are described in Example 3.

In order to further reduce d1 and d2, for example, as in a projection 216 shown in FIG. 10D, the surface holding the substrate and the surface located below the surface are inclined with respect to the horizontal plane. The inclination is preferably set in a direction in which the volume of the space in the cassette increases. As a result, the volume of the space in the cassette increases, and the probability of contact between the substrate and the cassette further decreases.

The present invention is effective in a semiconductor device manufacturing process, particularly an SPC process requiring a high temperature or a gettering process. Here, the SPC process refers to a crystallization process of a semiconductor film using solid phase growth of the semiconductor film. Further, the gettering step here refers to a step of reducing the impurity concentration in a semiconductor film in a certain region for the purpose of improving the characteristics of a semiconductor device. It goes without saying that the higher the temperature of the process, the higher the cost of the process. In this heat treatment, it is very important to suppress oxidation of the semiconductor device. In order to prevent this oxidation, for example, heat treatment may be performed in a state without oxygen such as a nitrogen atmosphere, or heat treatment may be performed under reduced pressure. This allows
Oxygen concentration decreases. The pressure is suitably about 10 to 10000 Pa. The above-mentioned pressure range is a range in which the substrate can be efficiently heated without using radiation and is effective in preventing oxidation of the semiconductor device.

The shape of the robot arm may be a fork type robot arm 2200 as shown in FIG. Also, other shapes may be used.

The present invention will be described below. The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of: transporting a plurality of substrates to a cassette by a robot arm, adjoining the plurality of substrates at an interval d in a vertical direction, and heat-treating the plurality of substrates. The relationship between the thickness t3 of the substrate, the warp t1 of the substrate generated while the substrate is held by the robot arm, and the warp t2 of the substrate stored in the cassette is represented by a conditional expression t1 + t2 + d1. + d2>d> t3 +
d1 + d2, where d1 is the distance between the robot arm and the substrate located above the robot arm when the substrate is carried in and out of the cassette, and d2 is the distance between the substrate and the substrate. A distance between the robot arm and the substrate positioned below the robot arm at the time of loading and unloading, wherein the robot arm sequentially loads the plurality of substrates from under the cassette; Transferring the plurality of substrates sequentially from the upper side of the cassette by a robot arm.

Another structure of the present invention is that a plurality of substrates on which semiconductor films are formed are transported to a cassette by a robot arm, the plurality of substrates are adjacent to each other at an interval d in a vertical direction, and the plurality of substrates are heat-treated. In the method for manufacturing a semiconductor device, the thickness of the robot arm t3, the warp t1 of the substrate generated when the substrate is held by the robot arm, and the warpage of the substrate stored in the cassette The relationship with the warp t2 is determined by the conditional expression t1 + t2 + d1 + d2>
d> t3 + d1 + d2, where d1 is the distance between the robot arm and the substrate located above the robot arm when the substrate is carried in and out of the cassette, d
2 is a distance between the robot arm and the substrate located below the robot arm when the substrate is carried in and out of the cassette, and the robot arm moves the plurality of substrates under the cassette. And a step of carrying out the plurality of substrates in order from the top of the cassette by the robot arm.

In the above invention, the size of one side of each of the substrates is 300 × 400 mm or more;
That is, it is suitable for applying the present invention that the area of the substrate is 120,000 mm ² or more and the thickness of the substrate is 0.3 to 1.1 mm. The thickness of the substrate is preferably 0.4 to 0.8 mm for applying the present invention.

In the above invention, it is preferable that the upper surface of the robot arm has a curvature that is convex toward the outside of the robot arm, because the transfer accuracy is further improved. It is preferable that the lower surface of the robot arm has a convex curvature toward the outside of the robot arm, because the distance between the substrates stored in the cassette can be reduced.

In the above invention, the projection holding the substrate of the cassette holds the substrate on a surface inclined from a horizontal plane, and the inclined surface is a surface whose height decreases toward the center of the substrate. This is preferable because the distance between the substrates housed in the cassette can be further reduced.

In the above invention, the surface of the projection that holds the substrate of the cassette under the surface of holding the substrate is a surface whose height increases toward the center of the substrate. This is preferable because the distance between the substrates accommodated in the substrate can be reduced.

In the above invention, if the heat treatment is an SPC process for a semiconductor thin film, the effect is high in terms of reduction in manufacturing cost. Alternatively, if the heat treatment is a step of gettering impurities in the semiconductor thin film, the effect is high in terms of reduction in manufacturing cost.

In the above invention, it is preferable that the heat treatment is performed under a reduced pressure of 10 to 10000 Pa since oxidation of the semiconductor device is prevented.

[0027]

(Embodiment 1) In this embodiment,
A case where the vertical heat treatment apparatus of the present invention is used for crystallization of a semiconductor film to be a semiconductor layer (active layer) of a TFT will be described with reference to FIG.

First, a base film 11 made of a 200-nm-thick silicon oxynitride film and a 55-nm-thick amorphous semiconductor film (in this embodiment, an amorphous silicon A film 12 is formed. In this step, the base film and the amorphous silicon film may be formed continuously without being exposed to the atmosphere.

Next, an aqueous solution (aqueous nickel acetate solution) containing 10 ppm by weight of a metal element (nickel in this embodiment) is applied by spin coating to form a metal element-containing layer 13.
Is formed on the amorphous silicon film 12. Metal elements usable here include palladium (Pd), tin (Sn), lead (Pb), cobalt (C
o), platinum (Pt), copper (Cu), and gold (Au).

In this embodiment, the method of adding nickel by the spin coating method has been described, but the metal element may be added by a method such as a vapor deposition method or a sputtering method. (FIG. 3
(A))

Next, the substrate on which the semiconductor film to which the metal element is added is formed is carried into a quartz boat by a transfer robot and stored therein. The transfer robot has a ceramic robot arm with a thickness of 10 mm, and conditional expression (4)
And the distance d between the substrates is 20 mm. At this time, d1 = d
2 = 5 mm. The substrates are stored in a quartz boat capable of storing 60 substrates. When the substrates are sequentially loaded from below the quartz boat, t3 = 10 mm and d = 20 mm.
There is a margin of 0mm and it can be carried in relatively easily. If the method of packing the substrates in order from the top when loading the substrates is adopted, the conditional expression of the distance d between the substrates becomes the expression (2), and t1 + t2 is about 15 mm.
Therefore, if d = 20 mm, Expression (2) is not satisfied, and transport becomes difficult.

After storing the substrates in the quartz boat 203, the quartz boat 203 is moved upward by the boat elevator unit 205, and the substrates are stored in the quartz tube 201. In order to prevent oxidation of the semiconductor film due to heat treatment, the inside of the quartz tube 201 is set to a nitrogen atmosphere, and heating is started. For example,
First, a heat treatment is performed at 400 to 500 ° C. for about 1 hour to desorb hydrogen contained in the film.
The amorphous silicon is crystallized by performing heat treatment at 650 ° C. for 4 to 12 hours to obtain the crystalline silicon film 14. ((B) of FIG. 3) (Embodiment 2)

In the second embodiment, a method for removing a metal element from the crystalline silicon film manufactured in the first embodiment will be described.
This method is generally called a gettering step.

An insulating film 16 having a thickness of 200 nm is formed on the crystalline silicon film 14 as a mask made of a silicon oxide film, and an opening 15 is formed. A step of adding an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) to the crystalline silicon film 14 exposed from the opening 15 is performed. By this step, 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm
A gettering region 17 containing phosphorus at a concentration of ³ is formed. The method of adding phosphorus may be, for example, a doping method.

The crystalline silicon film to which phosphorus has been added is carried into the vertical heat treatment apparatus, and stored in a quartz tube. The loading method may be the method described in the first embodiment. Next, the inside of the quartz tube was evacuated with a rotary pump and a mechanical booster pump to obtain high purity (C contained in nitrogen).
(The concentration of H ₄ , CO, CO ₂ , H ₂ , H ₂ O, and O ₂ is 1 ppb or less) at a flow rate of 5 l / min to maintain the pressure in the quartz tube at 13.3 to 26.7 Pa. , Oxygen concentration is 5pp
A nitrogen atmosphere of m or less (2 ppm or less in this embodiment) is created. 450 to 650 ° C., 4 to 24 in this nitrogen atmosphere.
Perform the heat treatment process for a long time. In this embodiment, the atmosphere is a nitrogen atmosphere. However, if the oxygen concentration can be reduced to 5 ppm or less, the atmosphere may be a gas containing no oxygen, for example, an inert gas such as helium (He), neon (Ne), or argon (Ar). Good. Further, a gas such as hydrogen (H) which does not deposit by thermal decomposition or react with the semiconductor film.
₂ ) You can.

By this heat treatment step, nickel in the crystalline silicon film 14 moves in the direction of the arrow, and is captured in the gettering region 17 by the gettering action of phosphorus. That is, nickel is removed from the crystalline silicon film 14, and the concentration of nickel contained in the crystalline silicon film 14 is 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ at.
oms / cm ³ or less.

The crystalline silicon film 14 formed as described above uses a metal element that promotes crystallization, and after the crystallization, the metal element is removed by the gettering action of phosphorus. Since the concentration of the metal element remaining in the crystalline silicon film 14 is reduced, a good crystalline silicon film can be obtained.

(Embodiment 1) In this embodiment, an example of a transfer machine using the substrate transfer method of the present invention will be described. An embodiment will be described with reference to FIG.

In FIG. 4, a robot arm 207 for transferring a substrate is located at the center. The direction can be changed by the rotation mechanism, and expansion and contraction are also possible. First, the robot arm 207 carries the substrate 1 from the uppermost substrate 1 of the cassette 208 in which the substrates are stored to the lowermost position 10 of the cassette 209 in which the substrates are not stored. Next, in the cassette 208, the substrate 2 that has become the uppermost substrate due to the transport of the substrate 1
To the position 11 of the cassette 209 in which no substrates are stored.
Transfer to By repeating these series of operations, all the substrates stored in the cassette 208 can be moved to the cassette 209. By following these rules,
The positional relationship between the substrate and the robot arm when loading and unloading the substrate is the same as in FIG. 1 (c). Therefore, since the equation for limiting the distance between the substrates is (4), the condition for the distance d between the substrates is relaxed, and the distance between the substrates can be further reduced.

(Embodiment 2) In this embodiment, an example in which a relatively narrow distance between substrates produces industrially good results will be described. Specifically, in the heat treatment process of the manufacturing process of the semiconductor device, the value of the contact resistance between the gate electrode and the wiring of the semiconductor device is determined when the distance between the substrates of the vertical batch processing apparatus performing the heat treatment is small and wide. In contrast, an example in which the resistance value is lower in a narrow case is shown.

In this embodiment, the step of fabricating a TFT is omitted, and the difference in contact chain resistance when a laminated film of TaN and W is used as a gate electrode and Al-Nd is used for a gate wiring is experimentally examined. Here is an example.

First, a film of TaN was formed to a thickness of 30 nm on one side of a quartz substrate, and a film of W was continuously formed to a thickness of 370 nm. Before film formation, the quartz substrate was sufficiently washed. In particular,
Washing with pure water and washing with megasonic were performed.

Thereafter, for the purpose of forming a contact chain, the laminated film of TaN and W was patterned and further subjected to thermal annealing. In the manufacturing process of the semiconductor device, the thermal annealing is performed, for example, in a process of activating a dopant doped in an active layer, a process of gettering impurities in a channel region of a TFT, and the like. Generally, a vertical batch processing apparatus is often used for such a thermal annealing step. The appropriate temperature for the thermal annealing in the activation step and the gettering step was about 450 to 600 degrees.

FIG. 5 shows an overview of the vertical heat treatment apparatus used in this experiment. The experimental substrate is housed in a quartz boat 211 surrounded by a quartz tube 210. In order to carry out experiments by changing the distance between adjacent substrates during the heat treatment, a cleaned quartz substrate is arranged at addresses 1 to 20, 23 to 60 in FIG. 5, and TaN is applied to addresses 21 and 22, 68 and 76. The substrate on which the laminated film of W was formed was arranged. As a result, the substrates disposed at addresses 21 and 22 are used for an experiment in the case where the substrate interval is small, and the substrates disposed at addresses 68 and 76 are:
It was used in experiments where the substrate spacing was wide. Address 21 and 2
The distance between the substrates of No. 2 was 5 mm, and the distance between the substrates of addresses 68 and 76 was 50 mm. In this embodiment, thermal annealing was performed for 4 hours under a nitrogen atmosphere at 600 degrees and atmospheric pressure. When the inside of the quartz tube was replaced with nitrogen, nitrogen was introduced into the quartz tube 210 from the gas supply pipe 212 while the inside of the quartz tube 210 was evacuated by the vacuum pump 220 via the valve 219. During the heat treatment, nitrogen was flowed at 5000 cm ³ per minute from the gas supply pipe 212. At this time, the oxygen concentration in the atmosphere inside the quartz tube was about 15 ppm.

Thereafter, a film of Al-Nd was formed, and a contact chain was formed by patterning. The number of stages of the contact chain was 50. FIG. 6 shows the result of measuring the contact chain resistance. The contact chain resistance of the substrate arranged at the address 21 has a very small variation around several tens Ω, whereas
The contact chain resistance of the substrate located at the address 68 varied widely in the range from several tens of Ω to nearly 100 Ω. From this result, it can be said that the shorter the distance between the substrates during the heat treatment, the more the variation in the contact resistance can be suppressed. That is, this experiment showed that shortening the distance between the substrates also leads to improvement in the characteristics of the semiconductor device. It is speculated that the cause of such a result may be the effect of oxidation of W. This phenomenon can be explained by considering that the reduction in the distance between the substrates made the efficiency of oxidation of W inferior and the deterioration of characteristics suppressed. In order to further suppress oxidation, heat treatment under reduced pressure may be performed. Thereby, the oxygen concentration decreases. The atmosphere during the heat treatment is preferably a nitrogen atmosphere because oxidation can be further prevented. The pressure is 1
About 0 to 10000 Pa is appropriate. The pressure range is
The substrate can be efficiently heated without using radiation, and is in a range that is effective for preventing oxidation of the semiconductor device.

(Embodiment 3) In this embodiment, the shape of the robot arm and the projection 1 supporting the substrate described with reference to FIG.
An example in which the distance between the substrates is further reduced by changing the shape of the substrate 05 will be described. The robot arm shown in this embodiment is
This allows the substrate to be transported with a margin, and also does not easily damage the substrate.

This embodiment will be described with reference to FIGS. FIG. 8A is a view similar to FIG. 7 except that the shape of the robot arm 213 is different. Robot arm 2
13 has a curvature at a portion in contact with the substrate,
The curvature approximately matches the curvature of the substrate formed when the substrate 103 is held by the robot arm 213. This significantly increases the area of the portion where the robot arm 213 and the substrate 103 are in contact with each other, so that the probability of damaging the substrate is significantly reduced. FIG. 8B is an example in which the shape of the projection 105 supporting the substrate is changed. The lower part of the protrusion 214 is a surface that is inclined with respect to the horizontal direction, and the shape of this surface approximately matches the warpage of the substrate at the end of the substrate 103 when the robot arm 213 holds the substrate 103. Thus, when the substrate 103 is stored in the quartz boat 104, the probability of contact between the substrate 103 and the protrusion 214 can be reduced. Therefore, the design allows more time,
The distance between the substrates can be further reduced.

FIG. 8C shows an example in which the upper part of the projection is inclined with respect to the horizontal plane. When the protrusion 215 holds the substrate 103, the contact area between the substrate 103 and the protrusion 215 is significantly increased, so that the substrate 103 is not easily damaged. FIG. 8D shows an example in which both the upper and lower portions of the projection are inclined with respect to the horizontal plane. Due to these inclinations, the projection 214 shown in FIG. 8B and the projection 214 shown in FIG.
The characteristics of both of the protrusions 215 shown in FIG.

FIG. 9A shows an example in which the lower part of the robot arm 217 has a curvature. Accordingly, the distance d2 between the substrate 103 located below the robot arm 217 and the robot arm 217 can be further reduced. FIGS. 9B to 9D are examples in which the shapes of the protrusions are modified similarly to FIGS. 8B to 8D. These effects are similar to those of FIG. FIG. 10A shows the robot arm 21.
This is an example in which the upper and lower portions of 8 have curvature. This has an effect obtained by adding the effects of the robot arm 213 and the robot arm 217. 10 (b) to 10 (d) correspond to FIG.
This is an example in which the shape of the projection is modified similarly to (b) to (d). These effects are similar to those of FIG. Embodiment 4 In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 300 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 300, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, SiH ₄ , N 2
The silicon oxynitride film 301a formed by using H ₃ and N ₂ O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 10 nm).
0 nm). In this embodiment, a 50 nm-thick silicon oxynitride film 301a (composition ratio: Si = 32%, O = 27%,
N = 24%, H = 17%). Next, as a second layer of the base film 301, a plasma CVD
A silicon oxynitride film 301b formed by using iH ₄ and N ₂ O as a reaction gas has a thickness of 50 to 200 nm (preferably 100 nm).
(About 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 301b (composition ratio Si =
32%, O = 59%, N = 7%, H = 2%).

Next, a semiconductor film 302 is formed on the base film. As the semiconductor film 302, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or a silicon germanium (SiGe) alloy. Subsequently, the crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a metal such as nickel) is patterned into a desired shape. Formed. The semiconductor layers 402 to 406 are formed. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method, a solution containing nickel is held on the amorphous silicon film. Dehydrogenation (500
After heating at 550 ° C. for 1 hour), a crystalline silicon film was formed. The dehydrogenation and the heat treatment may be performed by a method using a vertical heat treatment apparatus which is a feature of the present invention. Hereinafter, there are several heat treatment steps, and any of these steps may be performed by a method using a vertical heat treatment apparatus which is a feature of the present invention. Also,
The method characterized by the present invention may be used in a transfer machine used for transferring a substrate. Then, semiconductor layers 402 to 406 were formed by patterning the crystalline silicon film using a photolithography method.

When a laser crystallization method is used for crystallization of a semiconductor film, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. When using these lasers,
It is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz.
And a laser energy density of 100 to 800 mJ / cm ²
(Typically 200 to 700 mJ / cm ² ). Also, YA
When a G laser is used, its second harmonic is used to make the pulse oscillation frequency 1 to 300 Hz, and the laser energy density is 300 to 1000 mJ / cm ² (typically 350 to 80 mJ / cm ² ).
0 mJ / cm ² ). And width 100-1000μ
A laser beam condensed linearly at m, for example, 400 μm may be irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time may be set to 50 to 98%.

After forming the semiconductor layers 402 to 406, T
A small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of FT.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured is thereafter
Good characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Next, as shown in FIG. 11B, a first conductive film 408 having a thickness of 20 to 100 nm and a second conductive film 4 having a thickness of 100 to 400 nm are formed on the gate insulating film 407.
09 is laminated. In this embodiment, a first conductive film 408 made of a TaN film having a thickness of 30 nm and a
A second conductive film 409 made of a W film was formed by lamination.
The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 408 is used.
Is TaN and the second conductive film 409 is W, but there is no particular limitation, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. AgP
A dCu alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; Are combined with a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. Alternatively, a combination of the second conductive film and the Cu film may be used.

Next, resist masks 410 to 415 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed.
The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method is used, and C is used as an etching gas.
Using F ₄ , Cl ₂ and O ₂ , each gas flow ratio was 2
At 5/25/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

Thereafter, a mask 410 made of resist is formed.
The second etching condition was changed without removing 415, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In this manner, the first shape conductive layers 417 to 422 (the first conductive layers 417a to 422a and the second conductive layers 417b to 417b) formed of the first conductive layer and the second conductive layer by the first etching process.
2b) is formed. 416 is a gate insulating film,
The region not covered by the conductive layers 417 to 422 having the
A region that is etched and thinned by about 50 nm is formed.

Then, a first doping process is performed without removing the resist mask to add an n-type impurity element to the semiconductor layer. (FIG. 12A) The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 1.
0 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 60 to 10
The operation is performed at 0 keV. In this embodiment, the dose is 1.5
X 10 ¹⁵ / cm ² , and the acceleration voltage was set to 80 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 417 to 421 serve as a mask for the impurity element imparting n-type, and the first high-concentration impurity regions 30 are self-aligned.
6 to 310 are formed. First high concentration impurity region 30
To 6 to 310, an impurity element imparting n-type is added in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Next, a second etching process is performed without removing the resist mask. Here, the W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as} an etching gas. At this time, second conductive layers 428b to 433b are formed by a second etching process. on the other hand,
The first conductive layers 417a to 422a are hardly etched to form second shape conductive layers 428 to 433.

Next, as shown in FIG. 12B, a second doping process is performed without removing the resist mask. In this case, the dose is lower than that of the first doping process, and an n-type impurity element is introduced at a high acceleration voltage of 70 to 120 keV. In this embodiment, the dose is set to 1.5 × 10 ¹⁴ / cm ² and the acceleration voltage is set to 90 keV. The second doping process uses the second shape conductive layers 428 to 433 as a mask,
The impurity element is also introduced into the semiconductor layer below the second conductive layers 428b to 433b, and the second high concentration impurity regions 423a to 427a and the low concentration impurity regions 42 are newly added.
3b to 427b are formed.

Next, after removing the mask made of resist, masks 434a and 434a made of resist are newly added.
34b is formed, and a third etching process is performed as shown in FIG. SF ₆ and Cl ₂ were used as etching gases, and the gas flow ratio was 50/10 (scc
m) and a pressure of 1.3 Pa and 500
An RF (13.56 MHz) power of W is applied to generate plasma, and an etching process is performed for about 30 seconds. 10 W RF (13.56 MH) on the substrate side (data stage)
z) Turn on the power and apply a substantially non-self bias voltage. Thus, the p-channel type TFT and the TFT (pixel T
The TaN film (FT) is etched to form third shape conductive layers 435 to 438.

Next, after removing the resist mask, the gate insulating film 416 is selectively removed using the second shape conductive layers 428 and 430 and the second shape conductive layers 435 to 438 as masks. Insulating layers 439-44
4 is formed. (FIG. 13A)

Next, a new mask 4 made of resist is used.
45a to 445c are formed and a third doping process is performed. By the third doping treatment, the impurity region 4 in which the impurity element imparting the conductivity type opposite to the one conductivity type is added to the semiconductor layer serving as the active layer of the p-channel TFT.
46 and 447 are formed. Second conductive layers 435a, 43
8a is used as a mask for the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 446 and 447 are formed by an ion doping method using diborane (B ₂ H ₆ ). (FIG. 13B) In the third doping process, the semiconductor layers forming the n-channel TFT are covered with masks 445a to 445c made of resist. Phosphorus is added at different concentrations to the impurity regions 446 and 447 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is set to 2 × in each of the regions. 10 ^{20 to} 2 ×
By performing the doping treatment to have a density of 10 ²¹ / cm ³ , no problem arises because the p-type TFT functions as a source region and a drain region. In this embodiment, since a part of the semiconductor layer serving as the active layer of the p-channel TFT is exposed, there is an advantage that an impurity element (boron) can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, a mask 445a made of resist is used.
To 445c are removed to form a first interlayer insulating film 461. As the first interlayer insulating film 461, plasma C
Using a VD method or a sputtering method, a thickness of 100 to 200
The insulating film containing silicon is formed as nm. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Of course, the first interlayer insulating film 461
Is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 13C, heat treatment is performed to recover the crystallinity of the semiconductor layers, activate the impurity elements added to the respective semiconductor layers, and perform source drain gettering. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As a thermal annealing method, an oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere of 1 ppm or less, preferably 0.1 ppm or less,
Typically, the heat treatment may be performed at 500 to 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, nickel used as a metal during crystallization is doped with impurity regions 423a, 425a, and 426 containing high-concentration phosphorus.
a, 446a and 447a are crystallized. Therefore, the metal element is gettered in the impurity region, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Heat treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, an active layer is formed after an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to carry out a chemical treatment.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 462 made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461. In this embodiment, the film thickness is 1.6 μm
Was formed, but the viscosity was 10 to 1000
cp, preferably 40 to 200 cp, and those having irregularities on the surface were used.

In this embodiment, in order to prevent specular reflection, irregularities are formed on the surface of the pixel electrode by forming a second interlayer insulating film having irregularities on the surface. In addition, a projection may be formed in a region below the pixel electrode in order to obtain light scattering by providing unevenness on the surface of the pixel electrode. In that case, the projection can be formed using the same photomask as that for forming the TFT, so that the projection can be formed without increasing the number of steps. Note that the protrusions may be appropriately provided on the substrate in the pixel portion region other than the wiring and the TFT portion. Thus, irregularities are formed on the surface of the pixel electrode along irregularities formed on the surface of the insulating film covering the convex portions.

Further, a film whose surface is flattened may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, the surface is made uneven by adding a process such as a known sand blasting method or an etching method to prevent specular reflection and increase whiteness by scattering reflected light. Is preferred.

In the drive circuit 506, wirings 463 to 467 electrically connected to the respective impurity regions, respectively.
To form Note that these wirings are made of a 50 nm thick T
A laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning.

In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 14) The connection electrode 468 forms an electrical connection between the source wiring (the lamination of 443b and 449) and the pixel TFT. The gate wiring 469 is connected to the pixel T
An electrical connection is formed with the gate electrode of the FT. Also,
The pixel electrode 470 is electrically connected to the drain region 442 of the pixel TFT, and is also electrically connected to the semiconductor layer 458 functioning as one electrode forming a storage capacitor. In addition, as the pixel electrode 470, a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a stacked film thereof, is preferably used.

As described above, the n-channel TFT 50
1 and a CMOS circuit comprising a p-channel TFT 502;
And driving circuit 506 having n-channel TFT 503
And a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 can be formed over the same substrate. Thus, an active matrix substrate is completed.

The n-channel TFT 50 of the driving circuit 506
1 includes a channel formation region 423c, a low-concentration impurity region 423b (a GOLD region) overlapping with a first conductive layer 428a which forms part of a gate electrode, and a high-concentration impurity region 423a functioning as a source or drain region. ing. A p-channel TFT 5 connected to the n-channel TFT 501 via an electrode 466 to form a CMOS circuit
02 has a channel formation region 446d, impurity regions 446b and 446c formed outside the gate electrode, and a high-concentration impurity region 446a functioning as a source region or a drain region. Also, an n-channel TFT 50
3 includes a channel formation region 425c, a low-concentration impurity region 425b (GOLD region) overlapping with the first conductive layer 430a which forms part of the gate electrode, and a high-concentration impurity region 425a functioning as a source or drain region. are doing.

The pixel TFT 504 in the pixel portion has a channel formation region 426c, a low concentration impurity region 426b (LDD region) formed outside the gate electrode, and a high concentration impurity region 426a functioning as a source or drain region.
have. The semiconductor layers 447a and 447b functioning as one electrode of the storage capacitor 505 are each doped with an impurity element imparting p-type. The storage capacitor 505 includes an electrode (438) using the insulating film 444 as a dielectric.
a and 438b), and the semiconductor layers 447a to 447c.
And formed.

In the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

FIG. 15 is a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. Note that the same reference numerals are used for portions corresponding to FIGS. A chain line AA ′ in FIG. 14 is a chain line AA ′ in FIG.
It corresponds to the cross-sectional view cut by. The dashed line BB ′ in FIG. 14 corresponds to the cross-sectional view cut along the dashed line BB ′ in FIG.

[Embodiment 5] In this embodiment, a process for fabricating a reflection type liquid crystal display device from the active matrix substrate fabricated in Embodiment 4 will be described below. FIG. 16 is used for the description.

First, according to the fourth embodiment, after obtaining the active matrix substrate in the state shown in FIG. 14, an alignment film 567 is formed on at least the pixel electrode 470 on the active matrix substrate shown in FIG. Note that in this embodiment, before forming the alignment film 567, a columnar spacer 572 for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 569 is prepared. Next, the coloring layers 570 and 571 and the planarizing film 573 are formed over the counter substrate 569. The red coloring layer 570 and the blue coloring layer 572 are overlapped to form a light shielding portion. Alternatively, the light-blocking portion may be formed by partially overlapping the red coloring layer and the green coloring layer.

In this embodiment, the substrate shown in the fourth embodiment is used. Therefore, FIG. 1 shows a top view of the pixel portion of the fourth embodiment.
5, at least the gate wiring 469 and the pixel electrode 470
, The gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 need to be shielded from light. In this embodiment, the colored layers are arranged such that the light-shielding portion formed of the colored layers is overlapped at the positions where the light is to be shielded, and the opposing substrates are bonded to each other.

As described above, the number of steps can be reduced by shielding the gap between each pixel with the light-shielding portion composed of the colored layers without forming a light-shielding layer such as a black mask.

Next, a counter electrode 576 made of a transparent conductive film was formed on at least the pixel portion on the flattening film 573, an alignment film 574 was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 568.
Paste in. A filler is mixed in the sealant 568, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 575 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. Thus, the reflection type liquid crystal display device shown in FIG. 16 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
PC was pasted.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

This embodiment can be freely combined with Embodiments 1 to 4.

[Embodiment 6] In this embodiment, an example in which a light emitting device is manufactured using the present invention will be described. A light-emitting device is a device in which a layer (a light-emitting element) containing an organic compound from which luminescence generated by application of an electric field is obtained is used as a light source. Light emission in an organic compound includes light emission when returning from a singlet excited state to a ground state (fluorescence) and light emission when returning from a triplet excited state to a ground state (phosphorescence). In addition,
FIG. 17 is a sectional view of the light emitting device of the present embodiment.

In FIG. 17, a switching TFT 603 provided on a substrate 700 is an n-channel type TFT shown in FIG.
It is formed using FT503. Therefore, for the description of the structure, the description of the n-channel TFT 503 may be referred to.

Although the present embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The driving circuit provided on the substrate 700 is shown in FIG.
7 CMOS circuits. Therefore, the description of the structure is made of the n-channel TFT 501 and the p-channel TFT
Reference may be made to the description of 502. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The wirings 701 and 703 function as a source wiring of the CMOS circuit, and the wiring 702 functions as a drain wiring.
The wiring 704 is connected to the source wiring 708 and the switching T
The wiring 705 functions as a wiring for electrically connecting the source region of the FT to the source region.
It functions as a wiring for electrically connecting the drain region of the FT.

The current control TFT 604 corresponds to p
It is formed using a channel type TFT 502. Therefore,
For the description of the structure, the description of the p-channel TFT 502 can be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line), and 707 is an electrode which is electrically connected to the pixel electrode 710 by being superposed on the pixel electrode 710 of the current control TFT. is there.

Reference numeral 710 denotes a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 710 has a flat interlayer insulating film 7 before forming the wiring.
11 is formed. In this embodiment, it is very important to flatten the steps due to the TFT using the flattening film 711 made of resin. Since a light-emitting layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, carbon particles or metal particles are added to the insulating film that is a material of the bank 712 to lower the resistivity and suppress generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and the metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

A light emitting layer 713 is formed on the pixel electrode 710. Although only one pixel is shown in FIG. 17, light-emitting layers corresponding to each color of R (red), G (green), and B (blue) are separately formed in this embodiment. In this embodiment, the low molecular weight organic light emitting material is formed by a vapor deposition method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a light emitting layer is formed on the copper phthalocyanine film.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic light emitting material that can be used as the light emitting layer, and it is not necessary to limit the present invention to this. A light-emitting layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer has been described, but a high molecular weight organic light emitting material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

When the cathode 714 is formed, the light emitting element 715 is completed. The light emitting element 71 here
Reference numeral 5 denotes a diode formed by the pixel electrode (anode) 710, the light emitting layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, in particular, a D film is preferably used.
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the light-emitting layer 713
Can be suppressed. Therefore, the problem that the light emitting layer 713 is oxidized during the subsequent sealing step can be prevented.

Furthermore, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, a light emitting device having a structure as shown in FIG. 17 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 without exposing to the atmosphere using a multi-chamber (or in-line) film forming apparatus. . Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

In this manner, the n-channel TFTs 601 and 602 are placed on the insulator 501 whose main body is a plastic substrate.
A switching TFT (n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed. The number of masks required in the manufacturing process up to this point is
Less than a typical active matrix light emitting device.

That is, the manufacturing process of the TFT is greatly simplified, and an improvement in yield and a reduction in manufacturing cost can be realized.

Further, as described with reference to FIG.
By providing an impurity region overlapping the gate electrode with an insulating film interposed therebetween, n is resistant to deterioration caused by the hot carrier effect.
A channel type TFT can be formed. for that reason,
A highly reliable light-emitting device can be realized.

In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are also provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, the light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the light emitting element will be described with reference to FIG. It should be noted that the reference numerals used in FIG.

FIG. 18A is a top view showing a state in which the light emitting element has been sealed, and FIG. 18B is a cross-sectional view of FIG. 18A taken along the line CC ′. 80 shown by dotted line
Reference numeral 1 denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material;
Denotes a first sealant, 903 denotes a second sealant, and a sealant 907 is provided inside the first sealant 902.

Reference numeral 904 denotes wiring for transmitting signals input to the source-side driving circuit 801 and the gate-side driving circuit 807, and a video signal or a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The light emitting device in this specification includes not only the light emitting device body but also an FPC
Alternatively, this also includes a state where the PWB is attached.

Next, the cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 14) in which T601 and p-channel TFT 602 are combined.

[0119] The pixel electrode 710 functions as an anode of the light emitting element. Further, banks 712 are provided at both ends of the pixel electrode 710.
Are formed, and a light-emitting layer 713 and a cathode 714 of a light-emitting element are formed over the pixel electrode 710.

The cathode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate driver circuit 807 are covered with the cathode 714 and the passivation film 567.

Further, a cover member 901 is attached by a first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the light emitting element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

[0122] The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (FRP) is used as the material of the plastic substrate 901a constituting the cover member 901.
iberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

Also, the cover material 90 is formed by using the sealing material 907.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

With the above structure, the light emitting element is sealed with the sealing material 90.
By encapsulating the light-emitting element in the light-emitting element 7, the light-emitting element can be completely shut off from the outside, and a substance such as moisture or oxygen, which promotes deterioration of the light-emitting layer due to oxidation, can be prevented from entering from the outside. Therefore, a highly reliable light emitting device can be obtained.

This embodiment can be freely combined with Embodiments 1 to 4.

[Embodiment 7] By applying the present invention, various electro-optical devices (active matrix type liquid crystal display device, active matrix type light emitting device, active matrix type EC display device) can be manufactured. That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head mounted display (goggle type display), a car navigation system, a car stereo, a personal computer, and a portable information terminal (mobile computer, mobile phone, electronic book, etc.). ). FIG. 19 shows an example of them.
FIG. 20 and FIG.

FIG. 19A shows a personal computer, which includes a main body 3001, an image input section 3002, and a display section 30.
03, a keyboard 3004 and the like. Display unit 3 of the present invention
003 can be applied.

FIG. 19B shows a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, and an image receiving portion 310.
6 and so on. The present invention can be applied to the display portion 3102.

FIG. 19C shows a mobile computer (mobile computer), which includes a main body 3201, a camera section 3202, an image receiving section 3203, operation switches 3204, a display section 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 19D shows a goggle type display, which comprises a main body 3301, a display section 3302, and an arm section 330.
3 and so on. The present invention can be applied to the display portion 3302.

FIG. 19E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, and a speaker portion 340.
3, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3402.

FIG. 19F shows a digital camera, which includes a main body 3501, a display section 3502, an eyepiece section 3503, operation switches 3504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 3502.

FIG. 20A shows a front type projector, which includes a projection device 3601, a screen 3602, and the like. The present invention can be applied to the liquid crystal display device 3808 forming a part of the projection device 3601 and other driving circuits.

FIG. 20B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3, including a screen 3704 and the like. The present invention provides a projection device 3
The present invention can be applied to a liquid crystal display device 3808 which constitutes a part of the LCD 702 and other driving circuits.

FIG. 20C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 20A and 20B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 20D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 20C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 20D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 20, a case in which a transmissive electro-optical device is used is shown, and an application example in a reflective electro-optical device and a light emitting device is not shown.

FIG. 21A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 21B shows a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, and an antenna 4006.
And so on. The present invention can be applied to the display portions 4002 and 4003.

FIG. 21C shows a display, which includes a main body 4101, a support 4102, a display portion 4103, and the like.
The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 6.

[0143]

According to the present invention, the number of substrates that can be accommodated per unit volume of the vertical heat treatment apparatus is increased.
Increase productivity. In particular, in a manufacturing process of a semiconductor device, many steps require a high temperature, and the present invention contributes to significant cost reduction. Further, the present invention leads to improvement of the characteristics of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a side view showing an embodiment of the present invention.

FIG. 2 is a side view showing a vertical batch processing apparatus.

FIG. 3 is a side view showing an embodiment of the present invention.

FIG. 4 is a side view showing an embodiment of the present invention.

FIG. 5 is a side view showing an embodiment of the present invention.

FIG. 6 is a graph showing the effect of the present invention.

FIG. 7 is a side view showing one embodiment of the present invention.

FIG. 8 is a side view showing an embodiment of the present invention.

FIG. 9 is a side view showing an embodiment of the present invention.

FIG. 10 is a side view showing an example of the embodiment of the present invention.

FIG. 11 is a side view illustrating an example of a manufacturing process of a semiconductor device.

FIG. 12 is a side view illustrating an example of a manufacturing process of a semiconductor device.

FIG. 13 is a side view illustrating an example of a manufacturing process of a semiconductor device.

FIG. 14 is a side view illustrating an example of a manufacturing process of a semiconductor device.

FIG. 15 is a top view illustrating an example of a manufacturing process of a semiconductor device.

FIG. 16 is a side view illustrating an example of a manufacturing process of a semiconductor device.

FIG. 17 is a side view illustrating an example of a structure of a light-emitting device.

18A and 18B are a top view and a side view illustrating an example of a structure of a light-emitting device.

FIG. 19 illustrates an example of a semiconductor device.

FIG. 20 illustrates an example of a semiconductor device.

FIG. 21 illustrates an example of a semiconductor device.

FIG. 22 is a diagram showing an example of an embodiment of the present invention.

[Explanation of symbols]

 101 Substrate 102 Robot arm 103 Substrate 104 Quartz boat 105 Projection 201 Quartz tube 202 Heater unit 203 Quartz boat 204 Quartz table 205 Boat elevator unit 206 High-pressure vessel 207 Robot arm 208 Cassette 209 Cassette 210 Quartz tube 211 Quartz boat 212 Gas supply pipe 213 Robot arm 214 Projection 215 Projection 216 Projection 217 Robot arm 218 Robot arm 219 Valve 220 Vacuum pump

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/20 H01L 21/20 21/285 21/285 S 21/324 21/324 S // C23C 16 / 44 C23C 16/44 FF term (reference) 2H088 FA17 HA01 HA06 4K030 BB05 CA06 DA09 GA02 GA12 JA03 KA04 LA18 4M104 AA09 BB01 BB02 BB04 BB08 BB13 BB14 BB16 BB17 BB18 BB30 BB32 BB40 5 FA02 FA07 FA11 GA05 GA32 GA47 GA48 GA49 HA65 NA04 PA13 PA18 PA30 5F052 AA02 AA13 BA07 BB02 BB07 CA10 DA01 DA02 DA03 DB02 DB03 DB07 EA15 EA16 FA06 JA01 JA04

Claims (23)

[Claims] 1. A method for manufacturing a semiconductor device, comprising the steps of: transporting a plurality of substrates to a cassette by a robot arm, adjoining the plurality of substrates at an interval d in a vertical direction, and heat-treating the plurality of substrates. Arm thickness t3
And the relationship between the warp t1 of the substrate generated when the substrate is held by the robot arm and the warp t2 generated in the substrate stored in the cassette is represented by a conditional expression t1 + t2 + d.
1 + d2>d> t3 + d1 + d2, where d1 is the distance between the robot arm and the substrate located above the robot arm when the substrate is carried in and out of the cassette; d2 is a distance between the robot arm and the substrate located below the robot arm when the substrate is carried in and out of the cassette, and the robot arm moves the plurality of substrates under the cassette. And a step of sequentially carrying out the plurality of substrates from the top of the cassette by the robot arm. 2. A semiconductor device comprising a step of transporting a plurality of substrates on which a semiconductor film is formed to a cassette by a robot arm, adjoining the plurality of substrates at an interval d in a vertical direction, and heat-treating the plurality of substrates. In the manufacturing method, the relationship between the thickness t3 of the robot arm, the warp t1 of the substrate generated when the substrate is held by the robot arm, and the warp t2 generated on the substrate stored in the cassette is defined as And t1 + t2 + d1 + d2>d> t3 + d1 + d2, where d1 is the robot arm and the substrate positioned above the robot arm when the substrate is carried in and out of the cassette. And d2 is the distance between the robot arm and the substrate located below the robot arm when the substrate is loaded into and unloaded from the cassette, and A method of manufacturing a semiconductor device, comprising: a step of sequentially loading a plurality of substrates from a lower side of the cassette; and a step of sequentially transporting the plurality of substrates from an upper side of the cassette by the robot arm. 3. The substrate according to claim 1, wherein the area of the substrate is 120,000 mm ² or more, and the thickness of the substrate is 0.3 to 1.
A method for manufacturing a semiconductor device, which is 1 mm. 4. A method for manufacturing a semiconductor device according to claim 1, wherein the size of one side of each of the substrates is at least 300 × 400 mm, and the thickness of the substrates is 0.3 to 1.1 mm. . 5. The substrate according to claim 1, wherein the area of the substrate is 120,000 mm ² or more, and the thickness of the substrate is 0.4 to 0.4 mm.
A method for manufacturing a semiconductor device, which is 8 mm. 6. A method of manufacturing a semiconductor device according to claim 1, wherein a size of one side of each of said substrates is 300 × 400 mm or more, and a thickness of said substrate is 0.4 to 0.8 mm. . 7. The method according to claim 1, wherein
A method for manufacturing a semiconductor device, wherein a curvature of an upper surface of the robot arm is convex toward the outside of the robot arm. 8. The method according to claim 1, wherein:
A method for manufacturing a semiconductor device, wherein a lower surface of the robot arm has a curvature that is convex toward the outside of the robot arm. 9. The method according to claim 1, wherein
A method of manufacturing a semiconductor device, wherein upper and lower surfaces of the robot arm have curvatures protruding outward from the robot arm. 10. The cassette according to claim 1, wherein the projection holding the substrate of the cassette holds the substrate on a surface inclined from a horizontal plane, and the inclined surface is located at a center of the substrate. A method for manufacturing a semiconductor device, characterized in that the height decreases toward the surface. 11. The cassette according to claim 1, wherein the surface of the cassette, which holds the substrate, which is located below the substrate holding surface, has a height toward the center of the substrate. A method for manufacturing a semiconductor device, which is an increasing surface. 12. The cassette according to claim 1, wherein the projection holding the substrate of the cassette holds the substrate on a surface 1 inclined from a horizontal plane, and the surface 1 is provided at the center of the substrate. A surface having a height decreasing toward the surface, and a surface 2 of the protrusion located below the surface 1 being a surface increasing in height toward the center of the substrate. Method. 13. A method for manufacturing a semiconductor device according to claim 2, wherein said heat treatment is an SPC process for a semiconductor thin film. 14. The method for manufacturing a semiconductor device according to claim 2, wherein the heat treatment is a step of gettering impurities in the semiconductor thin film. 15. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed under a reduced pressure of 10 to 10000 Pa. 16. A method for manufacturing a semiconductor device, comprising: transferring a plurality of substrates to a cassette by a robot arm, adjoining the plurality of substrates at an interval d in a vertical direction, and heat-treating the plurality of substrates. Arm thickness
The relationship between t3, the warp t1 of the substrate generated in a state where the substrate is held by the robot arm, and the warp t2 generated in the substrate stored in the cassette is represented by a conditional expression t1 + t2 +
d1 + d2>d> t3 + d1 + d2, where d1 is the distance between the robot arm and the substrate located above the robot arm when the substrate is carried in and out of the cassette; d2 is a distance between the robot arm and the substrate located below the robot arm when the substrate is loaded into and unloaded from the cassette;
A step of carrying in the plurality of substrates in order from the lower side of the cassette by the robot arm, and a step of carrying out the plurality of substrates in order from the upper side of the cassette by the robot arm. A method for manufacturing a semiconductor device, comprising: 17. A plurality of substrates on which semiconductor films have been formed are transported to a cassette by a robot arm, and are spaced vertically by a distance d.
A method of manufacturing a semiconductor device having a step of heat-treating the plurality of substrates by adjoining the plurality of substrates, wherein the thickness t3 of the robot arm and the substrate generated when the substrate is held by the robot arm The relationship between the warp t1 of the substrate and the warp t2 generated in the substrate housed in the cassette satisfies the following condition: t1 + t2 + d1 + d2>d> t3 + d1 + d2, and d1 is the cassette of the substrate. D2 is the distance between the robot arm and the substrate located above the robot arm when loading and unloading, and d2 is the distance between the robot arm and the robot arm when loading and unloading the substrate into and from the cassette. The distance between the substrate located on the side,
The heat treatment is performed under a reduced pressure of 10 to 10000 Pa, and the robot arm sequentially loads the plurality of substrates from below the cassette, and the robot arm transfers the plurality of substrates from above the cassette. And a step of sequentially carrying out the steps. 18. A method for manufacturing a semiconductor device, comprising the steps of: transporting a plurality of substrates to a cassette by a robot arm, adjoining the plurality of substrates at a vertical interval d, and heat-treating the plurality of substrates. Arm thickness
The relationship between t3, the warp t1 of the substrate generated in a state where the substrate is held by the robot arm, and the warp t2 generated in the substrate stored in the cassette is represented by a conditional expression t1 + t2 +
d1 + d2>d> t3 + d1 + d2, where d1 is the distance between the robot arm and the substrate located above the robot arm when the substrate is carried in and out of the cassette; d2 is the distance between the robot arm and the substrate located below the robot arm when the substrate is carried in and out of the cassette, and the area of the substrate is 12
0000 mm ² or more, the thickness of the substrate is 0.3 to 1.1 mm
Wherein the heat treatment is performed under a reduced pressure of 10 to 10000 Pa, and the robot arm sequentially loads the plurality of substrates from the lower side of the cassette; and the robot arm transfers the plurality of substrates to the cassette. A step of carrying out the semiconductor device sequentially from the upper side of the semiconductor device. 19. A plurality of substrates on which a semiconductor film has been formed are transferred to a cassette by a robot arm, and are vertically spaced at a distance d.
A method of manufacturing a semiconductor device having a step of heat-treating the plurality of substrates by adjoining the plurality of substrates, wherein the thickness t3 of the robot arm and the substrate generated when the substrate is held by the robot arm The relationship between the warp t1 of the substrate and the warp t2 generated in the substrate stored in the cassette satisfies the conditional expression t1 + t2 + d1 + d2>d> t3 + d1 + d2, and d1 is D2 is the distance between the robot arm and the substrate located above the robot arm when loading and unloading, and d2 is the distance between the robot arm and the robot arm when loading and unloading the substrate into and from the cassette. The distance between the substrate located on the side,
The area of the substrate is 120,000 mm ² or more, the thickness of the substrate is 0.3 to 1.1 mm, and the heat treatment is performed under a pressure of 10
Performed under a reduced pressure of 10000 Pa, a step of carrying in the plurality of substrates in order from the lower side of the cassette by the robot arm, and a step of carrying out the plurality of substrates in order from the top of the cassette by the robot arm. A method for manufacturing a semiconductor device, comprising: 20. A method for manufacturing a semiconductor device, comprising the steps of: transporting a plurality of substrates to a cassette by a robot arm, adjoining the plurality of substrates at a vertical interval d, and heat-treating the plurality of substrates. Arm thickness
The relationship between t3, the warp t1 of the substrate generated in a state where the substrate is held by the robot arm, and the warp t2 generated in the substrate stored in the cassette is represented by a conditional expression t1 + t2 +
d1 + d2>d> t3 + d1 + d2, where d1 is the distance between the robot arm and the substrate located above the robot arm when the substrate is carried in and out of the cassette; d2 is the distance between the robot arm and the substrate located below the robot arm when the substrate is carried in and out of the cassette, and the area of the substrate is 12
0000 mm ² or more, and the thickness of the substrate is 0.4 to 0.8 mm
Wherein the heat treatment is performed under a reduced pressure of 10 to 10000 Pa, and the robot arm sequentially loads the plurality of substrates from below the cassette, and the robot arm transfers the plurality of substrates to the cassette. A step of carrying out the semiconductor device sequentially from the upper side of the semiconductor device. 21. A plurality of substrates on which semiconductor films have been formed are transported to a cassette by a robot arm, and are vertically separated by a distance d.
A method of manufacturing a semiconductor device having a step of heat-treating the plurality of substrates by adjoining the plurality of substrates, wherein the thickness t3 of the robot arm and the substrate generated when the substrate is held by the robot arm The relationship between the warp t1 of the substrate and the warp t2 generated in the substrate housed in the cassette satisfies the following condition: t1 + t2 + d1 + d2>d> t3 + d1 + d2, and d1 is the cassette of the substrate. D2 is the distance between the robot arm and the substrate located above the robot arm when loading and unloading, and d2 is the distance between the robot arm and the robot arm when loading and unloading the substrate into and from the cassette. The distance between the substrate located on the side,
The area of the substrate is 120,000 mm ² or more, the thickness of the substrate is 0.4 to 0.8 mm, and the heat treatment is performed at a pressure of 10 mm.
Performed under a reduced pressure of 10000 Pa, a step of carrying in the plurality of substrates in order from the lower side of the cassette by the robot arm, and a step of carrying out the plurality of substrates in order from the top of the cassette by the robot arm. A method for manufacturing a semiconductor device, comprising: 22. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device or a light emitting device. 23. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a digital camera, a projector, a goggle type display,
Personal computers, DVD players, e-books,
Alternatively, a method for manufacturing a semiconductor device, which is a portable information terminal.