JP2002329368A - Error correction encoding method for disk medium, error correction encoding circuit, disk medium, error correction method, and error correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction encoding method which is compatible to conventional methods and is strong against burst error by reducing an influence of burst error accompanied with the rise of density in DVD development for the next generation. SOLUTION: An error correction encoding method for disk mediums is provided which interleaves two product codes in the order based on a prescribed interleave rule and sends them to record them in a disk medium. The error correction encoding method has a second interleave step where R/2 higher rows of each of S sector data of one of two product codes and R/2 following rows are substituted in the unit of rows and a third interleave step where two products codes are alternately sent in the unit of rows and sent data of every (R+1)th row are recorded in the disk medium as physical sector data in the sending order, and thus this method is strong against burst error and can record an address in recording data in the same manner as conventional methods.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding method and an error correction coding circuit for a disk medium (recording medium) such as a DVD, a disk medium (recording medium), an error correction method, and an error correction circuit.

[0002]

2. Description of the Related Art Conventionally, in an optical disk such as a CD which is a high-density and large-capacity recording medium, an R disk is used to correct an error caused by a defect of the medium or dust or scratch attached on a disk surface.
An error correction code such as an seed-Solomon code is used. Further, for example, a DVD which has realized a larger capacity and a higher density to enable digital recording of AV data
In this example, data is arranged in a matrix, and error correction coding is performed in two dimensions in a row direction and a column direction.
-Solomon encoded product code is used.

[0003] In the product code, generally, a code having a relatively low error correction capability is used for each code of a row and a column, but a high error correction capability is realized by encoding the code two-dimensionally. .

In the DVD, user data is arranged in a matrix of 172 bytes in the row direction and 192 bytes in the column direction, and a parity of 10 bytes is added in the row direction and a parity of 16 bytes is added in the column direction. As a result, 182 bytes x
208 bytes constitute one product code, which is recorded on the disk in the row direction. Since the encoding in the row and column directions has the added parity of 10 bytes and 16 bytes, respectively, the minimum distance of the code is 11 bytes.
And 17 respectively, and have a correction capability of 5 corrections and 8 corrections, respectively.

When the minimum distance is d, the number of corrections t
Generally satisfies the relationship d ≧ 2 × t + 1 (Equation 1).

Further, when an error position is known in advance when performing a correction process, erasure correction using so-called known error position information is possible. By performing erasure correction, the number of corrections can be increased up to twice. be able to.

In the case of a product code, this error position information can be easily obtained by detecting that the code in the row or column direction cannot be corrected. If an uncorrectable flag is assigned to the entire uncorrectable row and column, and if an uncorrectable flag is assigned to the corresponding row in the row-direction correction, the error will be corrected in the next column-direction code when the error is corrected. When the uncorrectable flag is added to the corresponding column by the correction of the above, when the error correction of the code in the next row direction, the added uncorrectable flag is directly used as the error position information,
That is, by using this as an erasure flag, the next column or row can be corrected by erasure correction.

Assuming that the number of erasure corrections is e, the relationship of d ≧ 2 × t + e + 1 (Equation 2) holds, and in the above-described DVD example, the row direction is
Since the minimum distance d = 11, when all the erasure corrections are performed, the correction capability of a maximum of 10 corrections (t = 0, e = 1
0), since the minimum distance d = 17 in the column direction, similarly, it has a correction capability of 16 corrections.

In a product code, a so-called repetitive correction, which repeatedly executes correction of a code in a row direction and a column direction, is effective. All errors are corrected by a single correction in a row direction or a column direction. Even if it is not possible, by repeating, it is often possible to gradually reduce the number of errors in the entire product code and finally correct all of them. , A highly reliable error correction is realized.

[0010]

As for data reading errors of a disk medium such as an optical disk, many errors occur due to defects in the medium or dust on the disk surface. At this time,
The error is generally a burst error, that is, continuous data often makes a continuous error. Furthermore, as the density has been further increased in recent years, the influence of dust and the like has become relatively larger, and the occurrence of a larger burst error has become a problem. For example, several μm attached on the disk surface
~ Several tens of μm of garbage, continuously from tens of bytes to 100
In some cases, a burst error as large as a byte was caused.

[0011] In the above-mentioned DVD, an HD-D which records an HD image from a conventional SD image as a next generation DVD is also used.
As VD development research progresses, reducing the effects of burst errors has become a major issue.

In view of the above-mentioned problems, the present invention is compatible with the conventional product code, that is, there is little change from the conventional method, and address information and the like included in the recording data can be recorded at the same level as the conventional one, and it is long. An object of the present invention is to provide an error correction coding method, an error correction coding circuit, an optical disk, an error correction method, and an error correction circuit for a disk medium that can be corrected with high reliability even when a burst error occurs. I do.

[0013]

According to the error correction encoding method for a disk medium of the present invention, user data is divided into a predetermined sector length, and ID information of the user data is added to the head of each divided user data. A sector data generating step of generating sector data of (R × C) bytes;
The 2 × S pieces of the sector data are alternately divided into two pieces in the order of the user data, and the two pieces are arranged in a matrix of (S × R) rows × C columns to form interleaved sector data (A) and interleaved sector data ( B) for generating interleave sector data, and P and P in the column direction to perform double error detection and correction coding on the interleaved sector data (A) and (B) in the row and column directions, respectively.
A product code composed of ((S × R) + PO) rows × (C + PI) columns by adding a PO parity of a PO row having a relationship of O = S and a PI parity of a PI column in the row direction. (A) and a product code generating step of generating a product code (B); and performing the product codes (A) and (B) by adding the PO parity of the PO row to the S sector data for each row. A first interleaving step of generating first interleaved data (A) and first interleaved data (B) by inserting the first interleaved data (A) and the first interleaved data (B). A second interleaving step of generating the second interleaved data (B) by replacing the / 2 rows and the succeeding R / 2 rows in row units, the first interleaved data (A) and the second interleaving data (B) are alternately transmitted in units of rows, and a third interleaving step of recording the transmitted data for each (R + 1) line as physical sector data on a disk medium in the order of transmission is provided.

The error correction encoding circuit of the present invention divides user data into predetermined sector lengths, adds ID information of the user data to the beginning of each divided user data, and (R × C) bytes. A sector data generating means for generating sector data; and 2.times.S pieces of the sector data are alternately divided into two in the order of the user data, and each is divided into (S.times.
R) interleaved sector data generating means for arranging interleaved sector data (A) and interleaved sector data (B) by arranging them in a matrix of rows × C columns, and interleaved sector data (A) and (B), respectively. In order to perform double error detection and correction encoding in the row and column directions, the PO parity of the PO row having the relationship of PO = S in the column direction and the PI parity of the PI column in the row direction are respectively added. ((S × R) + PO) rows × (C + P)
I) Product code generating means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B)
Are inserted into the S sector data one row at a time for each row of the PO parities to generate first interleaved data (A) and first interleaved data (B). Means, and the upper R / 2 of each of the S sector data of the first interleaved data (B)
A second interleaving means for generating second interleaved data (B) by replacing a row and a subsequent R / 2 row on a row-by-row basis; the first interleaved data (A) and the second interleaved data ( B) are alternately transmitted in units of rows, and a third interleaving means for recording the transmitted data for each (R + 1) row as physical sector data on a disk medium in the order of transmission is provided.

According to the error correction method of the present invention, two pieces of reproduction data read from a disk medium are stored in a memory every (C + PI) bytes in a matrix of (S × R + PO) rows × (C + PI) columns. And a third deinterleaving step for generating first interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Split,
For each of the divided S pieces, a top R / 2 row,
A second deinterleaving step of generating the first interleaved data (B) by replacing the succeeding R / 2 rows on a row-by-row basis, and the first interleaved data (A) and the first interleaved data (B) Is divided into S pieces, and each row is extracted one by one from each of the least significant rows and collected as PO parity, so that
A first deinterleaving step of generating two product codes of ((S × R) + PO) rows × (C + PI) columns;
An error correction step of performing error correction on the two product codes for each product code.

The error correction circuit of the present invention stores two pieces of reproduction data read from a disk medium in a memory in the form of a matrix of (S × R + PO) rows × (C + PI) columns every (C + PI) bytes. And third deinterleaving means for generating first interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Second deinterleaving for generating first interleaved data (B) by subdividing the upper R / 2 rows and subsequent R / 2 rows for each of the divided S pieces in units of rows And means for dividing each of the first interleaved data (A) and the first interleaved data (B) into S pieces, extracting one row at a time from each of the divided lowermost rows as PO parity By putting together, each ((S ×
(R) + PO) first deinterleaving means for generating two product codes of (rows) × (C + PI) columns, and error correcting means for performing error correction on the two product codes for each product code And characterized in that:

In the error correction encoding method for a disk medium according to the present invention, the user data is divided into a predetermined sector length, and an I-data of the user data is added to the head of each divided user data.
A sector data generating step of generating (R × C) bytes of sector data by adding D information; and 2 × S pieces of the sector data are alternately divided into two in the order of the user data;
An interleaved sector data generating step of arranging each in a matrix of (S × R) rows × C columns to generate interleaved sector data (A) and interleaved sector data (B); B), the PO parity of the PO row having the relationship of PO = S in the column direction and the P parity of the PI column in the row direction are used to perform double error detection and correction coding in the row and column directions, respectively.
Each I parity is added, and each ((S × R) +
PO) a product code generation step of generating a product code (A) and a product code (B) composed of rows × (C + PI) columns, and the product codes (A) and (B) are respectively A first interleaving step of inserting parity one row at a time into the S sector data for each row to generate first interleaved data (A) and first interleaved data (B); The data (B) is divided into S regions in which R rows of sector data and PO parity are composed of one row, and R / 2 rows are cyclically shifted row by row in the column direction for each of the divided areas. A second interleaving step of generating second interleaved data (B)
The first interleaved data (A) and the second interleaved data (B) are alternately transmitted in units of rows, and the data of each transmitted (R + 1) line is recorded on a disk medium as physical sector data in the order of transmission. 3 interleaving steps.

The error correction encoding circuit of the present invention divides user data into predetermined sector lengths, adds ID information of the user data to the beginning of each divided user data, and (R × C) bytes. A sector data generating means for generating sector data; and 2.times.S pieces of the sector data are alternately divided into two in the order of the user data, and each is divided into (S.times.
R) interleaved sector data generating means for arranging interleaved sector data (A) and interleaved sector data (B) by arranging them in a matrix of rows × C columns, and interleaved sector data (A) and (B), respectively. In order to perform double error detection and correction encoding in the row and column directions, the PO parity of the PO row having the relationship of PO = S in the column direction and the PI parity of the PI column in the row direction are respectively added. ((S × R) + PO) rows × (C + P)
I) Product code generating means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B)
Are inserted into the S sector data one row at a time for each row of the PO parities to generate first interleaved data (A) and first interleaved data (B). Means for dividing the first interleaved data (B) into S areas each having R rows of sector data and one PO parity, and dividing each of the divided areas into rows in the column direction. Second interleaving means for generating a second interleaved data (B) by cyclically shifting the data by R / 2 rows, and converting the first interleaved data (A) and the second interleaved data (B) in units of rows. And a third interleaving means for alternately transmitting the data for each (R + 1) row and recording the data as physical sector data on the disk medium in the transmission order.

According to the error correction method of the present invention, two sets of reproduction data read from a disk medium are stored in a memory in (C + PI) bytes for each (C + PI) rows × (C + PI) columns. And a third deinterleaving step for generating first interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Split,
A second deinterleaving step of generating a first interleave data (B) by performing a R / 2 row cyclic shift on a row-by-row basis in the column direction for each of the divided S pieces;
Each of the first interleaved data (A) and the first interleaved data (B) is divided into S, and one row is extracted from each of the divided lowermost rows, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving step of generating two product codes of (+ PO) rows × (C + PI) columns, and an error correcting step of performing an error correction on the two product codes for each product code. It is characterized by having.

The error correction circuit of the present invention stores two sets of reproduction data read from a disk medium in a memory in the form of (S × R + PO) rows × (C + PI) columns for each (C + PI) bytes. And third deinterleaving means for generating first interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Then, each of the divided S pieces is divided into R /
First interleaved data (B) after cyclically shifting two rows
, And each of the first interleaved data (A) and the first interleaved data (B) is divided into S pieces, and one row from the respective lowest row is divided. The first deinterleaving means for generating two product codes, each of which is ((S × R) + PO) rows × (C + PI) columns, An error correction means for performing error correction on each code for each product code is provided.

In the error correction encoding method for a disk medium according to the present invention, the user data is divided into a predetermined sector length, and the I data of the user data is added to the head of each divided user data.
A sector data generating step of generating (R × C) bytes of sector data by adding D information; and 2 × S pieces of the sector data are alternately divided into two in the order of the user data;
An interleaved sector data generating step of arranging each in a matrix of (S × R) rows × C columns to generate interleaved sector data (A) and interleaved sector data (B); B), the PO parity of the PO row having the relationship of PO = S in the column direction and the P parity of the PI column in the row direction are used to perform double error detection and correction coding in the row and column directions, respectively.
Each I parity is added, and each ((S × R) +
PO) a product code generation step of generating a product code (A) and a product code (B) composed of rows × (C + PI) columns, and the product codes (A) and (B) are respectively A first interleaving step of inserting parity one row at a time into the S sector data for each row to generate first interleaved data (A) and first interleaved data (B); A second interleaving step (B) for generating second interleaved data (B) by replacing the upper R / 2 rows and the succeeding R / 2 rows of each of the S sector data of data (B) in row units; And the first
Of the interleaved data (A) is divided into S areas each including R rows of sector data and one PO parity, and each PO parity row of each divided area is divided into R areas from above in each area. A second interleaving step (A) for generating second interleaved data (A) by inserting the second interleaved data (A) and the second interleaved data (B). A third interleaving step of alternately transmitting the data in units of rows and recording the data of each transmitted (R + 1) row as physical sector data on the disk medium in the order of transmission.

The error correction encoding circuit according to the present invention divides user data into predetermined sector lengths, adds ID information of the user data to the beginning of each divided user data, and (R × C) bytes. A sector data generating means for generating sector data; and 2.times.S pieces of the sector data are alternately divided into two in the order of the user data, and each is divided into (S.times.
R) interleaved sector data generating means for arranging interleaved sector data (A) and interleaved sector data (B) by arranging them in a matrix of rows × C columns, and interleaved sector data (A) and (B), respectively. In order to perform double error detection and correction encoding in the row and column directions, the PO parity of the PO row having the relationship of PO = S in the column direction and the PI parity of the PI column in the row direction are respectively added. ((S × R) + PO) rows × (C + P)
I) Product code generating means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B)
Are inserted into the S sector data one row at a time for each row of the PO parities to generate first interleaved data (A) and first interleaved data (B). Means, and the upper R / 2 of each of the S sector data of the first interleaved data (B)
A second interleaving means (B) for generating the second interleaved data (B) by replacing the rows and the lower R / 2 rows on a row-by-row basis;
A row is divided into S areas each having one row of sector data and PO parity, and each PO parity row of each divided area is inserted next to the R / 2 row from the top in each area. Second
A second interleaving means (A) for generating the interleaved data (A), and the second interleaved data (A) and the second interleaved data (B) are alternately transmitted in units of rows and transmitted ( (R + 1) third interleaving means for recording data of each row as physical sector data on a disk medium in the order of transmission.

According to the error correction method of the present invention, two pieces of reproduction data read from a disk medium are stored in a memory in a matrix of (S × R + PO) rows × (C + PI) columns every (C + PI) bytes. And a third deinterleaving step of generating second interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Split,
For each of the divided S pieces, a top R / 2 row,
A second deinterleaving step (B) for generating the first interleaved data (B) by replacing the succeeding R / 2 rows on a row-by-row basis, and (R + 1) rows of the second interleaved data (A). Is divided into S pieces, and the POs in the ((R / 2) +1) -th row from the top of each of the divided S pieces
A second deinterleaving step (A) for extracting parity and moving it to the lowermost end of each of the divided S areas to generate first interleaved data (A);
, Each of the interleaved data (A) and the first interleaved data (B) is divided into S pieces, and one row is extracted from each of the divided lowermost rows and collected as PO parity, so that (S × R) + P
O) A first deinterleaving step of generating two product codes of rows × (C + PI) columns, and an error correcting step of performing error correction on the two product codes for each product code It is characterized by having.

The error correction circuit of the present invention stores two pieces of reproduction data read from a disk medium in a memory in (C + PI) rows × (C + PI) columns each for (C + PI) bytes. And third deinterleaving means for generating second interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into S (R + 1) rows Second deinterleaving for generating first interleaved data (B) by subdividing the upper R / 2 rows and subsequent R / 2 rows for each of the divided S pieces in units of rows Means (B) and the second interleaved data (A) as (R
+1) Each row is divided into S rows, the PO parity of the ((R / 2) +1) -th row is extracted from each of the divided S rows, and moved to the lowermost end of each of the divided S areas Second deinterleaving means (A) for generating first interleaved data (A), and the first interleaved data (A) and the first interleaved data (B)
Is divided into S pieces, and one row is extracted one by one from each of the least significant rows and grouped as PO parity, so that each is ((S × R) + PO) rows × (C + P
I) first deinterleaving means for generating two product codes which are columns, and error correcting means for performing error correction on the two product codes for each product code. I do.

In the error correction encoding method for a disk medium according to the present invention, the user data is divided into a predetermined sector length, and the I-data of the user data is added to the head of each divided user data.
A sector data generating step of generating (R × C) bytes of sector data by adding D information; and 2 × S pieces of the sector data are alternately divided into two in the order of the user data;
An interleaved sector data generating step of arranging each in a matrix of (S × R) rows × C columns to generate interleaved sector data (A) and interleaved sector data (B); B), the PO parity of the PO row having the relationship of PO = S in the column direction and the P parity of the PI column in the row direction are used to perform double error detection and correction coding in the row and column directions, respectively.
Each I parity is added, and each ((S × R) +
PO) a product code generation step of generating a product code (A) and a product code (B) composed of rows × (C + PI) columns, and the product codes (A) and (B) are respectively Parity is calculated from the top of each of the S sector data ((R / R /
2) +1)) A first interleaving step of inserting first one row at a time to generate first interleaved data (A) and first interleaved data (B), and the first interleaved data (B) With the sector data of R row and P
O-parity is divided into S regions composed of one row,
A second interleaving step of generating a second interleaved data (B) by performing a cyclic shift of R / 2 rows on a row basis in a column direction for each divided area, and a first interleaved data (A); A third interleaving step of alternately transmitting the second interleaved data (B) in row units and recording the transmitted data for each (R + 1) row as physical sector data on a disk medium in the order of transmission. And

The error correction coding circuit of the present invention divides user data into predetermined sector lengths, adds ID information of the user data to the head of each divided user data, and (R × C) bytes. A sector data generating means for generating sector data; and 2.times.S pieces of the sector data are alternately divided into two in the order of the user data, and
R) interleaved sector data generating means for arranging interleaved sector data (A) and interleaved sector data (B) by arranging them in a matrix of rows × C columns, and interleaved sector data (A) and (B), respectively. In order to perform double error detection and correction coding in the row and column directions, the PO parity of the PO row having the relationship of PO = S in the column direction and the PI parity of the PI column in the row direction are added. ((S × R) + PO) rows × (C + P)
I) Product code generating means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B)
From the top of each of the S sector data in the ((R / 2) +1)) row from the top of the PO row.
First interleaving means for generating first interleaved data (A) and first interleaved data (B) by inserting each line, and the first interleaved data (B)
Is divided into S areas in which R rows of sector data and PO parities are composed of one row, and for each of the divided areas, R / 2 rows are cyclically shifted row by row in the column direction to form a second area. Second interleaving means for generating interleaved data (B); and alternately transmitting the first interleaved data (A) and the second interleaved data (B) in row units.
And a third interleaving means for recording the transmitted data for each (R + 1) row as physical sector data in the transmission order on a disk medium.

According to the error correction method of the present invention, two pieces of reproduction data read from a disk medium are stored in a memory in the form of (S × R + PO) rows × (C + PI) columns for each (C + PI) bytes. And a third deinterleaving step for generating first interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Split,
A second deinterleaving step of generating a first interleave data (B) by performing a R / 2 row cyclic shift on a row-by-row basis in the column direction for each of the divided S pieces;
Each of the first interleaved data (A) and the first interleaved data (B) is divided into S pieces, and from the top of each of the divided respective ((R / 2) +1)) rows Each row is extracted and grouped as PO parity, so that each row is ((S × R) + PO) rows × (C + P
I) a first deinterleaving step of generating two product codes that are columns, and an error correcting step of performing error correction on the two product codes for each product code. I do.

The error correction circuit of the present invention stores two pieces of reproduction data read from the disk medium in a memory in the form of (S × R + PO) rows × (C + PI) columns for each (C + PI) bytes. And third deinterleaving means for generating first interleaved data (A) and second interleaved data (B), and dividing the second interleaved data (B) into (R + 1) rows by S Then, each of the divided S pieces is divided into R /
First interleaved data (B) after cyclically shifting two rows
, And each of the first interleaved data (A) and the first interleaved data (B) is divided into S pieces, and ((R / 2) +1)) By extracting rows one by one from the row and combining them as PO parity, two product codes, each of which is ((S × R) + PO) rows × (C + PI) columns, are generated. A first deinterleaving means and an error correcting means for performing error correction on the two product codes for each product code. The disk medium of the present invention is characterized in that physical sector data is recorded by the above-described disk medium error correction coding method or disk medium error correction coding circuit.
An error correction code can be obtained based on the physical sector data.

[0029]

Embodiments of the present invention will be described below with reference to the accompanying drawings. The present invention is applicable to a recording medium in which a reading error may occur when reading digital data, for example, a disk medium such as a DVD. In the following description, the recording medium will be described as a disk medium.

(Sector Data Generation Step) FIG. 1 is a diagram showing the configuration of sector data in the error correction encoding method for a recording medium according to the first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes user data;
Reference numeral 102 denotes ID information of the user data 101. Data or MPEG sent from host computer
The compressed data of user data 1
01, and is divided every 2 Kbytes. Further, at the head of each user data 101, ID information 102 including address information such as a logical sector address and a physical sector address of a sector in which each user data is recorded is added. The ID information 102 includes normal address information and a CRC (cyclic redundancy check) code for error detection, and has a length of about 6 bytes.
Sector data 103 is composed of user data 101 and ID information 102. In FIG. 1, the sector data 103 is composed of 12 bytes × 172 bytes = 2064 bytes. As will be described later, the sector data 103 is a logical sector data unit, and does not necessarily have to match data recorded in a physical sector as a result of processing such as interleaving. Further, data recorded in a physical sector is further recorded including parity and the like subjected to error correction coding. The user data 101 may include not only data transmitted from the host computer or MPEG compressed data, but also control data for copyright protection and the like.

(Interleaved Sector Data Generation Step) FIG. 2 is a diagram showing the configuration of the interleaved sector data (A) and (B) of the embodiment.

In FIG. 2, 201 is sector data composed of 2064 bytes of data indicated by 103 in FIG. 1, 202 is ID information included in each sector data 201, 203 is interleaved sector data (A), 204 Is interleaved sector data (B).

The 32 sector data 201 are alternately interleaved sector data (A) 203 and interleaved sector data (B) 20 according to the data order.
4 are interleaved and divided. In FIG. 2, each sector data 201 is stored in sector 0 according to the data order.
From sector 0, sectors 0, 2, 4, 6,
.., 30 are interleaved sector data (A) 203
The sectors 1, 3, 5, 7,..., 31 are divided into interleaved sector data (B) 204.

Each of the interleaved sector data (A) and (B) is composed of data for 16 sectors, and is arranged in a matrix of (12 × 16) rows × 172 columns.

(Product Code Generation Step) FIG. 3 is a configuration diagram of the product code (A) and the product code (B) of the embodiment.

In FIG. 3, reference numeral 301 denotes sector data indicated by 201 in FIG. The interleaved sector data (A) 203 (FIG. 2) and the interleaved sector data 302 are subjected to double error detection and correction coding in the row and column directions respectively in the product code generation step, and are product coded. A) 304 and product code (B) 30
It becomes 5.

In the product code generation step, the error detection and correction coding in the row and column directions is performed by, for example, a known Re, respectively.
ed-Solomon coded, a 10-byte PI parity 302 in the row direction, and a 16-byte PO parity in the column direction.
Parity 303 is added.

When each product code is viewed individually, the above-described interleaved sector data generation step is not performed, but the encoding method itself is the same as the conventional DVD. In the present embodiment, the improvement of the ability to correct a burst error is realized by collecting two conventional product codes and recording them in a predetermined interleave described later. Since the encoding method itself is not changed, an encoding method with high compatibility and high correction capability is realized. Further, by performing the above-described interleaved sector data generation step and a predetermined interleave step described later, it is possible to not only improve the correction capability but also to record the ID information at a constant interval when the information is recorded on the disk. Furthermore, even if an uncorrectable error occurs, the uncorrectable error can be located in a relatively unified form as logical sector data.

(First Interleaving Step) FIG.
FIG. 4 is a configuration diagram of first interleaved data (A) and (B) of the embodiment.

In FIG. 4, reference numeral 401 denotes sector data indicated by 301 in FIG. 3, reference numeral 404 denotes first interleaved data (A) generated in the first interleaving step, and reference numeral 405 denotes first interleaved data (B).
It is.

Product code (A) 304 and product code (B) 3
05 (FIG. 3), a PO parity 303 (FIG. 3) is inserted for each row of sector data, that is, for every 12 rows. As a result of the insertion, the PO parity 402
In the first interleaving step, the first interleaving data (A) 404 and the first interleaving data (B) 405 are generated by equally dividing the PO parity for each sector data.

(Second Interleaving Step) FIG.
FIG. 3 is a configuration diagram of first interleaved data (A) and second interleaved data (B) of the embodiment.

In FIG. 5, reference numeral 501 denotes first interleaved data (A), which is the same as 404 shown in FIG. Reference numeral 502 denotes second interleaved data (B), which is generated from the first interleaved data (B) 405 (FIG. 4) by a second interleaving step.

In the second interleaving step, the first
Sector data 401 of the interleaved data (B)
The upper 6 lines and the lower 6 lines in FIG. 4 are replaced. As a result of the replacement, in the second interleaved data (B), the ID information 504 is located in the seventh row from the top of each sector data.
In the second interleaving step, only the first interleave data (B) 405 (FIG. 4) is replaced with six rows, but the first interleave data (A) 40
No. 4 (FIG. 4) is not subjected to any processing.

(Third Interleave Step) In the third interleave step, the first interleave data (A) 501 and the second interleave data (B) 502 shown in FIG. In the order in which they were recorded.

First, the first row of the first interleaved data (A) 501, the first row of the second interleaved data (B) 502, and then the first row of the first interleaved data (A) 501 The second line, and so on, are sent alternately one line at a time.

By executing the third interleaving step as described above, the data of sector 0 and sector 1 can be obtained.
The data of sector 2 and sector 3, and similarly, each sector data is interleaved by two sectors and recorded on the disk medium. For example, the physical sector length is set to (172 + 10).
If the size is × 13, that is, the length of 13 rows, the logical sector and the physical sector do not match on a sector basis, but match on a two-sector basis.

At this time, ID information 503 and 504 are located at the head of all the physical sectors. For example, in a read-only disc, the address of the physical sector is assigned to the ID information 50.
When reproducing from 3,504, it is located at the head of each sector and at a fixed interval, and has a configuration that is easy to reproduce.

As described above, in the error correction encoding method for a disk medium according to the first embodiment of the present invention, the first to third interleaving is performed on the two product codes (A) and (B). By performing the steps and recording the data on the disk medium, the interleave length can be doubled, and a configuration resistant to burst errors can be realized. For example, in the conventional method of recording only one product code as it is, errors exceeding 16 lines, that is, (172)
When an error exceeding (+10) × 16 = 2912 bytes occurs, the correction becomes impossible. In this embodiment, (172+
10) Unable to correct for the first time with an error exceeding x32 = 5824 bytes.

Further, in the first embodiment of the present invention, the first through third codes are used for two product codes (A) and (B).
By performing the interleaving step described above and recording the data on a disk medium, it is possible not only to improve the correction capability but also to record the ID information at regular intervals when the information is recorded on the disk. Easy going. By facilitating address reproduction, for example, improvement in search performance can be realized.

Furthermore, even in the event that correction is impossible, the logical sector and the physical sector match in units of two sectors, and an error caused by a physical flaw or the like matches the logical sector in units of two sectors. This allows uncorrectable errors to be located in relatively unified form as logical sector data. By locating the uncorrectable error in a relatively unified manner as logical sector data, for example, when an MPEG compressed image is recorded, it is possible to relatively reduce image disturbance.

The first interleaving step, the second
Instead of performing the interleaving step and the third interleaving step step by step individually, FIG.
Directly from the product code (A) 304 and the product code (B) 305 shown in FIG.
It is obvious that a batch interleave step which is equivalent to sending the second interleaved data (B) 502 alternately for each row and recording the data on the disk in the order of transmission can be easily realized.

FIG. 6 is a block diagram of an error correction coding circuit for a disk medium according to a second embodiment of the present invention.

In this embodiment, an error correction coding circuit for performing the coding according to the error correction coding method shown in the first embodiment will be disclosed.

In FIG. 6, reference numeral 601 denotes an entire error correction coding circuit; 602, a semiconductor memory; RA used as a working memory of the error correction coding circuit 601;
M and 603 are bus / memory control circuits for controlling the recording and reproduction of the RAM 602 and the internal bus 610, and 604 is an input IF control circuit for inputting data to be recorded on the disk medium to the error correction circuit. Handshake circuit with decoder, or ATAPI or SCSI
Is a protocol control circuit. Further, the input IF control circuit 604 includes an ID information adding circuit including logical or physical address information of data to be recorded. Reference numeral 605 denotes an encoding circuit for a product code.
A PI code encoding circuit 608 for adding a 0-byte PI parity to each row;
It comprises a PO encoding circuit 607 for adding a PO parity of bytes to each column. 606 is a RAM 60
2 is the product code (A) shown in the first embodiment stored in
This is an output IF control circuit for executing the first to third interleaving steps at the same time when sending 304 and the product code (B) 305 to the modulation circuit, and also performs IF control with the modulation circuit. 609 is an error correction encoding circuit 601
This is an overall control circuit that performs overall control, and is configured by a microcontroller or the like.

The PO encoding circuit 507 and the PI encoding circuit 508 all perform Re encoding.
This is ed-Solomon encoding, and the encoding itself includes the well-known Reed-Sono of DVD including product encoding.
It can be constituted by a lomon encoding circuit.

Hereinafter, the operation of the error correction coding circuit 601 according to the second embodiment of the present invention will be described. As described above, the operation of each component of the error correction coding circuit 601 is as follows.
It is controlled by the overall control circuit 609.

The user data 611 sent from the host microcomputer or the MPEG encoder is input IF
The data is stored in the RAM 602 via the control circuit 604 and the bus / memory control circuit 603. At the time of storage, the user data 611 is divided into sectors, and ID information 202 is added to the head of each sector. The sector data including the ID information is composed of 172 × 12 = 2064 bytes, and the 32 sector data is divided into two sections alternately in the sector order, each of which is interleaved sector data composed of 16 sector data. Are stored in two areas of the RAM 602 in a matrix of 192 rows × 172 columns. The input IF control circuit 604 includes an address generation circuit for the RAM 602 (not shown) for this purpose. Obviously, the address generation circuit can be easily constituted by a counter, a simple control circuit, and the like.

For the stored interleaved sector data (A) and (B),
The I encoding is performed by the PI encoding circuit 608, and a 10-byte PI parity is added to each row.
Next, PO encoding is performed by the PO encoding circuit 607, and a 16-byte PO parity is added to each column. By the above processing, one product code is generated,
The second product code is similarly generated by the product code encoding circuit 605. Generated product codes (A) and (B)
Are stored in the RAM 602 in a matrix as shown in FIG.

The two product codes are then output to the RAM by the output IF control circuit 606 in accordance with the recording order on the disk.
The data is read out from 602 and sent to the modulation circuit to be recorded on a disk. The output IF control circuit 606 executes reading according to the address of the RAM 602 generated by the address generation circuit 613.

FIG. 7 shows an address generation circuit 613 (FIG. 6).
3 is a more detailed configuration diagram of FIG. 7, reference numeral 701 denotes an X counter for generating a column address; 702, a Y counter for generating a row address; 703, an A / B flag generation circuit for distinguishing between product codes (A) and (B);
Is an upper / lower 6-row interchange circuit for exchanging upper 6 rows and lower 6 rows of sector data, 705 is a selector, and 707 is a first interleaving step for dividing a PO row used in a conventional DVD into sector data one row at a time. Is a parity row interleave circuit for realizing. The outline of the operation of the address generation circuit 613 (FIG. 6) configured as described above will be described below.

X counter 701 and Y counter 702
Generates a column address and a row address, respectively, for reading a product code stored in a matrix. The X counter sequentially increments from 0 to 181 and repeats this. The Y counter is incremented for each row by two product codes, that is, for every 182 × 2 bytes. The A / B flag generation circuit 703 generates an A / B flag for distinguishing between product codes (A) and (B). A
The / B flag is a signal that toggles every line, that is, every 182 bytes. The above X counter 701 and Y counter 70
2. It is clear that the A / B flag generation circuit 703 can be constituted by a counter and a simple control circuit. Up and down 6
The row replacement circuit 704 includes a circuit for adding 6 to the value and a circuit for subtracting 6 to replace the upper 6 rows and the lower 6 rows of the sector data.
The subtraction and the last one line are kept as they are, and the process for 13 lines is repeated. Thus, for example, when the input Y address changes by one from 0 to 12, 6, 7, 8,.
The output is 11, 0, 1, 2,... 5, 12.
The selector 705 outputs the input from the upper and lower six-row permutation circuit 704 only when the A / B flag indicates the product code (B), and outputs the Y address as it is in the case of the product code (A). Parity row interleave circuit 706
A conventional DVD is provided with a PO address conversion circuit 707 for converting memory mapping into a row address where a PO parity row of a product code is stored whenever a value obtained by adding 1 to a row address sent from the selector becomes a multiple of 13. This is realized by the same configuration as the PO parity interleave circuit used in (1).

According to the address generation circuit shown in FIG. 7, the product code (A) stored in the RAM 602 (FIG. 6),
By reading (B) and (B), it is possible to execute batch interleaving in which the first to third interleaving steps are batched. It should be noted that the address generation circuit in FIG. 7 is an example, and it goes without saying that various realizing means are possible according to the case where the storage form of the product code in the RAM is changed.

As described above, the error correction coding circuit according to the second embodiment of the present invention, which performs the coding of the error correction code according to the error correction method of the first embodiment, has a strong correction against a burst error. It is possible to realize error correction coding that can demonstrate its ability. Further, by performing the first to third interleaving steps and recording the data on a disk medium, not only the correction capability is improved but also when the data is recorded on the disk, the ID
Information can be recorded at regular intervals, and address reproduction is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

In the above-described second embodiment of the present invention, an example in which batch interleaving is performed has been described. However, it is apparent that first to third interleaving may be performed sequentially and individually.

FIG. 8 is an external view of an optical disk according to the third embodiment of the present invention.

In FIG. 8, reference numeral 801 denotes an optical disk;
Reference numeral 2 denotes encoded data recorded on spiral or concentric tracks of the optical disc 301.
The encoded data 802 in the present embodiment records the error correction code of the first or second embodiment. In an optical disc, data is recorded as uneven pits or dark and light dots made of a phase change material or the like. Generally, at the time of recording, encoded data is digitally modulated by a modulation code such as 8/16 modulation and then recorded on a track of a disk. Here, the state where the modulation by the modulation code is omitted and the encoded data is recorded as it is is shown.

In the encoded data of the first or second embodiment, the symbol of the first row and first column of the first interleaved data (A) in FIG. 5 is recorded first on the optical disk, and First interleaved data (A) 501 and second interleaved data (B) are interleaved and recorded for each row. Reference numeral 803 denotes ID information added to the head of each sector data.
It is recorded at regular intervals every 2 × 13 bytes.

In the optical disk according to the third embodiment of the present invention, by recording the coded data shown in the first or second embodiment, two product codes are recorded in an interleaved manner, so that a burst error is recorded. , A strong correction capability can be realized, and highly reliable error correction can be performed. Furthermore, by recording ID information at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

FIG. 9 is a flowchart showing a correction algorithm of the error correction method according to the fourth embodiment of the present invention. The fourth embodiment of the present invention discloses a method for correcting an error correction code recorded on an optical disk 801 (FIG. 8).

In FIG. 9, reference numeral 901 denotes a third deinterleave step, 902 denotes a second deinterleave step, 903 denotes a first deinterleave step, and 904 denotes an error correction step.

First, as a third deinterleaving step 901, the reproduction data read from the disk medium is divided into two in the RAM every 182 bytes, and each is divided into a matrix of 208 rows × 182 columns. Store in memory.
The stored reproduction data is stored as first interleaved data (A) and second interleaved data (B), similar to 501 and 502 in FIG. 5 in the first embodiment.

As a second deinterleaving step 902, the second interleaved data (B) stored in the RAM is divided into 16 pieces for every 13 rows, and the divided 16
For each of these, the upper 6 lines and the subsequent lower 6 lines are replaced in line units. As a result of this step, 404 in FIG.
And 405, as the first interleaved data (A) and the first interleaved data (B).
M. In this step, the first interleaved data (A) does not change.

As a first deinterleaving step 903, the two pieces of first interleaved data (A) and (B) are each divided into 16 rows every 13 rows, and each of the divided 16 rows is divided into 16 rows. Then, it is extracted line by line from the lowest order and summarized as PO parity. As a result of this step, a product code (A) similar to 304 and 305 in FIG.
And the product code (B) are stored in the RAM. This step is the same as the deinterleaving step of the parity row interleaving in the conventional DVD when the first interleaved data (A) and (B) are viewed independently. The only difference is that you need to do it twice.

As an error correction step 904, each of the two product codes (A) and (B) is corrected. This step is also the same as the error correction of the conventional DVD, and is different only in that it needs to be performed twice.

In the error correction method according to the fourth embodiment of the present invention, which performs error correction according to the above-described correction algorithm, by reproducing the encoded data shown in the first or second embodiment, Since the product code is recorded in an interleaved manner, it is possible to realize a strong correction capability with respect to a burst error, and to perform highly reliable error correction. Further, since the ID information is recorded at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

In the present embodiment, the first to third deinterleaving steps are performed sequentially as independent steps. However, a direct step of storing two product codes in the memory so as to directly form two product codes from reproduced data is used. Needless to say, it can be configured.

FIG. 10 is a configuration diagram of an error correction circuit according to a fifth embodiment of the present invention. This embodiment discloses an error correction circuit that corrects an error correction code recorded on the optical disk shown in FIG.

In FIG. 10, reference numeral 1001 denotes an entire error correction circuit; 1002, a semiconductor memory which is used as a working memory of the error correction circuit 1001;
Reference numeral 003 denotes recording / reproduction control for the RAM 1002 and the internal bus 1
A bus / memory control circuit for controlling 010 and an output IF control circuit 1004 for outputting error-corrected user data, for example, a handshake circuit with an MPEG decoder, or an ATAPI or SCSI protocol control circuit. Further, the output IF control circuit 1004 includes an ID information deletion circuit for deleting ID information added to each sector data. Reference numeral 1005 denotes a product code (A) and product code (B) error correction circuit, which corrects an error in each row of a PI code obtained by adding a 10-byte PI parity to 172-byte data. 100
8 and 16 bytes of PO for 192 bytes of data
It is composed of a PO code error correction circuit 1007 that corrects an error of the PO code added with parity for each column. 10
06 is the RAM 1 for storing the reproduced data reproduced from the disk.
002 is an input IF control circuit stored in the RAM 10
When the reproduction data is stored in 02, the third deinterleave step to the first deinterleave step shown in the fourth embodiment are collectively executed. Further, it performs IF control with the demodulation circuit. 1009 is an error correction circuit 1001
This is an overall control circuit that performs overall control, and is configured by a microcontroller or the like.

Incidentally, the PO code error correction circuit 1007,
And all error correction circuits of the PI code error correction circuit 1008 are error correction of Reed-Solomon code. The product codes (A) and (B) can be executed by simply using the correction circuit twice.

Hereinafter, the operation of the error correction circuit 1001 according to the fifth embodiment of the present invention will be described. As described above, the operation of each component of the error correction encoding circuit 1001 is controlled by the overall control circuit 1009.

Reproduction data 1 reproduced from a disk medium
011 is stored in the RAM 1002 via the input IF control circuit 1006 and the bus / memory control circuit 1003. The input IF control circuit 1006 generates an address of the RAM 1002 which is equivalent to executing the following three interleaving steps at the time of storing the input reproduction data 1011 in the RAM. The address generation is performed by the address generation circuit 1013. The address generation circuit 1013 is the same as the address generation circuit 613 of the error correction coding circuit of the second embodiment shown in FIG. 7, and stores the reproduction data 1011 in the RAM 1002 according to the address of the address generation circuit 1013. Here, the details of the address generation circuit 1013 are omitted.

(Third Deinterleaving Step) First, the reproduction data read from the disk medium is
It is divided into two every 182 bytes on the AM, and each is divided into 208
The data is stored in the memory in a matrix of rows × 182 columns. The stored reproduction data is the same as the first interleaved data (A) similar to 501 and 502 in FIG. 5 in the first embodiment.
And the second interleaved data (B).

(Second Deinterleaving Step) RA
The second interleaved data (B) stored in M
The image is divided into 16 lines every three lines, and for each of the 16 lines, the upper 6 lines and the succeeding lower 6 lines are replaced in line units. As a result of this step, 404 and 40 in FIG.
5, the first interleaved data (A) and the first
Is stored in the RAM as interleaved data (B). In this step, the first interleaved data (A)
Does not change.

(First Deinterleaving Step) Two first interleaved data (A) and (B)
Is divided into 16 pieces every 13 lines, and the divided 16
For each of them, one row is extracted from the lowest order and collected as PO parity. As a result of this step, FIG.
Are stored in the RAM as a product code (A) and a product code (B), similar to 304 and 305.

The above three deinterleaving steps are performed collectively, that is, the RAM 1 of the reproduced data 1011
Storing the data in the RAM 1002 once is stored in the RAM 1002.
Stored as a product code (A) and a product code (B).

An error correction of each product code is performed by the product code error correction circuit 1005 on the reproduced data divided and stored in the two product codes (A) and (B). First, error correction of the PI code is executed by the PI code error correction circuit 1008. Since a PI parity of 10 bytes is added to each row, error correction of a maximum of 5 bytes is executed. Next, the PO code error correction is executed by the PO code error correction circuit 1007, and a 16-byte PO parity is added to each column.
Error correction of up to 8 bytes is performed. Through the above processing, error correction of one product code is performed, and error correction of the second product code is similarly performed by the product code error correction circuit 1005. In the above error correction,
It is possible to perform more reliable error correction by using known repetition correction and erasure correction.

Next, the output IF control circuit 1004 reads out the sector data of the two product codes, for which the error correction has been executed, from the RAM 1002 and sends them to the MPEG decoding circuit and the host computer. At the time of transmission, the ID information added to the head of each sector data is deleted, and only the user data is transmitted to the MPEG decoding circuit or the host computer. In addition, deletion of ID information
Once the entire sector data including ID information is stored in RAM 1002
May be deleted after reading from
Obviously, only the user data excluding the information may be read from the RAM 1002. In reading, each sector data stored in the RAM 1002 may be deinterleaved and read in sector order. Although not shown, an address generating circuit for deinterleaving and reading in the order of sectors is provided in the output IF control circuit 1.
It is apparent that the counter is included in 004 and can be constituted by a simple counter or the like.

As described above, in the error correction circuit according to the fifth embodiment of the present invention, by reproducing the encoded data shown in the first or second embodiment, two product codes are interleaved. Since it is recorded, it is possible to realize a strong correction capability against a burst error, and it is possible to perform highly reliable error correction. Further, since the ID information is recorded at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

In the present embodiment, the address generation circuit and the input IF control circuit for executing the first to third deinterleaving steps collectively are disclosed, but they may be performed as independent steps in order.

Hereinafter, an error correction encoding method for a disk medium according to the sixth embodiment of the present invention will be described.

The error correction encoding method for a disk medium in the sixth embodiment differs from the first embodiment in the second interleaving step. Similarly to the first embodiment, by performing the sector data generation step, the interleave sector data generation step, the product code generation step, and the first interleave step, the first interleave data (A) 404 shown in FIG. And first interleaved data (B) 405 are generated. The description of the sector data generation step, the interleave sector data generation step, the product code generation step, and the first interleave step is the same as in the first embodiment, and will not be repeated.

FIG. 11 is a configuration diagram of the first interleaved data (A) and the second interleaved data (B) according to the sixth embodiment of the present invention.

(Second Interleaving Step) FIG.
In FIG. 4, reference numeral 1101 denotes first interleaved data (A), which is the same as 404 shown in FIG. 110
Reference numeral 2 denotes second interleaved data (B), which is generated from the first interleaved data (B) 405 in FIG. 4 by a second interleaving step.

In the second interleaving step, the first
The second interleaved data (B) 1102 is generated by cyclically shifting the twelve rows of sector data 401 and each one PO row of the interleaved data (B) by six rows in the column direction. In the second interleaved data (B) 1102,
Each ID information 1104 is located on the seventh row from the top of each sector data, and each PO row 1106 is located on the sixth row from the top. In the second interleaving step, a cyclic shift of 6 rows is performed only on the first interleaved data (B) 405, but the first interleaved data (A) 4
04 is not subjected to any processing.

(Third Interleave Step) In the third interleave step, the first interleave data (A) 1101 and the second interleave data (B) 1102 shown in FIG. In the order in which they were recorded.

First, the first row of the first interleaved data (A) 1101, the first row of the second interleaved data (B) 1102, and then the first row of the first interleaved data (A) 1101 2nd line, and so on
Send out line by line.

By executing the third interleaving step as described above, the data of sector 0 and sector 1 can be obtained.
The data of sector 2 and sector 3, and similarly, each sector data is interleaved by two sectors and recorded on the disk medium. For example, the physical sector length is set to (172 + 10).
× 13, that is, assuming a length of 13 rows, the logical sector and the physical sector do not match in sector units,
This is consistent when looking at two sectors.

At this time, the ID information 1103 and 1104 are located at the head of all the physical sectors. For example, when the address of the physical sector is reproduced from the ID information 1103 and 1104 on a read-only disc, at the head of each sector. , And at regular intervals, so that it is easy to reproduce. In this embodiment, unlike the first embodiment, the number of PO rows included in each physical sector is one by one.
There is an advantage that the data structure of each physical sector can be the same.

As described above, in the error correction coding method for a disk medium according to the sixth embodiment of the present invention, the first to third interleaving is performed on the two product codes (A) and (B). By performing the steps and recording the data on the disk medium, the interleave length can be doubled, and a configuration resistant to burst errors can be realized. For example, in the conventional method of recording only one product code as it is, errors exceeding 16 lines, that is, (172)
When an error exceeding (+10) × 16 = 2912 bytes occurs, the correction becomes impossible. In this embodiment, (172+
10) Unable to correct for the first time with an error exceeding x32 = 5824 bytes.

Further, in the sixth embodiment of the present invention, the first through third product codes are used for two product codes (A) and (B).
By performing the interleaving step described above and recording the data on a disk medium, it is possible not only to improve the correction capability but also to record the ID information at regular intervals when the information is recorded on the disk. Easy going. By facilitating address reproduction, for example, improvement in search performance can be realized.

Furthermore, even in the event that correction is impossible, the logical sector and the physical sector match in two-sector units, and the error generated due to physical damage or the like matches the logical sector in two-sector units. This allows uncorrectable errors to be located in relatively unified form as logical sector data. By locating the uncorrectable error in a relatively unified manner as logical sector data, for example, when an MPEG compressed image is recorded, it is possible to relatively reduce image disturbance.

Further, the number of PO rows included in each physical sector is also one by one, and the data structure of each physical sector can be the same.

Note that the first interleave step, the second interleave step, and the third interleave step are not individually executed in order, but the product code (A) 304 and the product code (B) shown in FIG. 305 directly from the interleaved data (A) 110 shown in FIG.
It is clear that a batch interleaving step that is equivalent to sending the first and second interleaved data (B) 1102 alternately row by row and recording them on the disk in the order of transmission can be easily realized.

FIG. 12 is a diagram showing the configuration of an error correction encoding circuit for a disk medium according to a seventh embodiment of the present invention. In the present embodiment, an error correction coding circuit for performing the coding according to the error correction coding method shown in the sixth embodiment will be disclosed.

In FIG. 6, reference numeral 1201 denotes an entire error correction coding circuit; 1202, a RAM used as a working memory of the error correction coding circuit 1201; 1203, control of recording / reproduction to / from the RAM 1202; A bus / memory control circuit for controlling 1210;
An input IF control circuit 1204 inputs data to be recorded on the disk medium to the error correction circuit.
Handshake circuit with EG decoder, or ATAP
It is an I or SCSI protocol control circuit. Further, the input IF control circuit 1204 includes an ID information adding circuit including logical or physical address information of data to be recorded.
Reference numeral 1205 denotes a product code encoding circuit, which includes a PI code encoding circuit 1208 for adding a 10-byte PI parity to 172-byte data for each row and a 16-byte PO parity for 192-byte data. It comprises a PO code encoding circuit 1207 added for each column.
An output IF control 1206 performs batch operation of the first to third interleaving steps when transmitting the product code (A) 304 and the product code (B) 305 stored in the RAM 1202 to the modulation circuit. It is a circuit and also performs IF control with the modulation circuit. Reference numeral 1209 denotes an overall control circuit for controlling the entire error correction encoding circuit 1201, which is configured by a microcontroller or the like, and controls output IF control 1206.
Only the second embodiment differs from the second embodiment of the present invention.

The operation of the error correction coding circuit 1201 according to the seventh embodiment of the present invention will be described below. As described above, the operation of each component of the error correction encoding circuit 1201 is controlled by the overall control circuit 1209.

The user data 1211 sent from the host microcomputer or the MPEG encoder is input I
The data is stored in the RAM 1202 via the F control circuit 1204 and the bus / memory control circuit 1203. When storing,
The user data 1211 is divided into sectors, and ID information 202 is added to the beginning of each sector. The sector data including the ID information is composed of 172 × 12 = 2064 bytes, and the 32 sector data is divided into two sections alternately in the sector order, and each is divided into 16 sector data as interleaved sector data. ,
The data is stored in two areas of the RAM 1202 in a matrix of 192 rows × 172 columns. The input IF control circuit 1204 includes:
For this purpose, an address generation circuit for the RAM 1202 (not shown) is provided. Obviously, the address generation circuit can be easily constituted by a counter, a simple control circuit, and the like.

For the stored interleaved sector data (A) and (B),
The I encoding is performed by the PI encoding circuit 1208, and a 10-byte PI parity is added to each row.
Next, PO encoding is performed by a PO encoding circuit 1207, and a 16-byte PO parity is added to each column. By the above processing, one product code is generated, and the second product code is similarly generated by the product code encoding circuit 120.
5 generated. The generated product codes (A) and (B) are stored in the RAM 1202 in a matrix as shown in FIG.

The two product codes are then output by the output IF control circuit 1206 according to the recording order on the disk.
It is read from M1202, sent to the modulation circuit, and recorded on the disk. The output IF control circuit 1206 performs reading according to the address of the RAM 1202 generated by the address generation circuit 1213.

FIG. 13 is a more detailed block diagram of the address generation circuit 1213. 13, reference numeral 1301 denotes an X counter for generating a column address; 1302, a Y counter for generating a row address; 1303, an A / B flag generation circuit for distinguishing between product codes (A) and (B);
4 is a 6-row cyclic shift circuit for cyclically shifting each row of PO data by 6 rows in the column direction, 1305 is a selector, and 1307 is a PO used in a conventional DVD. This is a parity row interleaving circuit for implementing a first interleaving step of dividing a row into sector data one by one. An outline of the operation of the address generation circuit 1213 configured as described above will be described below.

X counter 1301 and Y counter 13
02 is for reading a product code stored in a matrix.
Generate a column address and a row address, respectively. X
The counter increments sequentially from 0 to 181.
Repeat this. The Y counter is 1 for both product codes.
Increment every row, that is, every 182 × 2 bytes. The A / B flag generation circuit 1303 calculates the product code (A)
An A / B flag for distinguishing between (A) and (B) is generated. The A / B flag is a signal that toggles every row, that is, every 182 bytes. Obviously, the X counter 1301, the Y counter 1302, and the A / B flag generation circuit 1303 can be constituted by a counter and a simple control circuit. The 6-row shift circuit 1304 stores the sector data and P
In order to cyclically shift the O row by six rows in the column direction, for example, the following operation is performed on the input Y address, and the output Y ′ is transmitted.

A quotient and a remainder obtained by dividing the input Y address by 13 are obtained, 6 is added to the remainder, and this is modulo-operated by 13. The result of the modulo operation and the quotient × 13 are added and sent to the selector. The following operation is shown by the expression.

Y ′ = “Y / 13” × 13 + ((Ymod
13) +6) mod13 Here, “x” is a maximum integer equal to or less than x.

Only when the A / B flag indicates the product code (B), the selector 1305 selects the six-row cyclic shift circuit 1
The input from the controller 304 is output. In the case of the product code (A), the Y address is output as it is. The parity row interleave circuit 1306 outputs a product code PO every time a value obtained by adding 1 to the row address sent from the selector becomes a multiple of 13.
A PO address conversion circuit 1307 for converting memory mapping into a row address at which a parity row is stored is provided, and is realized by a configuration similar to a PO parity interleave circuit used in a conventional DVD.

By reading the product codes (A) and (B) stored in the RAM 1202 in accordance with the address generation circuit shown in FIG. 13, batch interleaving in which the first to third interleaving steps are batched is executed. be able to. Note that the address generation circuit in FIG. 13 is an example, and it goes without saying that various realizing means are possible according to the case where the storage form of the product code in the RAM is changed.

As described above, the error correction coding circuit according to the seventh embodiment of the present invention, which performs the coding of the error correction code according to the error correction method of the sixth embodiment, has a strong correction against a burst error. It is possible to realize error correction coding that can demonstrate its ability. Further, by performing the first to third interleaving steps and recording the data on a disk medium, not only the correction capability is improved but also when the data is recorded on the disk, the ID
Information can be recorded at regular intervals, and address reproduction is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

Further, in the present embodiment, unlike the second embodiment, the number of PO rows included in each physical sector is one by one.
There is an advantage that the data structure of each physical sector can be the same.

In the above-described seventh embodiment of the present invention, an example in which batch interleaving is performed has been described. However, it is apparent that first to third interleaving may be performed sequentially and individually.

FIG. 14 is an external view of an optical disk according to the eighth embodiment of the present invention.

Referring to FIG. 14, reference numeral 1401 denotes an optical disk;
Reference numeral 1402 denotes encoded data recorded on spiral or concentric tracks of the optical disk 1401. The encoded data 1402 in this embodiment records the error correction code of the sixth or seventh embodiment.

In the optical disk, data is recorded as uneven pits or light and dark dots made of a phase change material or the like. Generally, at the time of recording, encoded data is digitally modulated by a modulation code such as 8/16 modulation and then recorded on a track of a disk. Here, the state where the modulation by the modulation code is omitted and the encoded data is recorded as it is is shown.

In the coded data of the sixth or seventh embodiment, the symbol of the first row and first column of the first interleaved data (A) in FIG. 11 is recorded first on the optical disc. First interleaved data (A) 1101 and second interleaved data (B) 1
102 are recorded interleaved for each row.
Reference numeral 1403 denotes ID information added to the head of each sector data, which is recorded at regular intervals every 182 × 13 bytes. Reference numeral 1404 denotes a PO parity, which is recorded on the disk at regular intervals one line at a time. In the present embodiment, unlike the first embodiment, the data structure of each physical sector is the same.

In the optical disk according to the eighth embodiment of the present invention, since the encoded data shown in the sixth or seventh embodiment is recorded, two product codes are interleaved and recorded. A strong correction capability can be realized for a burst error, and highly reliable error correction can be performed. Furthermore, by recording ID information at regular intervals, address reproduction including the control circuit is facilitated.
By facilitating address reproduction, for example, improvement in search performance can be realized.

Further, in this embodiment, unlike the first embodiment, the number of PO rows included in each physical sector is one by one.
The data structure of each physical sector is the same.

FIG. 15 is a flowchart showing a correction algorithm of the error correction method according to the ninth embodiment of the present invention. The ninth embodiment of the present invention discloses a method of correcting an error correction code recorded on the optical disk shown in FIG.

In FIG. 15, reference numeral 1501 denotes a third deinterleaving step, 1502 denotes a second deinterleaving step, 1503 denotes a first deinterleaving step,
504 is an error correction step.

Third deinterleaving step 150
1. First, the reproduction data read from the disk medium is divided into two pieces on a RAM every 182 bytes, and each is stored in a memory in a matrix of 208 rows × 182 columns. The stored reproduction data is stored as first interleaved data (A) and second interleaved data (B), similar to 1101 and 1102 in FIG. 11 in the sixth embodiment.

Second deinterleaving step 150
2. The second interleaved data (B) stored in the RAM is divided into 16 pieces for every 13 rows, and the divided 16
For each of these, a cyclic permutation of six rows is performed in the column direction. As a result of this step, similar to 404 and 405 in FIG.
They are stored in the RAM as first interleaved data (A) and first interleaved data (B). In this step, the first interleaved data (A) does not change.

First deinterleaving step 150
Each of the three first and second interleaved data (A) and (B) is divided into 16 pieces every 13 rows, and each of the 16 divided pieces is extracted one by one from the bottom. Put together as PO parity. This step is the same as the first deinterleaving step in the fourth embodiment of the present invention. As a result of this step, the same product code (A) and product code (B) are stored in the RAM as 304 and 305 in FIG. This step is the same as the deinterleaving step of parity row interleaving in the conventional DVD when the first interleaved data (A) and (B) are viewed independently. The only difference is that you need to do it twice.

Error Correction Step 1504 Each of the two product codes (A) and (B) is corrected. This step is also the same as the error correction of the conventional DVD, and is different only in that it needs to be performed twice.

In the error correction method according to the ninth embodiment of the present invention, which performs error correction according to the above-described correction algorithm, by reproducing the encoded data shown in the sixth or seventh embodiment, Since the product code is recorded in an interleaved manner, it is possible to realize a strong correction capability with respect to a burst error, and to perform highly reliable error correction. Further, since the ID information is recorded at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

Furthermore, the number of PO rows included in each physical sector is also one by one, and the data structure of each physical sector can be the same.

In the present embodiment, the first to third deinterleaving steps are sequentially performed as independent steps. However, a direct step of storing two product codes in the memory so as to directly form two product codes from reproduced data is used. Needless to say, it can be configured.

FIG. 16 is a configuration diagram of an error correction circuit according to the tenth embodiment of the present invention. In this embodiment,
An error correction circuit for correcting an error correction code recorded on the optical disk shown in FIG. 14 is disclosed.

Referring to FIG. 16, reference numeral 1601 denotes an entire error correction circuit; 1602, a semiconductor memory; a RAM used as a working memory of the error correction circuit 1601;
Reference numeral 603 denotes recording / reproduction control to the RAM 1602 and the internal bus 1
A bus / memory control circuit 610 controls the output IF control circuit 1604 for outputting error-corrected user data. For example, it is a handshake circuit with an MPEG decoder or an ATAPI or SCSI protocol control circuit. Further, the output IF control circuit 1604 includes an ID information deletion circuit for deleting ID information added to each sector data. Reference numeral 1605 denotes a product code (A) and product code (B) error correction circuit, which corrects an error in each row of a PI code obtained by adding a 10-byte PI parity to 172-byte data. 100
8 and 16 bytes of PO for 192 bytes of data
It is composed of a PO code error correction circuit 1607 for correcting an error of the PO code added with parity for each column. 16
06 is the RAM 1 for storing the reproduced data reproduced from the disk.
The input IF control circuit stored in the RAM 602
When the reproduction data is stored in 02, the third deinterleave step to the first deinterleave step shown in the ninth embodiment are collectively executed. Further, it performs IF control with the demodulation circuit. 1609 is an error correction circuit 1601
This is an overall control circuit that performs overall control, and is configured by a microcontroller or the like.

The above PO code error correction circuit 1607,
And all error correction circuits of the PI code error correction circuit 1608 are error correction of Reed-Solomon code, and the error correction itself includes a well-known Reed-Solomon error correction circuit of DVD including an error correction as a product code. And the product codes (A) and (B) can be executed simply by using the correction circuit twice.

Hereinafter, the operation of the error correction circuit 1601 according to the tenth embodiment of the present invention will be described. As mentioned above,
The operation of each component of the error correction coding circuit 1601 is controlled by the overall control circuit 1609.

Reproduction data 1 reproduced from a disk medium
611 is stored in the RAM 1602 via the input IF control circuit 1606 and the bus / memory control circuit 1603. The input IF control circuit 1606 generates an address of the RAM 1602, which is equivalent to executing the following three interleaving steps collectively when storing the input reproduction data 1611 on the RAM. The address generation is performed by the address generation circuit 1613. The address generation circuit 1613 is the same as the address generation circuit 1213 of the error correction encoding circuit of the seventh embodiment shown in FIG. 13, and stores the reproduction data 1611 in the RAM 1602 according to the address of the address generation circuit 1613. Here, details of the address generation circuit 1613 are omitted.

(Third Deinterleaving Step) First, the reproduction data read from the disk medium is
It is divided into two every 182 bytes on the AM, and each is divided into 208
The data is stored in the memory in a matrix of rows × 182 columns. The stored reproduction data is the same as 1101 in FIG. 11 in the sixth embodiment.
And 1102, are stored as first interleaved data (A) and second interleaved data (B).

(Second Deinterleaving Step) RA
The second interleaved data (B) stored in M
It is divided into 16 every three rows, and each of the divided 16 pieces is cyclically shifted in the column direction in row units. As a result of this step, the first, similar to 404 and 405 in FIG.
Are stored in the RAM as the interleaved data (A) and the first interleaved data (B). In this step, the first interleaved data (A) does not change.

(First Deinterleaving Step) Two first interleaved data (A) and (B)
Is divided into 16 pieces every 13 lines, and the divided 16
For each of them, one row is extracted from the lowest order and collected as PO parity. As a result of this step, FIG.
Are stored in the RAM as a product code (A) and a product code (B), similar to 304 and 305.

The above three deinterleaving steps are performed collectively, that is, the RAM 1 of the reproduction data 1611
By performing storage once in the 602, the RAM 1602 has
Stored as a product code (A) and a product code (B).

For the reproduced data divided and stored in the two product codes (A) and (B), error correction of each product code is executed by the product code error correction circuit 1605. First, the PI code error correction is performed by the PI code error correction circuit 1608, and since a 10-byte PI parity is added to each row, error correction of up to 5 bytes is performed. Next, the PO code error correction is performed by the PO code error correction circuit 1607, and a 16-byte PO parity is added to each column.
Error correction of up to 8 bytes is performed. Through the above processing, error correction of one product code is performed, and error correction of the second product code is similarly performed by the product code error correction circuit 1605. In the above error correction,
It is possible to perform more reliable error correction by using known repetition correction and erasure correction.

Next, the sector data of the two product codes subjected to the error correction are read from the RAM 1602 by the output IF control circuit 1604 and sent to the MPEG decoding circuit and the host computer. At the time of transmission, the ID information added to the head of each sector data is deleted, and only the user data is transmitted to the MPEG decoding circuit or the host computer. In addition, deletion of ID information
The entire sector data including the ID information is temporarily stored in the RAM 1602.
May be deleted after reading from
Obviously, only the user data excluding the information may be read from the RAM 1602. In reading, each sector data stored in the RAM 1602 may be deinterleaved and read in sector order. An address generation circuit (not shown) for deinterleaving and reading out in the order of the sectors includes an output IF control circuit 160.
It is obvious that this can be constituted by a simple counter or the like included in the above.

As described above, in the error correction circuit according to the tenth embodiment of the present invention, the two product codes are interleaved by reproducing the encoded data shown in the sixth or seventh embodiment. Since it is recorded, it is possible to realize a strong correction capability against a burst error, and it is possible to perform highly reliable error correction. Further, since the ID information is recorded at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address playback,
The number of PO rows included in each physical sector is also one by one, and there is an advantage that the data structure of each physical sector can be the same. For example, an improvement in search performance can be realized.

Also, the number of PO rows included in each physical sector is one.
Each row has the same data structure for each physical sector.

In the present embodiment, the address generation circuit and the input IF control circuit for executing the first to third deinterleaving steps collectively are disclosed, but they may be performed as independent steps in order.

Hereinafter, an error correction encoding method for a disk medium according to the eleventh embodiment of the present invention will be described.

The error correction encoding method for a disk medium according to the eleventh embodiment differs from the first and sixth embodiments in the second interleaving step. As in the first embodiment, by performing a sector data generation step, an interleaved sector data generation step, a product code generation step, and a first interleave step, FIG.
The first interleaved data (A) 404 and the first interleaved data (B) 405 shown in FIG.

The description of the sector data generating step, the interleaved sector data generating step, the product code generating step, and the first interleaving step is the same as that of the first embodiment, and will not be repeated.

FIG. 17 shows a second embodiment of the eleventh embodiment of the present invention.
3 is a configuration diagram of the interleaved data (A) and the second interleaved data (B).

(Second interleaving step (B))
In FIG. 17, reference numeral 1702 denotes second interleave data (B), and second interleave step (B)
As a result, the first interleaved data (B) 40 in FIG.
5 is generated.

In the second interleaving step (B), the upper 6 rows and the lower 6 rows of each sector data 401 of the first interleaved data (B) are replaced. As a result of the replacement, in the second interleaved data (B) 1702,
The ID information 1704 is located in the seventh row from the top of each sector data.

(Second interleaving step (A))
In FIG. 17, reference numeral 1701 denotes second interleave data (A), and the first interleave data (A) 404 in FIG. 4 is obtained by the second interleave step (A).
Generated from

In the second interleaving step (A), each PO parity row of the first interleaved data (A) 404 is inserted into the seventh row from the top of each sector data 401. Each PO row 1705 is located on the seventh row from the top.

(Third Interleave Step) In the third interleave step, the second interleave data (A) 1701 and the second interleave data (B) 1702 shown in FIG. In the order in which they were recorded.

First, the first line of the second interleaved data (A) 1701, the first line of the second interleaved data (B) 1702, and then the second line of the second interleaved data (A) 1701 Second line, and so on
Send one line at a time.

By performing the third interleaving step as described above, the data of sector 0 and sector 1 can be obtained.
The data of sector 2 and sector 3, and similarly, each sector data is interleaved by two sectors and recorded on the disk medium. For example, the physical sector length is set to (172 + 10).
If the size is × 13, that is, the length of 13 rows, the logical sector and the physical sector do not match on a sector basis, but match on a two-sector basis.

At this time, ID information 1703 and 1704 are located at the beginning of all physical sectors. For example, when reproducing the physical sector address from the ID information 1703 and 1704 on a read-only disc, at the beginning of each sector. , And at regular intervals, so that it is easy to reproduce. Also, in the present embodiment, unlike the first and sixth embodiments, the PO row included in each physical sector is also one row at the end of the physical sector, and the data structure of each physical sector is the same as that of the conventional DVD. There is an advantage that it can be done.

As described above, in the error correction encoding method for a disk medium according to the eleventh embodiment of the present invention, the first to third interleaving is performed for two product codes (A) and (B). By performing the steps and recording the data on the disk medium, the interleave length can be doubled, and a configuration resistant to burst errors can be realized. For example, in the conventional method of recording only one product code as it is, errors exceeding 16 lines, that is, (172)
When an error exceeding (+10) × 16 = 2912 bytes occurs, the correction becomes impossible. In this embodiment, (172+
10) Unable to correct for the first time with an error exceeding x32 = 5824 bytes.

Further, in the eleventh embodiment of the present invention, 2
By performing the first to third interleaving steps on the two product codes (A) and (B) and recording them on a disk medium, not only improving the correction capability but also recording on a disk In addition, it is possible to record ID information at regular intervals, thereby facilitating address reproduction. By facilitating address reproduction, for example, improvement in search performance can be realized.

Furthermore, even in the event that correction is impossible, the logical sector and the physical sector match in two-sector units, and the error generated due to physical damage or the like matches the logical sector in two-sector units. This allows uncorrectable errors to be located in relatively unified form as logical sector data. By locating the uncorrectable error in a relatively unified manner as logical sector data, for example, when an MPEG compressed image is recorded, it is possible to relatively reduce image disturbance.

Further, the PO rows included in each physical sector are arranged one row at a time in the last row similarly to the conventional DVD, and the data structure of each physical sector can be made the same.

The first interleaving step, the second interleaving step (A), the second interleaving step (B), and the third interleaving step are not individually executed in order, but are shown in FIG. Second interleaved data (A) 1701 shown in FIG. 17 directly from product code (A) 304 and product code (B) 305
It is obvious that a batch interleaving step which is equivalent to transmitting the second interleaved data (B) 1702 alternately row by row and recording the data on the disk in the order of transmission can be easily realized.

FIG. 18 is a block diagram of an error correction coding circuit for a disk medium according to the twelfth embodiment of the present invention.

The present embodiment discloses an error correction coding circuit for performing the coding according to the error correction coding method shown in the eleventh embodiment.

In FIG. 18, reference numeral 1801 denotes an entire error correction coding circuit; 1802, a RAM used as a working memory of the error correction coding circuit 1801; A bus / memory control circuit for controlling 1810, an input IF control circuit 1804 for inputting data to be recorded on a disk medium to an error correction circuit, for example,
Handshake circuit with MPEG decoder, or AT
It is an API or SCSI protocol control circuit. Further, the input IF control circuit 1804 includes an ID information adding circuit including logical or physical address information of data to be recorded. Reference numeral 1811 denotes a product code encoding circuit which includes a PI code encoding circuit 1808 for adding a 10-byte PI parity to 172-byte data for each row and a 16-byte PO parity for 192-byte data. It comprises a PO code encoding circuit 1807 added to each column. Reference numeral 1806 denotes an output IF control for executing the first to third interleaving steps collectively when sending the product code (A) 304 and the product code (B) 305 stored in the RAM 1802 to the modulation circuit. It is a circuit and also performs IF control with the modulation circuit. Reference numeral 1809 denotes an overall control circuit for controlling the entire error correction encoding circuit 1801, which is constituted by a microcontroller or the like, and which controls an output IF control 1801.
Only Example 6 is different from Example 2 and Example 7 of the present invention.

Hereinafter, the operation of the error correction circuit 1801 according to the twelfth embodiment of the present invention will be described. As mentioned above,
The operation of each component of the error correction coding circuit 1801 is controlled by the general control circuit 1809.

The user data 1811 sent from the host microcomputer, the MPEG encoder, etc.
The data is stored in the RAM 1802 via the F control circuit 1804 and the bus / memory control circuit 1803. When storing,
The user data 1811 is divided into sector units, and ID information 202 is added to the head of each sector. The sector data including the ID information is composed of 172 × 12 = 2064 bytes, and the 32 sector data is divided into two sections alternately in the sector order, and each is divided into 16 sector data as interleaved sector data. ,
The data is stored in two areas of the RAM 1802 in a matrix of 192 rows × 172 columns. The input IF control circuit 1804 includes:
For this purpose, an address generation circuit for the RAM 1802 (not shown) is provided. Obviously, the address generation circuit can be easily constituted by a counter, a simple control circuit, and the like.

For the stored interleaved sector data (A) and (B),
The I encoding is performed by the PI encoding circuit 1808, and a 10-byte PI parity is added to each row.
Next, PO encoding is performed by the PO encoding circuit 1807, and a 16-byte PO parity is added to each column. By the above processing, one product code is generated, and the second product code is similarly processed by the product code encoding circuit 180.
5 generated. The generated product codes (A) and (B) are stored in the RAM 1802 in a matrix as shown in FIG.

The two product codes are then output to the output IF control circuit 1806 in accordance with the recording order on the disk.
The data is read from M1802, sent to the modulation circuit, and recorded on the disk. The output IF control circuit 1806 executes reading according to the address of the RAM 1802 generated by the address generation circuit 1813.

FIG. 19 is a more detailed block diagram of the address generation circuit 1813. 19, reference numeral 1901 denotes an X counter for generating a column address; 1902, a Y counter for generating a row address; 1903, an A / B flag generation circuit for distinguishing between product codes (A) and (B);
Numeral 4 denotes an upper / lower 6-row switching circuit for switching upper 6 rows and lower 6 rows of sector data for performing the second interleaving step (B), 1905 denotes a selector, 19
Reference numeral 07 denotes a parity row interleave circuit for realizing a first interleave step of dividing a PO row used in a conventional DVD into sector data one row at a time, and 19.
09 is a PO row insertion circuit for performing the second interleaving step (A).

The address generation circuit 1 configured as described above
The outline of the operation of 813 will be described below.

X counter 1901 and Y counter 19
02 is for reading a product code stored in a matrix.
Generate a column address and a row address, respectively. X
The counter increments sequentially from 0 to 181.
Repeat this. The Y counter is 1 for both product codes.
Increment every row, that is, every 182 × 2 bytes. The A / B flag generation circuit 1903 calculates the product code (A)
An A / B flag for distinguishing between (A) and (B) is generated. The A / B flag is a signal that toggles every row, that is, every 182 bytes. Obviously, the X counter 1901, Y counter 1902, and A / B flag generation circuit 1903 can be constituted by a counter and a simple control circuit. The upper / lower 6-row swapping circuit 1904 swaps the upper 6 rows and lower 6 rows of the sector data in order to perform the second interleaving step (B). A circuit for adding 6 and a circuit for subtracting 6 are provided.
The subtraction and the last one line are kept as they are, and the process for 13 lines is repeated. Thus, for example, when the input Y address changes by one from 0 to 12, 6, 7, 8,.
The output is 11, 0, 1, 2,... 5, 12.

The PO row insertion circuit 1909 for performing the second interleaving step (A) finds the remainder of the input Y address divided by 13, and the remainder is 6 to 11
In the case of (1), 1 is added to the Y address, and when the remainder is 12, a value obtained by subtracting 7 from the Y address is sent to the selector 1905.

When the A / B flag indicates the product code (B), the selector 1905 selects the upper / lower six-row switching circuit 1
904, and in the case of the product code (A), PO
The input from the row insertion circuit 1909 is output. The parity row interleave circuit 1906 converts a memory mapping to a row address where a product code PO parity row is stored every time a value obtained by adding 1 to a row address sent from the selector becomes a multiple of 13. 190
7 and is realized with the same configuration as the PO parity interleave circuit used in the conventional DVD.

By reading the product codes (A) and (B) stored in the RAM 1802 in accordance with the address generation circuit shown in FIG. 19, batch interleaving in which the first to third interleaving steps are batched is executed. be able to. Note that the address generation circuit in FIG. 19 is an example, and it goes without saying that various realizing means are possible according to the case where the storage form of the product code in the RAM is changed.

As described above, the first embodiment of the present invention for encoding an error correction code in the error correction method according to the eleventh embodiment.
The error correction coding circuit according to the second embodiment can realize error correction coding capable of exhibiting a strong correction capability against a burst error. Further, by performing the first to third interleaving steps and recording the data on a disk medium, not only the correction capability is improved but also when the data is recorded on a disk,
ID information can be recorded at regular intervals,
Address playback is easy. By facilitating address reproduction, for example, improvement in search performance can be realized.

Also, in the present embodiment, unlike the second and seventh embodiments, the PO row included in each physical sector is also one row at the last row of the physical sector, and the data structure of each physical sector is changed to the conventional one. Can be the same as DVD.

In the twelfth embodiment of the present invention,
Although the example in which batch interleaving is performed has been described, the first and second
Obviously, (A), second (B), and third interleaving may be performed sequentially and individually.

FIG. 20 is an external view of an optical disk according to the thirteenth embodiment of the present invention.

In FIG. 20, 2001 is an optical disk,
Reference numeral 2002 denotes encoded data recorded on a spiral or concentric track of the optical disc 2001. The coded data 2002 in the present embodiment records the error correction code of the eleventh or twelfth embodiment.

In an optical disk, data is recorded as uneven pits or light and dark dots made of a phase change material. Generally, at the time of recording, encoded data is digitally modulated by a modulation code such as 8/16 modulation and then recorded on a track of a disk. Here, the state where the modulation by the modulation code is omitted and the encoded data is recorded as it is is shown.

In the coded data of the eleventh or twelfth embodiment, the symbol in the first row and first column of the second interleaved data (A) 1701 in FIG. 17 is recorded first on the optical disc. Second interleaved data (A) 1701 and second interleaved data (B) 1702 are interleaved and recorded for each row. Reference numeral 2003 denotes ID information added to the head of each sector data, which is recorded at regular intervals every 182 × 13 bytes. Reference numeral 2004 denotes PO parity, which is recorded on the disk at regular intervals in the last row of each physical sector, one row at a time, and has the same data structure as a conventional DVD.

In the optical disk according to the thirteenth embodiment of the present invention, since the encoded data shown in the eleventh or twelfth embodiment is recorded, two product codes are interleaved and recorded. A strong correction capability can be realized for a burst error, and highly reliable error correction can be performed. Furthermore, by recording ID information at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

Further, in this embodiment, the PO rows included in each physical sector are recorded on the disk at regular intervals in the last row of each physical sector, and have the same data structure as a conventional DVD.

FIG. 21 is a flowchart showing a correction algorithm of the error correction method according to the fourteenth embodiment of the present invention. The fourteenth embodiment of the present invention discloses a method for correcting an error correction code recorded on the optical disc shown in FIG.

In FIG. 21, reference numeral 2101 denotes a third deinterleave step, 2102 denotes a second deinterleave step (B), 2103 denotes a second deinterleave step (A), 2104 denotes a first deinterleave step,
2105 is an error correction step.

Third deinterleaving step 2101
First, the reproduction data read from the disk medium is divided into two every 182 bytes on the RAM,
Each is stored in the memory in a matrix of 208 rows × 182 columns. The stored reproduction data is stored as second interleaved data (A) and second interleaved data (B), similar to 1701 and 1702 in FIG. 17 in the eleventh embodiment.

Second deinterleaving step (B) 2
As 102, the second interleaved data (B) 1702 stored in the RAM is divided into 16 rows every 13 rows, and the upper 6 rows and the lower 6 rows successive to each of the 16 rows are divided into rows. Replace with unit. As a result of this step, the data is stored in the RAM as first interleaved data (B) similar to 405 in FIG.

Second deinterleaving step (A) 2
As 103, the second interleaved data (A) 1701 stored in the RAM is divided into 16 pieces for every 13 rows, and the divided 16 PO parity rows are extracted and the 13th row is extracted as the 13th row. Move. As a result of this step, the data is stored in the RAM as first interleaved data (A) similar to 404 in FIG.

First deinterleaving step 2104
Assuming that the two first interleaved data (A) and (B) are each divided into 16 pieces every 13 rows, and each of the 16 divided pieces is extracted one by one from the bottom. Put together as PO parity. As a result of this step, the same product code (A) and product code (B) are stored in the RAM as 304 and 305 in FIG. This step is the same as the deinterleaving step of parity row interleaving in the conventional DVD when the first interleaved data (A) and (B) are viewed independently. The only difference is that you need to do it twice.

As an error correction step 2105, each of the two product codes (A) and (B) is corrected. This step is also the same as the error correction of the conventional DVD, and is different only in that it needs to be performed twice.

In the error correction method according to the fourteenth embodiment of the present invention, which performs error correction according to the above-described correction algorithm, by reproducing the encoded data shown in the eleventh or twelfth embodiment, Since the product code is recorded in an interleaved manner, it is possible to realize a strong correction capability with respect to a burst error, and to perform highly reliable error correction.

Further, by recording ID information at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

In this embodiment, the PO rows included in each physical sector are recorded on the disk at regular intervals in the last row of each physical sector, and have the same data structure as a conventional DVD.

In this embodiment, the third to first deinterleaving steps are performed as independent steps in order. However, in the direct step of storing two product codes in the memory so as to directly form two product codes from reproduced data. Needless to say, it can be configured.

FIG. 22 is a configuration diagram of an error correction circuit according to the fifteenth embodiment of the present invention. In this embodiment,
An error correction circuit for correcting an error correction code recorded on the optical disk shown in FIG. 20 is disclosed.

In FIG. 22, reference numeral 2201 denotes an entire error correction circuit; 2202, a RAM used as a working memory of the error correction circuit 2201;
Reference numeral 203 denotes a recording / reproducing control for the RAM 2202 and an internal bus
A bus / memory control circuit 2210 for controlling the output 210 is an output IF control circuit for outputting error-corrected user data, and is, for example, a handshake circuit with an MPEG decoder or an ATAPI or SCSI protocol control circuit. Further, the output IF control circuit 2204 includes an ID information deletion circuit for deleting ID information added to each sector data. Reference numeral 2205 denotes an error correction circuit for a product code (A) and a product code (B), and a PI code error correction circuit that corrects an error of a PI code obtained by adding a 10-byte PI parity to 172 bytes of data for each row. 220
8 and 16 bytes of PO for 192 bytes of data
It is composed of a PO code error correction circuit 2207 that corrects an error of the PO code added with parity for each column. 22
06 stores the reproduced data reproduced from the disk in the RAM 2
202 is an input IF control circuit stored in the RAM 22
When the reproduction data is stored in the 02, the third deinterleaving step to the first deinterleaving step shown in the fourteenth embodiment are collectively executed. Further, it performs IF control with the demodulation circuit. 2209 is an error correction circuit 220
1 is an overall control circuit that performs overall control, and is configured by a microcontroller or the like.

Incidentally, the PO code error correction circuit 2207,
Each of the error correction circuits of the PI code error correction circuit 2208 is an error correction of a Reed-Solomon code. The product codes (A) and (B) can be executed by simply using the correction circuit twice.

Hereinafter, the operation of the error correction circuit 2201 according to the fifteenth embodiment of the present invention will be described. As mentioned above,
The operation of each component of the error correction coding circuit 2201 is controlled by the general control circuit 2209.

Reproduction data 2 reproduced from a disk medium
211 is stored in the RAM 2202 via the input IF control circuit 2206 and the bus / memory control circuit 2203. When storing the input reproduction data 2211 in the RAM, the input IF control circuit 2206 generates an address of the RAM 2202 which is equivalent to executing the following three interleaving steps collectively. The address generation is performed by the address generation circuit 2213. The address generation circuit 2213 is the same as the address generation circuit 1813 of the error correction coding circuit of the twelfth embodiment shown in FIG. 19, and stores the reproduction data 2211 in the RAM 2202 according to the address of the address generation circuit 2213. Here, details of the address generation circuit 2213 are omitted.

(Third Deinterleaving Step) First, the reproduction data read from the disk medium is
It is divided into two every 182 bytes on the AM, and each is divided into 208
The data is stored in the memory in a matrix of rows × 182 columns. The stored reproduction data corresponds to 170 in FIG. 17 in the eleventh embodiment.
1 and 1702, are stored as second interleaved data (A) and second interleaved data (B).

(Second Deinterleave Step (B)) The second interleave data (B) stored in the RAM is divided into 16 pieces every 13 rows, and the divided 1
For each of the six, the top six rows followed by the bottom six
Replace rows line by line. As a result of this step, 40 in FIG.
5 as first interleaved data (B) similar to R
Stored in AM.

(Second deinterleaving step (A)) The second interleaving data (A) stored in the RAM is divided into 16 pieces every 13 rows, and the divided 1
The seventh PO parity row is extracted from the top of each of the six, and moved to the lowermost end of each of the divided 16 pieces. As a result of this step, the first
Is stored in the RAM as interleaved data (A).

(First Deinterleaving Step) Two first interleaved data (A) and (B)
Is divided into 16 pieces every 13 lines, and the divided 16
For each of them, one row is extracted from the lowest order and collected as PO parity. As a result of this step, FIG.
Are stored in the RAM as a product code (A) and a product code (B), similar to 304 and 305.

The above three deinterleaving steps are performed collectively, that is, the RAM 2 of the reproduction data 2211
By performing storage once in the RAM 202, the RAM 2202 stores
Stored as a product code (A) and a product code (B).

An error correction of each product code is performed by the product code error correction circuit 2205 on the reproduced data divided and stored in the two product codes (A) and (B). First, PI code error correction is performed by the PI code error correction circuit 2208. Since a 10-byte PI parity is added to each row, an error correction of up to 5 bytes is performed. Next, the PO code error correction is performed by the PO code error correction circuit 2207, and a 16-byte PO parity is added to each column.
Error correction of up to 8 bytes is performed. Through the above processing, error correction of one product code is performed, and error correction of the second product code is similarly performed by the product code error correction circuit 2205. In the above error correction,
It is possible to perform more reliable error correction by using known repetition correction and erasure correction.

Next, the sector data of the two product codes subjected to the error correction are read from the RAM 2202 by the output IF control circuit 2204 and sent to the MPEG decoding circuit and the host computer. At the time of transmission, the ID information added to the head of each sector data is deleted, and only the user data is transmitted to the MPEG decoding circuit or the host computer. In addition, deletion of ID information
Once the entire sector data including the ID information is stored in the RAM 2202
May be deleted after reading from
Obviously, only the user data excluding the information may be read from the RAM 2202. In reading, each sector data stored in the RAM 2202 may be deinterleaved and read in the order of sectors. Although not shown, an address generation circuit for deinterleaving and reading in the order of sectors is provided in the output IF control circuit 2.
It is obvious that the data can be constituted by a simple counter or the like, which is included in 204.

As described above, in the error correction circuit according to the fifteenth embodiment of the present invention, by reproducing the encoded data shown in the eleventh or twelfth embodiment, two product codes are interleaved. Since it is recorded, it is possible to realize a strong correction capability against a burst error, and it is possible to perform highly reliable error correction. Further, since the ID information is recorded at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized. In addition, the PO row included in each physical sector also has 1 in the last row of the physical sector.
Line by line, and the data structure of each physical sector is
Can be the same as D.

In this embodiment, the address generation circuit and the input IF control circuit for executing the first to third deinterleaving steps collectively are disclosed, but they may be performed as independent steps in order.

Hereinafter, an error correction encoding method for a disk medium according to the sixteenth embodiment of the present invention will be described.

The error correction encoding method for a disk medium according to the sixteenth embodiment differs from the first embodiment in the first and second interleaving steps. As in the first embodiment, the product code (A) 304 and the product code (B) 305 shown in FIG. 3 are generated by performing the sector data generation step, the interleaved sector data generation step, and the product code generation step. .

The description of the sector data generating step, the interleaved sector data generating step, and the product code generating step is the same as in the first embodiment, and will not be repeated.

FIG. 23 shows a first embodiment of the sixteenth embodiment of the present invention.
FIG. 3 is a configuration diagram of interleaved data (A) and (B) of FIG.

(First Interleaving Step) FIG.
In FIG. 3, reference numeral 2301 denotes sector data indicated by reference numeral 301 in FIG. 3, and reference numeral 2304 denotes first interleaved data (A) generated by the first interleaving step.
305 is first interleaved data (B).

In the product code (A) 304 and the product code (B) 305 in FIG. 3, the PO parity 303 in FIG. 3 is inserted for each sector data, that is, for every 12 rows. The insertion position is different from the first embodiment, and is inserted in the seventh row from the top of each of the 12 rows of sector data. As a result, the PO parity 2302 in FIG. 23 is obtained. In the first interleave step in this embodiment, the first interleave data (A) 23 is divided evenly into the seventh row of each sector data in the PO parity.
04 and first interleaved data (B) 2305
Generate

FIG. 24 is a configuration diagram of the first interleaved data (A) and the second interleaved data (B) of the embodiment.

(Second Interleaving Step) FIG.
23, reference numeral 2401 denotes first interleaved data (A), which is the same as 2304 shown in FIG. 2
Reference numeral 402 denotes second interleaved data (B), which is generated from the first interleaved data (B) 2305 in FIG. 23 by a second interleaving step.

In the second interleaving step, the sector data 2301 of 6 + 6 rows and the PO row of each row of the first interleaved data (B) are cyclically shifted by 6 rows in the column direction to obtain the second interleaved data (B). ) 2402 is generated. In the second interleaved data (B) 2402, each ID information 2404 includes 7
Each PO row 2406 is located on the thirteenth row from the top. In the second interleaving step,
6 for only 1 interleaved data (B) 2305
The row is cyclically shifted, but no processing is performed on the first interleaved data (A) 2304.

(Third Interleave Step) In the third interleave step, the first interleave data (A) 2401 and the second interleave data (B) 2402 shown in FIG. 24 are alternately transmitted for each row, and transmitted. In the order in which they were recorded.

First, the first row of the first interleaved data (A) 2401, the first row of the second interleaved data (B) 2402, and then the first row of the first interleaved data (A) 2401 2nd line, and so on
Send out line by line.

By performing the third interleaving step as described above, the data of sector 0 and sector 1 can be obtained.
The data of sector 2 and sector 3, and similarly, each sector data is interleaved by two sectors and recorded on the disk medium. For example, the physical sector length is set to (172 + 10).
× 13, that is, assuming a length of 13 rows, the logical sector and the physical sector do not match in sector units,
This is consistent when looking at two sectors.

At this time, ID information 2403 and 2404 are located at the head of all physical sectors. For example, when reproducing the address of a physical sector from the ID information 2403 and 2404 on a read-only disc, at the head of each sector. , And at regular intervals, so that it is easy to reproduce. Also, in the present embodiment, unlike the first and sixth embodiments, the PO row included in each physical sector is also one row at the end of the physical sector, and the data structure of each physical sector is the same as that of the conventional DVD. There is an advantage that it can be done.

As described above, in the error correction encoding method for a disk medium according to the sixteenth embodiment of the present invention, the first to third interleaving is performed on two product codes (A) and (B). By performing the steps and recording the data on the disk medium, the interleave length can be doubled, and a configuration resistant to burst errors can be realized. For example, in the conventional method of recording only one product code as it is, errors exceeding 16 lines, that is, (172)
When an error exceeding (+10) × 16 = 2912 bytes occurs, the correction becomes impossible. In this embodiment, (172+
10) Unable to correct for the first time with an error exceeding x32 = 5824 bytes.

Further, in the sixteenth embodiment of the present invention, 2
By performing the first to third interleaving steps on the two product codes (A) and (B) and recording them on a disk medium, not only improving the correction capability but also recording on a disk In addition, it is possible to record ID information at regular intervals, thereby facilitating address reproduction. By facilitating address reproduction, for example, improvement in search performance can be realized.

Furthermore, even in the event that correction is impossible, the logical sector and the physical sector match in units of two sectors, and the error caused by physical damage or the like matches the logical sector in units of two sectors. This allows uncorrectable errors to be located in relatively unified form as logical sector data. By locating the uncorrectable error in a relatively unified manner as logical sector data, for example, when an MPEG compressed image is recorded, it is possible to relatively reduce image disturbance.

[0230] Furthermore, the PO rows included in each physical sector are arranged one row at a time in the last row, similarly to the conventional DVD, and the data structure of each physical sector can be the same.

It should be noted that the first interleave step, the second interleave step, and the third interleave step are not individually executed in order, but are performed by the product code (A) 304 and the product code (B) shown in FIG. The first interleaved data (A) shown in FIG.
2401 and second interleaved data (B) 2402
It is obvious that a batch interleave step which is equivalent to sending the data alternately for each row and recording the data on the disk in the order of transmission can be easily realized.

FIG. 25 is a configuration diagram of an error correction coding circuit for a disk medium according to the seventeenth embodiment of the present invention.

This embodiment discloses an error correction coding circuit for performing the coding according to the error correction coding method shown in the sixteenth embodiment.

In FIG. 25, reference numeral 2501 denotes an entire error correction coding circuit; reference numeral 2502, a RAM used as a working memory of the semiconductor device; and reference numeral 2503, control of recording / reproduction to / from the RAM 2502 and internal buses. A bus / memory control circuit 2510 controls the input / output control circuit 2504 for inputting data to be recorded on a disk medium to an error correction circuit.
Handshake circuit with MPEG decoder, or AT
It is an API or SCSI protocol control circuit. Further, the input IF control circuit 2504 includes an ID information adding circuit including logical or physical address information of data to be recorded. Reference numeral 2511 denotes a product code encoding circuit, which includes a PI code encoding circuit 2508 for adding a 10-byte PI parity to 172-byte data for each row, and a 16-byte PO parity for a 192-byte data. It comprises a PO code encoding circuit 2507 added to each column. Reference numeral 2506 denotes an output IF control for collectively executing the first to third interleaving steps when sending the product code (A) 304 and the product code (B) 305 stored in the RAM 2502 to the modulation circuit. It is a circuit and also performs IF control with the modulation circuit. Reference numeral 2509 denotes an overall control circuit for controlling the entire error correction encoding circuit 2501, which is composed of a microcontroller or the like, and which controls the output IF control 2501.
Only Example 6 is Example 2, Example 7, and Example 1 of the present invention.
Different from 2.

Hereinafter, the operation of the error correction circuit 2501 according to the seventeenth embodiment of the present invention will be described. As mentioned above,
The operation of each component of the error correction encoding circuit 2501 is controlled by the overall control circuit 2509.

The user data 2511 sent from the host microcomputer or the MPEG encoder or the like
The data is stored in the RAM 2502 via the F control circuit 2504 and the bus / memory control circuit 2503. When storing,
The user data 2511 is divided into sectors, and ID information 202 is added to the head of each sector. The sector data including the ID information is composed of 172 × 12 = 2064 bytes, and the 32 sector data is divided into two sections alternately in the sector order, and each is divided into 16 sector data as interleaved sector data. ,
The data is stored in two areas of the RAM 2502 in a matrix of 192 rows × 172 columns. In the input IF control circuit 2504,
For this purpose, an address generation circuit (not shown) for the RAM 2502 is provided. Obviously, the address generation circuit can be easily constituted by a counter, a simple control circuit, and the like.

For the stored interleaved sector data (A) and (B),
The I encoding is performed by the PI encoding circuit 2508, and a 10-byte PI parity is added to each row.
Next, PO encoding is performed by the PO encoding circuit 2507, and a 16-byte PO parity is added to each column. By the above processing, one product code is generated, and the second product code is similarly processed by the product code encoding circuit 250.
5 generated. The generated product codes (A) and (B) are stored in the RAM 2502 in a matrix as shown in FIG.

The two product codes are then output to the output IF control circuit 2506 according to the recording order on the disk.
The data is read from M2502, sent to the modulation circuit, and recorded on the disk. The output IF control circuit 2506 executes reading according to the address of the RAM 2502 generated by the address generation circuit 2513.

FIG. 26 is a more detailed configuration diagram of the address generation circuit 2513. 26, reference numeral 2601 denotes an X counter for generating a column address; 2602, a Y counter for generating a row address; 2603, an A / B flag generation circuit for distinguishing between product codes (A) and (B);
4 is a 6-row cyclic shift circuit for cyclically shifting a PO row of each row by 6 rows in the column direction, 2605 is a selector, and 2607 is a parity used in a conventional DVD. A parity row interleave circuit for realizing a first interleave step similar to a row interleave circuit for dividing a PO row into sector data one row at a time.
PO rows are inserted one by one next to two rows of sector data, whereas the parity row interleave circuit 2 of this embodiment is used.
In step 606, PO lines are inserted one by one in the seventh line of each of the 12 lines of sector data. An outline of the operation of the address generation circuit 2513 configured as described above will be described below.

X counter 2601 and Y counter 26
02 is for reading a product code stored in a matrix.
Generate a column address and a row address, respectively. X
The counter increments sequentially from 0 to 181.
Repeat this. The Y counter is 1 for both product codes.
Increment every row, that is, every 182 × 2 bytes. The A / B flag generation circuit 2603 uses the product code (A)
An A / B flag for distinguishing between (A) and (B) is generated. The A / B flag is a signal that toggles every row, that is, every 182 bytes. Obviously, the X counter 2601, Y counter 2602, and A / B flag generation circuit 2603 can be constituted by a counter and a simple control circuit. The 6-row shift circuit 2604 stores the sector data and P
In order to cyclically shift the O row by six rows in the column direction, for example, the following operation is performed on the input Y address, and the output Y ′ is transmitted.

The quotient and remainder are obtained by dividing the input Y address by 13, the remainder is added by 6, and this is modulo-operated by 13. The result of the modulo operation and the quotient × 13 are added and sent to the selector. The following operation is shown by the expression.

Y ′ = “Y / 13” × 13 + ((Ymod
13) +6) mod13 Here, “x” is a maximum integer equal to or less than x.

The selector 2605 operates only when the A / B flag indicates the product code (B).
The input from 604 is output, and in the case of the product code (A), the Y address is output as it is. The parity row interleave circuit 2606 obtains a remainder obtained by dividing the row address sent from the selector by 13, and every time the remainder becomes 6, a PO address for converting the memory mapping into a row address in which a PO parity row of a product code is stored. A conversion circuit 2607 is provided, and the configuration is realized by a slight modification of the PO parity interleave circuit used in the conventional DVD.

By reading the product codes (A) and (B) stored in RAM 2502 in accordance with the address generation circuit shown in FIG. 26, batch interleaving in which the first to third interleaving steps are batched is executed. be able to. Note that the address generation circuit in FIG. 26 is an example, and it goes without saying that various realizing means are possible according to the case where the storage form of the product code in the RAM is changed.

As described above, the first embodiment of the present invention for encoding an error correction code in the error correction method of the sixteenth embodiment.
The error correction coding circuit according to the seventh embodiment can realize error correction coding capable of exhibiting a strong correction capability against burst errors. Further, by performing the first to third interleaving steps and recording the data on a disk medium, not only the correction capability is improved but also when the data is recorded on a disk,
ID information can be recorded at regular intervals,
Address playback is easy. By facilitating address reproduction, for example, improvement in search performance can be realized.

Also, in this embodiment, unlike the second and seventh embodiments, the PO row included in each physical sector is also one row at the last row of the physical sector, and the data structure of each physical sector is changed to the conventional one. Can be the same as DVD.

Incidentally, in the seventeenth embodiment of the present invention,
Although the example of performing the batch interleave has been described, the first, second,
Obviously, the third interleave and the third interleave may be performed sequentially and individually.

FIG. 27 is an external view of an optical disk according to the eighteenth embodiment of the present invention.

In FIG. 27, reference numeral 2701 denotes an optical disk,
Reference numeral 2702 denotes encoded data recorded on spiral or concentric tracks of the optical disk 2701. The coded data 2702 in this embodiment records the error correction code of the sixteenth or seventeenth embodiment.

In an optical disk, data is recorded as uneven pits or light and dark dots made of a phase change material or the like. Generally, at the time of recording, encoded data is digitally modulated by a modulation code such as 8/16 modulation and then recorded on a track of a disk. Here, the state where the modulation by the modulation code is omitted and the encoded data is recorded as it is is shown.

In the coded data of the sixteenth or seventeenth embodiment, the symbol of the first row and first column of the first interleaved data (A) 2401 in FIG. 24 is recorded first on the optical disc. First interleaved data (A) 2401 and second interleaved data (B) 2402 are interleaved and recorded for each row. Reference numeral 2703 denotes ID information added to the head of each sector data, which is recorded at regular intervals every 182 × 13 bytes. Reference numeral 2704 denotes a PO parity, which is recorded on the disk at regular intervals in the last row of each physical sector, one row at a time, and has the same data structure as a conventional DVD.

In the optical disk according to the eighteenth embodiment of the present invention, since the coded data shown in the sixteenth or seventeenth embodiment is recorded, two product codes are interleaved and recorded. A strong correction capability can be realized for a burst error, and highly reliable error correction can be performed. Furthermore, by recording ID information at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

In the present embodiment, the PO rows included in each physical sector are recorded on the disk at regular intervals in the last row of each physical sector, and have the same data structure as a conventional DVD.

The optical disc of this embodiment has the same configuration as the optical disc of the thirteenth embodiment.

FIG. 28 is a flowchart showing a correction algorithm of the error correction method according to the nineteenth embodiment of the present invention. The nineteenth embodiment of the present invention discloses a method for correcting an error correction code recorded on the optical disc shown in FIG.

In FIG. 28, reference numeral 2801 denotes a third deinterleave step, 2802 denotes a second deinterleave step, and 2803 denotes a first deinterleave step.
804 is an error correction step.

Third Deinterleaving Step 1801
First, the reproduction data read from the disk medium is divided into two every 182 bytes on the RAM,
Each is stored in the memory in a matrix of 208 rows × 182 columns. The stored reproduction data is stored as first interleaved data (A) and second interleaved data (B), similar to 2401 and 2402 in FIG. 24 in the sixteenth embodiment.

Second deinterleaving step 2802
As a result, the second interleaved data (B) stored in the RAM is divided into 16 pieces every 13 rows, and the divided 1
For each of the six, the six rows are cyclically permutated in the column direction.
As a result of this step, the data is stored in the RAM as first interleaved data (A) and first interleaved data (B), similar to 2304 and 2305 in FIG.
In this step, the first interleaved data (A) does not change.

First deinterleaving step 1503
As a result, the two pieces of first interleaved data (A) and (B) are divided into 16 pieces every 13 rows, and each of the 16 pieces is divided into 1 pieces from the 7th row from the top.
Each row is extracted and summarized as PO parity. As a result of this step, the same product code (A) and product code (B) are stored in the RAM as 304 and 305 in FIG. In this step, when the first interleaved data (A) and (B) are viewed independently, the position where the PO row is originally stored is different from the deinterleaving step of the parity row interleaving in the conventional DVD. 2
You also need to do it differently.

Error Correction Step 2804 Each of the two product codes (A) and (B) is corrected. This step is the same as the conventional DVD error correction.
The only difference is what you need to do.

In the error correction method according to the nineteenth embodiment of the present invention for performing error correction according to the above-described correction algorithm, by reproducing the encoded data shown in the sixteenth or seventeenth embodiment, two Since the product code is recorded in an interleaved manner, it is possible to realize a strong correction capability with respect to a burst error, and to perform highly reliable error correction.

Further, by recording ID information at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized.

In this embodiment, the PO rows included in each physical sector are recorded on the disk at regular intervals in the last row of each physical sector, and have the same data structure as a conventional DVD.

In the present embodiment, the third to first deinterleaving steps are performed as independent steps in order. However, in the direct step of storing two product codes in the memory so as to directly form two product codes from reproduced data. Needless to say, it can be configured.

FIG. 29 is a configuration diagram of the error correction circuit according to the twentieth embodiment of the present invention. In this embodiment,
An error correction circuit for correcting an error correction code recorded on the optical disk shown in FIG. 27 is disclosed.

In FIG. 29, reference numeral 2901 denotes an entire error correction circuit, 2902 denotes a semiconductor memory, which is a RAM used as a working memory of the error correction circuit 2901;
Reference numeral 903 denotes recording / reproduction control to the RAM 2902 and the internal bus 2
A bus / memory control circuit 910 controls the output IF control circuit 2904 for outputting error-corrected user data. For example, it is a handshake circuit with an MPEG decoder, or an ATAPI or SCSI protocol control circuit. Further, the output IF control circuit 2904 includes an ID information deletion circuit for deleting ID information added to each sector data. Reference numeral 2905 denotes an error correction circuit for the product code (A) and the product code (B). The PI code error correction circuit corrects an error of a PI code obtained by adding a 10-byte PI parity to 172-byte data for each row. 290
8 and 16 bytes of PO for 192 bytes of data
It is composed of a PO code error correction circuit 2907 which corrects an error of the PO code added with parity for each column. 29
06 stores the reproduced data reproduced from the disk in the RAM 2
902 is an input IF control circuit to be stored in the RAM 29
When the reproduction data is stored in 02, the third deinterleaving step to the first deinterleaving step shown in the nineteenth embodiment are collectively executed. Further, it performs IF control with the demodulation circuit. 2909 is an error correction circuit 290
1 is an overall control circuit that performs overall control, and is configured by a microcontroller or the like.

Incidentally, the PO code error correction circuit 2907,
And all error correction circuits of the PI code error correction circuit 2908 are error correction of Reed-Solomon code, and the error correction itself includes a known Reed-Solomon error correction circuit of DVD including an error correction as a product code. The product codes (A) and (B) can be executed by simply using the correction circuit twice.

The operation of the error correction circuit 2901 according to the fifth embodiment of the present invention will be described below. As described above, the operation of each component of the error correction encoding circuit 2901 is controlled by the overall control circuit 2909.

Reproduced data 2 reproduced from a disk medium
911 is stored in the RAM 2902 via the input IF control circuit 2906 and the bus / memory control circuit 2903. When the input reproduction data 2911 is stored in the RAM, the input IF control circuit 2906 generates an address of the RAM 2902 which is equivalent to executing the following three interleaving steps collectively. Address generation is performed by an address generation circuit 2913. The address generation circuit 2913 is the same as the address generation circuit 2513 of the error correction encoding circuit of the seventeenth embodiment shown in FIG. 25, and stores the reproduction data 2911 in the RAM 2902 according to the address of the address generation circuit 2913. Here, the details of the address generation circuit 2913 are omitted.

(Third Deinterleaving Step) First, the reproduction data read from the disk medium is
It is divided into two every 182 bytes on the AM, and each is divided into 208
The data is stored in the memory in a matrix of rows × 182 columns. The stored reproduction data corresponds to 240 in FIG. 24 in the sixteenth embodiment.
1 and 2402, are stored as first interleaved data (A) and second interleaved data (B).

(Second Deinterleaving Step) RA
The second interleaved data (B) stored in M
It is divided into 16 every three rows, and each of the divided 16 pieces is cyclically shifted in the column direction in row units. As a result of this step, the data is stored in the RAM as first interleaved data (A) and first interleaved data (B), similar to 2304 and 2305 in FIG. In this step, the first interleaved data (A) does not change.

(First Deinterleaving Step) Two first interleaved data (A) and (B)
Is divided into 16 pieces every 13 lines, and the divided 16
For each of them, one row is extracted from the seventh row from the top and collected as PO parity. As a result of this step, a product code (A) similar to 304 and 305 in FIG.
And the product code (B) are stored in the RAM.

The above three deinterleaving steps are performed collectively, that is, the reproduction data 2911 RAM2
By performing storage once in the RAM 902, the RAM 2902 stores
Stored as a product code (A) and a product code (B).

Error correction of each product code is performed by the product code error correction circuit 2905 on the reproduced data divided and stored in the two product codes (A) and (B). First, PI code error correction is performed by the PI code error correction circuit 2208. Since a 10-byte PI parity is added to each row, an error correction of up to 5 bytes is performed. Next, the PO code error correction is performed by the PO code error correction circuit 2907, and a 16-byte PO parity is added to each column.
Error correction of up to 8 bytes is performed. Through the above processing, error correction of one product code is performed, and error correction of the second product code is similarly performed by the product code error correction circuit 2905.

In the above error correction, more reliable error correction can be performed by using known repetition correction and erasure correction.

Next, the sector data of the two product codes subjected to the error correction are read from the RAM 2902 by the output IF control circuit 2904 and sent to the MPEG decoding circuit and the host computer. At the time of transmission, the ID information added to the head of each sector data is deleted, and only the user data is transmitted to the MPEG decoding circuit or the host computer. In addition, deletion of ID information
Once the entire sector data including ID information is stored in RAM 2902
May be deleted after reading from
Obviously, only the user data excluding the information may be read from the RAM 2902. In reading, each sector data stored in the RAM 2902 may be deinterleaved and read in the order of sectors. Although not shown, an address generation circuit for deinterleaving and reading in the order of sectors is provided in the output IF control circuit 2.
904, and can be constituted by a simple counter or the like.

As described above, in the error correction circuit according to the twentieth embodiment of the present invention, by reproducing the encoded data shown in the sixteenth or seventeenth embodiment, two product codes are interleaved. Since it is recorded, it is possible to realize a strong correction capability against a burst error, and it is possible to perform highly reliable error correction. Further, since the ID information is recorded at regular intervals, address reproduction including the control circuit is facilitated. By facilitating address reproduction, for example, improvement in search performance can be realized. In addition, the PO row included in each physical sector also has 1 in the last row of the physical sector.
Line by line, and the data structure of each physical sector is
Can be the same as D.

In this embodiment, the address generation circuit and the input IF control circuit for executing the first to third deinterleaving steps collectively are disclosed, but they may be performed as independent steps in order.

As described above, the error correction encoding method for the disk medium, the optical disk,
The error correction method, the error correction coding circuit, and the error correction circuit have high compatibility with the conventional product code, that is, there are few changes from the conventional method, and two product codes are interleaved and recorded. Strong correction capability against errors can be realized. Further, the address can be recorded periodically for each physical sector, and the address reproduction including the control circuit is facilitated.

[0280]

As described above, the present invention is compatible with the conventional product code, that is, the change from the conventional method is small, the address information and the like included in the recording data can be recorded in the same manner as the conventional one, and the length is large. Even if a large burst error occurs, an error correction coding method, an error correction coding circuit, an optical disk, an error correction method, and an error correction circuit of a disk medium that can be corrected with high reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of sector data in an error correction encoding method for a disk medium according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of interleaved sector data (A) and (B) according to the first embodiment.

FIG. 3 is a configuration diagram of a product code (A) and a product code (B) according to the first embodiment.

FIG. 4 is a configuration diagram of first interleaved data (A) and (B) according to the first embodiment.

FIG. 5 is a configuration diagram of first interleaved data (A) and second interleaved data (B) according to the first embodiment.

FIG. 6 is a configuration diagram of an error correction coding circuit for a disk medium according to a second embodiment of the present invention.

FIG. 7 shows an address generation circuit 613 according to the second embodiment.
3 is a more detailed configuration diagram of FIG.

FIG. 8 is an outline view of an optical disc according to a third embodiment of the present invention.

FIG. 9 is a flowchart illustrating a correction algorithm of an error correction method according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of an error correction circuit according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of first interleaved data (A) and second interleaved data (B) according to a sixth embodiment of the present invention.

FIG. 12 is a configuration diagram of an error correction encoding circuit for a disk medium according to a seventh embodiment of the present invention.

FIG. 13 shows an address generation circuit 12 according to a seventh embodiment.
13 is a more detailed configuration diagram of FIG.

FIG. 14 is an outline view of an optical disc according to an eighth embodiment of the present invention.

FIG. 15 is a flowchart showing a correction algorithm of an error correction method according to a ninth embodiment of the present invention.

FIG. 16 is a configuration diagram of an error correction circuit according to a tenth embodiment of the present invention.

FIG. 17 is a configuration diagram of second interleaved data (A) and second interleaved data (B) according to an eleventh embodiment of the present invention.

FIG. 18 is a configuration diagram of an error correction encoding circuit for a disk medium according to a twelfth embodiment of the present invention.

FIG. 19 is an address generation circuit 1 according to a twelfth embodiment.
813 is a more detailed configuration diagram of FIG.

FIG. 20 is an outline drawing of an optical disc according to a thirteenth embodiment of the present invention.

FIG. 21 is a flowchart illustrating a correction algorithm of an error correction method according to a fourteenth embodiment of the present invention.

FIG. 22 is a configuration diagram of an error correction circuit according to a fifteenth embodiment of the present invention.

FIG. 23 is a configuration diagram of first interleaved data (A) and (B) according to a sixteenth embodiment of the present invention.

FIG. 24 is a configuration diagram of first interleaved data (A) and second interleaved data (B) according to a sixteenth embodiment.

FIG. 25 is a configuration diagram of an error correction coding circuit for a disk medium according to a seventeenth embodiment of the present invention.

FIG. 26 is an address generation circuit 2 according to a seventeenth embodiment.
FIG. 513 is a more detailed configuration diagram of FIG.

FIG. 27 is an outline view of an optical disc according to an eighteenth embodiment of the present invention.

FIG. 28 is a flowchart showing a correction algorithm of an error correction method according to a nineteenth embodiment of the present invention.

FIG. 29 is a configuration diagram of an error correction circuit according to a twentieth embodiment of the present invention.

[Explanation of symbols]

 103 Sector data 203 Interleaved sector data (A) 204 Interleaved sector data (B) 304 Product code (A) 305 Product code (B) 404 First interleaved data (A) 405 First interleaved data (B) 501 First Interleave data (A) 502 Second interleave data (B) 1101 First interleave data (A) 1102 Second interleave data (B) 1701 Second interleave data (A) 1702 Second interleave data (B) 2304) First interleaved data (A) 2305 First interleaved data (B) 2401 First interleaved data (A) 2402 Second interleaved data (B)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) 27 H03M 13/27 13/29 13/29 (72) Inventor Yuji Takagi 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Makoto Usui 1006 Okadoma Kadoma Kadoma City, Osaka Matsushita Electric Industrial (72) Inventor Hiroyuki Yabuno 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Atsushi Nakamura 1006 Odaka Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Ryoji Kobayashi Omon Gate, Kadoma City, Osaka Prefecture 1006 Matsushita Electric Industrial Co., Ltd. (72) Inventor Naohiro Kimura 1006 Okadoma, Kadoma-shi, Osaka Prefecture 1006 Matsushita Electric Industrial Co., Ltd. (72) Inventor Shigeki Taira 1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside the System Development Laboratory (72) Inventor Osamu Kawamae 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Digital Media Development Division, Hitachi, Ltd. (72) Inventor Taku Hoshizawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Nodan Chosaku 70, Yanagicho, Kochi-ku, Kawasaki-shi, Kanagawa Prefecture In-house Toshiba Yanagicho Works Co., Ltd. (72) Hiroshi Kashiwara 70, Yanagicho, Sachi-ku, Kawasaki-shi, Kanagawa Company Toshiba Yanagimachi Office F-term (reference) 5B001 AA02 AC05 AD04 AE04 5D044 AB01 BC03 CC06 DE61 DE68 DE81 GK14 5J065 AA03 AB02 AB05 AC03 AD02 AE06 AF02 AG06 AH09

Claims (44)

[Claims] 1. An error correction encoding method for a disk medium, wherein two product codes are interleaved in an order based on a predetermined interleave rule and transmitted and recorded on the disk medium. A sector data generating step of generating (R × C) bytes of sector data by adding ID information of the user data to the beginning of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Step; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) A product code generating step of generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively written in P of the PO row.
A first interleaving step of inserting the O parity into the S pieces of sector data row by row in the S pieces of data to generate first interleaved data (A) and first interleaved data (B); A second interleaving step of generating the second interleaved data (B) by replacing the upper R / 2 rows of the S pieces of sector data of the interleaved data (B) and the succeeding R / 2 rows on a row basis; The first interleaved data (A) and the second interleaved data (B) are alternately transmitted in units of rows, and the data of each transmitted (R + 1) line is recorded on a disk medium as physical sector data in the order of transmission. 3. An error correction coding method for a disk medium, comprising: 2. A first interleaving step, a second interleaving step, and a third interleaving step are collectively interleaving steps executed collectively when two product codes are transmitted to a disk medium. 2. The method according to claim 1, wherein the error correction encoding is performed. 3. R = 12, C = 172, S = PO = 1
6. The error correction encoding method for a disk medium according to claim 1, wherein PI = 10. 4. An error correction encoding circuit for a disk medium for interleaving two product codes in an order based on a predetermined interleaving rule and transmitting the product code, and recording the user data in a predetermined sector length. A sector data generating means for generating (R × C) bytes of sector data by adding ID information of the user data to the head of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Means; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) a product code generation means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively converted into P
A first interleaving means for generating first interleaved data (A) and first interleaved data (B) by inserting O parity into the S sector data one row at a time for each row; Second interleaving means for generating second interleaved data (B) by replacing the upper R / 2 rows and subsequent R / 2 rows of each of the S sector data of the interleaved data (B) in row units; The first interleaved data (A) and the second interleaved data (B) are alternately transmitted in units of rows, and the data of each transmitted (R + 1) line is recorded on a disk medium as physical sector data in the order of transmission. 3. An error correction coding circuit for a disk medium, comprising: 5. The first interleaving means, the second interleaving means, and the third interleaving means,
5. The error correction encoding circuit for a disk medium according to claim 4, further comprising batch interleaving means for executing the product code stored in the memory at a time when the product code is transmitted. 6. R = 12, C = 172, S = PO = 1
6. The error correction encoding circuit for a disk medium according to claim 4, wherein PI = 10. 7. The method according to claim 1, wherein the error correction encoding method is performed on a disk medium.
7. A disk medium on which physical sector data has been recorded by the error correction coding circuit for a disk medium according to any one of the above items. 8. An error correction method using an error correction code based on physical sector data recorded on a disk medium according to claim 7, wherein reproduced data read from the disk medium is stored in a memory in (C + PI) bytes. Each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate first interleaved data (A) and second interleaved data (B). Deinterleaving step; dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
A second deinterleaving step of generating the first interleaved data (B) by replacing the upper R / 2 rows and the succeeding R / 2 rows on a row-by-row basis; Each of the interleaved data (B) is divided into S pieces, and one row is extracted from each of the divided lowermost rows, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving step of generating two product codes that are (+ PO) rows × (C + PI) columns; and an error correcting step of performing error correction on the two product codes for each product code. An error correction method for a disk medium, comprising: 9. The third deinterleaving step, the second
9. The disk according to claim 8, wherein the deinterleaving step and the first deinterleaving step comprise a batch deinterleaving step which is executed collectively when the product code is stored in the memory. Error correction method for media. 10. An error correction circuit using an error correction code based on physical sector data recorded on a disk medium according to claim 7, wherein the reproduction data read from the disk medium is stored in a memory as (C + PI) bytes. Each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate first interleaved data (A) and second interleaved data (B). Deinterleaving means; dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
Second deinterleaving means for generating the first interleaved data (B) by replacing the upper R / 2 rows and the succeeding R / 2 rows on a row-by-row basis; Each of the interleaved data (B) is divided into S pieces, and one row is extracted from each of the divided lowermost rows, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving means for generating two product codes of (+ PO) rows × (C + PI) columns, and an error correcting means for performing error correction for each of the two product codes for the two product codes. An error correction circuit for a disk medium, comprising: 11. The third deinterleaving means, the second deinterleaving means, and the first deinterleaving means are constituted by batch deinterleaving means for executing collectively when a product code is stored in a memory. The error correction circuit for a disk medium according to claim 10, wherein: 12. A disk medium error correction encoding method for interleaving two product codes in an order based on a predetermined interleaving rule and transmitting the resultant data, and recording the user data in a predetermined sector length. A sector data generating step of generating (R × C) bytes of sector data by adding ID information of the user data to the beginning of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Step; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) A product code generating step of generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively written in P of the PO row.
A first interleaving step of inserting the O parity into the S pieces of sector data row by row in the S pieces of data to generate first interleaved data (A) and first interleaved data (B); The interleaved data (B) is divided into S areas in which the sector data and PO parity of R rows are composed of one row, and each of the divided areas is divided into rows in the column direction in row units.
A second interleave step of generating a second interleave data (B) by performing a cyclic shift of / 2 rows; and alternately applying the first interleave data (A) and the second interleave data (B) in row units. And a third interleaving step of recording the transmitted data for each (R + 1) row as physical sector data on the disk medium in the order of transmission, and a third interleaving step for the disk medium. 13. The first interleaving step, the second
The interleave step and the third interleave step comprise a batch interleave step which is executed collectively when two product codes are transmitted to a disk medium. Error correction encoding method for disk media. 14. R = 12, C = 172, S = PO = 1
14. The error correction encoding method for a disk medium according to claim 12, wherein PI = 10. 15. An error correction encoding circuit for a disk medium for interleaving two product codes in an order based on a predetermined interleave rule and transmitting the interleaved data, and recording the user data on a predetermined sector length. A sector data generating means for generating (R × C) bytes of sector data by adding ID information of the user data to the head of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Means; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) a product code generation means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively stored in the P row of the PO row.
A first interleaving means for generating first interleaved data (A) and first interleaved data (B) by inserting O parity into the S sector data one row at a time for each row; The interleaved data (B) is divided into S areas in which the sector data and PO parity of R rows are composed of one row, and each of the divided areas is divided into rows in the column direction in row units.
A second interleave means for generating a second interleave data (B) by performing a cyclic shift of / 2 rows; and alternately applying the first interleave data (A) and the second interleave data (B) in row units. And a third interleaving means for recording the transmitted data for each (R + 1) row as physical sector data on the disk medium in the order of transmission, and an error correction coding circuit for the disk medium. 16. The first interleave means, the second interleave means, and the third interleave means are collective interleave means for executing the product code stored in the memory at a time when the product code is transmitted. 16. The error correction coding circuit for a disk medium according to claim 15, wherein the circuit is configured. 17. R = 12, C = 172, S = PO = 1
17. The error correction coding circuit for a disk medium according to claim 15, wherein PI = 10. 18. A physical medium according to the disk medium error correction encoding method according to any one of claims 12 to 14, or the disk medium error correction encoding circuit according to any one of claims 15 to 17. A disk medium on which sector data is recorded. 19. An error correction method using an error correction code based on physical sector data recorded on a disk medium according to claim 18, wherein reproduced data read from the disk medium is stored in a memory in (C + PI) bytes. Each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate first interleaved data (A) and second interleaved data (B). Deinterleaving step; dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
A second deinterleaving step of generating a first interleaved data (B) by performing a cyclic shift of R / 2 rows in the column direction on a row basis; a first interleaved data (A) and a first interleaved data (B); ) Is divided into S parts, and one line is extracted from each of the divided lowermost lines, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving step of generating two product codes that are (+ PO) rows × (C + PI) columns; and an error correcting step of performing error correction on the two product codes for each product code. An error correction method for a disk medium, comprising: 20. A method according to claim 19, wherein the third deinterleaving step, the second deinterleaving step, and the first deinterleaving step comprise:
20. The error correction method for a disk medium according to claim 19, comprising a batch deinterleave step executed collectively. 21. An error correction circuit using an error correction code based on physical sector data recorded on a disk medium according to claim 18, wherein the reproduction data read from the disk medium is stored in a memory as (C + PI) bytes. Each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate first interleaved data (A) and second interleaved data (B). Deinterleaving means; dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
Second deinterleaving means for generating a first interleaved data (B) by performing a cyclic shift of R / 2 rows on a row-by-row basis in the column direction; and the first interleaved data (A) and the first interleaved data (B). ) Is divided into S parts, and one line is extracted from each of the divided lowermost lines, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving means for generating two product codes of (+ PO) rows × (C + PI) columns, and an error correcting means for performing error correction for each of the two product codes for the two product codes. An error correction circuit for a disk medium, comprising: 22. The third deinterleaving means, the second deinterleaving means, and the first deinterleaving means are constituted by batch deinterleaving means for executing collectively when storing a product code in a memory. 22. The error correction circuit for a disk medium according to claim 21, wherein the error correction is performed. 23. A disk medium error correction encoding method for interleaving two product codes in an order based on a predetermined interleave rule, transmitting the product code, and recording the user data in a predetermined sector length. A sector data generating step of generating (R × C) bytes of sector data by adding ID information of the user data to the beginning of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Step; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) A product code generating step of generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively written in P of the PO row.
A first interleaving step of inserting the O parity into the S pieces of sector data row by row in the S pieces of data to generate first interleaved data (A) and first interleaved data (B); A second interleaving step (B) for generating second interleaved data (B) by replacing the upper R / 2 rows and the subsequent R / 2 rows of each of the S sector data of the interleaved data (B) in units of rows. ), And divides the first interleaved data (A) into S areas each having R rows of sector data and one PO parity, and divides each PO parity row in each of the divided areas into A second interleaving step (A) for generating second interleaved data (A) by inserting the second interleaved data (A) from above the R / 2 line from the top of the area, and the second interleaved data (A) and the second Inn And a third interleaving step of alternately sending out (B + 1) data on a row-by-row basis and recording the sent data for each (R + 1) row as physical sector data on the disc in the order in which the data is sent out. Error correction coding method. 24. The first interleaving step, the second
The interleave step (A), the second interleave step (B), and the third interleave step comprise a batch interleave step executed collectively when two product codes are transmitted to a disk medium. 24. The method according to claim 23, wherein: 25. R = 12, C = 172, S = PO = 1
26. The method according to claim 23, wherein PI = 10. 26. An error correction encoding circuit for a disk medium for interleaving two product codes in an order based on a predetermined interleave rule and transmitting the product code, and recording the user data in a predetermined sector length. A sector data generating means for generating (R × C) bytes of sector data by adding ID information of the user data to the head of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Means; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction is used.
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) a product code generation means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively converted into P
A first interleaving means for generating first interleaved data (A) and first interleaved data (B) by inserting O parity into the S sector data one row at a time for each row; Second interleaving means (B) for generating second interleaved data (B) by replacing upper R / 2 rows and lower R / 2 rows of each of the S sector data of interleaved data (B) in row units And divides the first interleaved data (A) into S areas each including R rows of sector data and one PO parity, and divides each PO parity row of each divided area into each area. A second interleaving means (A) for generating second interleaved data (A) by inserting the next interleaved data after the R / 2 line from above, and the second interleaved data (A) and the second interleaved data data( ) Are alternately transmitted in row units, and third interleaving means for recording the transmitted data for each (R + 1) row as physical sector data on the disk medium in the transmission order is provided. Circuit. 27. A first interleaving means, a second interleaving means (A), a second interleaving means (B), and a third interleaving means send out the product code stored in a memory. 27. The error correction encoding circuit for a disk medium according to claim 26, wherein the error correcting encoding circuit is constituted by a batch interleave means for executing the batch collectively. 28. R = 12, C = 172, S = PO = 1
6. PI = 10, wherein PI = 10.
9. The error correction encoding circuit for a disk medium according to any one of 8. 29. A physical medium according to the error correction encoding method for a disk medium according to any one of claims 23 to 25, or by the error correction encoding circuit for a disk medium according to any one of claims 26 to 28. A disk medium on which sector data is recorded. 30. An error correction method using an error correction code based on physical sector data recorded on a disk medium according to claim 29, wherein reproduced data read from the disk medium is stored in a memory (C + PI). For each byte, each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate a second interleave data (A) and a second interleave data (B) Deinterleaving step; and dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
A second deinterleaving step (B) for generating the first interleaved data (B) by replacing the upper R / 2 rows and the succeeding R / 2 rows on a row-by-row basis, and the second interleaved data (A ) Is divided into S pieces by (R + 1) rows, the PO parity of the ((R / 2) +1) -th row is extracted from each of the S pieces, and the PO parity of each of the divided S areas is extracted. A second deinterleaving step (A) for generating the first interleaved data (A) by moving to the lower end; and S pieces each of the first interleaved data (A) and the first interleaved data (B) , And one line is extracted from each of the divided lowermost lines, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving step of generating two product codes that are (+ PO) rows × (C + PI) columns; and an error correcting step of performing error correction on the two product codes for each product code. An error correction method for a disk medium, comprising: 31. The third deinterleaving step, the second deinterleaving step (A), the second deinterleaving step (B), and the first deinterleaving step are performed when a product code is stored in a memory. 31. The error correction method for a disk medium according to claim 30, comprising a batch deinterleaving step executed collectively. 32. An error correction circuit using an error correction code based on physical sector data recorded on a disk medium according to claim 29, wherein reproduced data read from the disk medium is stored in a memory as (C + PI) bytes For each of them, each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns, and third interleaved data (A) and second interleaved data (B) are generated. Deinterleaving means; dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
Second deinterleaving means (B) for generating the first interleaved data (B) by replacing the upper R / 2 rows and the subsequent R / 2 rows on a row-by-row basis, and the second interleaved data (A ) Is divided into S pieces by (R + 1) rows, the PO parity of the ((R / 2) +1) -th row is extracted from each of the S pieces, and the PO parity of each of the divided S areas is extracted. Second deinterleaving means (A) for moving to the lower end to generate first interleaved data (A); and S pieces of each of the first interleaved data (A) and the first interleaved data (B) , And one line is extracted from each of the divided lowermost lines, and PO
By combining them as parity, each becomes ((S × R)
A first deinterleaving means for generating two product codes of (+ PO) rows × (C + PI) columns, and an error correcting means for performing error correction for each of the two product codes for the two product codes. An error correction circuit for a disk medium, comprising: 33. The third deinterleaving means, the second deinterleaving means (A), the second deinterleaving means (B), and the first deinterleaving means store a product code in a memory. 33. The error correction circuit for a disk medium according to claim 32, wherein the error correction circuit is constituted by batch deinterleaving means for executing the batch collectively. 34. A disk medium error correction encoding method for interleaving two product codes in an order based on a predetermined interleave rule and transmitting the product code, and recording the user data in a predetermined sector length. A sector data generating step of generating (R × C) bytes of sector data by adding ID information of the user data to the beginning of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Step; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) A product code generating step of generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively written in P of the PO row.
O-parity is inserted row by row in the ((R / 2) +1)) row from the top of each of the S sector data for each row, and the first interleaved data (A) and the first interleaved data (B ) Is generated, and the first interleaved data (B) is divided into S areas in which R rows of sector data and PO parity are composed of one row, and each divided area is divided into S areas. R for each row in the column direction
A second interleave step of generating a second interleave data (B) by performing a cyclic shift of / 2 rows; and alternately applying the first interleave data (A) and the second interleave data (B) in row units. And a third interleaving step of recording the transmitted data for each (R + 1) row as physical sector data on the disk medium in the order of transmission, and a third interleaving step. 35. The first interleaving step, the second
35. The interleaving step according to claim 34, wherein said interleaving step and said third interleaving step comprise a batch interleaving step which is executed collectively when two product codes are transmitted to a disk medium. Error correction encoding method for disk media. 36. R = 12, C = 172, S = PO = 1
36. The error correction encoding method for a disk medium according to claim 34, wherein PI = 10. 37. An error correction encoding circuit for a disk medium for interleaving two product codes in an order based on a predetermined interleave rule and transmitting the interleaved data, and recording the user data in a predetermined sector length. A sector data generating means for generating (R × C) bytes of sector data by adding ID information of the user data to the head of each divided user data; Interleaved sector data generation for generating interleaved sector data (A) and interleaved sector data (B) by dividing the data into two in the order of the user data and arranging them in a matrix of (S × R) rows × C columns Means; and interleaving sector data (A) and (B)
In order to perform double error detection and correction encoding in the row and column directions, respectively, the P of the PO row having the relationship of PO = S in the column direction
O parity and PI parity of the PI column in the row direction are added, respectively, and each is ((S × R) + PO) rows × (C
+ PI) a product code generation means for generating a product code (A) and a product code (B) composed of columns, and the product codes (A) and (B) are respectively stored in the P row of the PO row.
O-parity is inserted row by row in the ((R / 2) +1)) row from the top of each of the S sector data for each row, and the first interleaved data (A) and the first interleaved data (B ), And divides the first interleaved data (B) into S areas in which R rows of sector data and PO parity are composed of one row. R for each row in the column direction
A second interleave means for generating a second interleave data (B) by performing a cyclic shift of / 2 rows; and alternately applying the first interleave data (A) and the second interleave data (B) in row units. And a third interleaving means for recording the transmitted data for each (R + 1) row as physical sector data on the disk medium in the order of transmission, and an error correction coding circuit for the disk medium. 38. A first interleaving means, a second interleaving means, and a third interleaving means, in a collective interleaving step executed collectively when sending two product codes to a disk medium. The error correction coding circuit for a disk medium according to claim 37, wherein the error correction coding circuit is configured. 39. R = 12, C = 172, S = PO = 1
39. The error correction encoding circuit for a disk medium according to claim 37, wherein PI = 10. 40. A physical medium according to the disk medium error correction coding method according to any one of claims 34 to 36, or by the disk medium error correction encoding circuit according to any one of claims 37 to 39. A disk medium on which sector data is recorded. 41. An error correction method using an error correction code based on physical sector data recorded on a disk medium according to claim 40, wherein reproduced data read from the disk medium is stored in a memory in (C + PI) bytes. Each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate first interleaved data (A) and second interleaved data (B). Deinterleaving step; dividing the second interleaved data (B) into S pieces by (R + 1) rows, and for each of the divided S pieces,
A second deinterleaving step of generating a first interleaved data (B) by performing a cyclic shift of R / 2 rows in the column direction on a row basis; a first interleaved data (A) and a first interleaved data (B); ) Is divided into S pieces, and one row is extracted from the ((R / 2) +1))-th row from the top of each of the divided rows and combined as PO parity, whereby each of the (( S × R) + PO) row × (C + P)
I) a first deinterleaving step of generating two product codes as columns, and an error correcting step of performing error correction on the two product codes for each product code. Error correction method for disk media. 42. A third deinterleaving step, a second deinterleaving step, and a first deinterleaving step, comprising:
42. The error correction method for a disk medium according to claim 41, comprising a batch deinterleaving step executed collectively. 43. An error correction circuit using an error correction code based on physical sector data recorded on a disk medium according to claim 40, wherein reproduced data read from the disk medium is stored in a memory as (C + PI) bytes. Each is divided into two in the form of a matrix of (S × R + PO) rows × (C + PI) columns to generate first interleaved data (A) and second interleaved data (B). Deinterleaving means and the second interleaved data (B) are written in (R + 1) rows by S
Second deinterleaving means for generating first interleaved data (B) by cyclically shifting each of the divided S pieces by R / 2 rows in a column direction in row units, Each of the first interleaved data (A) and the first interleaved data (B) is divided into S pieces, and each of the divided pieces is counted from the ((R / 2) +1))-th row from the top row. Each row is extracted and collected as PO parity, so that each is ((S × R) + PO) rows × (C + P
I) first deinterleaving means for generating two product codes which are columns, and error correcting means for performing error correction on the two product codes for each product code. Error correction circuit for disk media. 44. The third deinterleaving means, the second deinterleaving means, and the first deinterleaving means are constituted by batch deinterleaving means for executing collectively when a product code is stored in a memory. The error correction circuit for a disk medium according to claim 43, wherein: