JP2004281043A - Information signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information signal processing method for performing signal processing which allows a maximum burst error correction length to be relatively easily extended without increasing the redundancy. <P>SOLUTION: Each data sector is subjected such signal processing that inner parities for rows from the first row of a first divided data sector to the M-th row of a second divided data sector are successively outputted as follows; the first row of the first divided data sector, the inner parity for the first row of the first divided data sector, the first row of the second divided data sector, the inner parity for the first row of the second divided data sector, etc. are outputted, and a first outer parity and a second outer parity are alternately inserted and can be outputted for output of each data sector when repeatedly outputting the first to K-th data sectors. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention particularly relates to an information signal processing method suitable for signal processing of a high-density recording medium.

  In recent years, information recording media have been increasing in density. For example, a DVD (Digital Versatile Disk) has a shorter minimum mark length than a CD (Compact Disk), and a track line density has a track pitch of 0.74 μm, which is 1/1 / CD. 2, and the recording capacity of the user is 4.7 GB for a single-sided single-layer disc.

  In addition, ultra-high-density optical disks using the next generation violet laser (GaN) are being studied by various companies with respect to the current generation using a red laser, and the recording capacity of the user is said to exceed 20 GB. Naturally, the shortest mark length and the track pitch also become smaller, and their values are said to be about 1/2 compared to DVD. In such a situation, if a defect occurs on the optical disk due to dust or scratches during molding of the disk or during use, the defect is twice as large as a DVD when viewed relatively from the data length.

  For example, in the case of a DVD, as shown in FIG. 13A, product coding in which data of 192 rows × 172 columns is set as a set, and 10 columns of PI parity are generated for each row and 16 rows of PO parity are generated for each column. To form an ECC (error correction code) block of 208 rows × 182 columns. Further, as shown in FIG. 13B, the PO parity is interleaved by inserting one row of PO parity into the next row for 12 rows of data.

  Further, as schematically shown in FIG. 14, in the DVD, the above ECC block is sequentially recorded from the first row to the 208th row of the first ECC block EB1, and then the second ECC block EB2 is recorded. Are recorded in order from the first line to the 208th line, and so on.

  In this method, when erasure correction using PO parity is performed, up to 16 rows can be corrected. This can correct data errors due to continuous defects up to 6 mm on the disk. Such a continuous error is generally referred to as a burst error. When the linear density is reduced to の in such a format, the defect that can be corrected is up to 3 mm. Also, PI parity can normally correct 5 symbols (bytes), and assuming that there is no random error, the burst error length that can be corrected is up to about 10 μm for DVD. Therefore, when the linear density is reduced to １ ／, the maximum defect that can be corrected by the PI parity is about 5 μm.

  Therefore, in the above-described conventional digital signal processing method and information recording medium, the burst error length that can be corrected by the PI parity and the PO parity is further reduced under a situation where a random error occurs. Note that the interleaving of the PO row of the DVD keeps the ratio of including the parity in the sector constant, does not disperse the burst error, and has no effect of increasing the correction length.

  To solve such a problem, there is a method of increasing the number of parities and increasing the correction length. However, the redundancy of the parity with respect to the ECC block increases, which is disadvantageous for high-density recording.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an information signal processing method for relatively easily performing a signal processing in which a maximum burst error correction length is increased without increasing redundancy.

  Another object of the present invention is to provide an information signal processing method for dispersing a relatively small burst error and performing signal processing with a high data linear density.

In order to solve the above problems, the present invention provides an information signal processing method having the following configuration.
An incoming digital information signal is divided in units of a predetermined number of words to form K continuous data sectors of M rows × N columns, and the K data sectors are each divided into two in the column direction. By doing so, first and second divided data sectors each having M rows × N / 2 columns are obtained, and the inner parity generated in row units of each divided data sector and each divided data sector are represented by K columns. An information signal processing method for performing signal processing so that it can be output together with outer parity generated by arranging in the direction,
For each data sector, the first row of the first divided data sector, the inner parity with respect to the first row of the first divided data sector, the first row of the second divided data sector, the second divided data sector From the first row of the first divided data sector to the inner parity for the Mth row of the second divided data sector, such as inner parity for the first row of
Next, when repeatedly outputting data from the first data sector to the K-th data sector, a first outer parity and a second outer parity generated from the K divided data sectors are output for each of the data sectors. An information signal processing method characterized by performing signal processing so that either one of parity and parity can be inserted alternately and output.

  According to the present invention, it is possible to provide an information recording method and an information reproducing method for recording and reproducing information by increasing the maximum burst error correction length relatively easily without increasing the redundancy. It is possible to provide an information signal processing method for performing signal processing in which a large-scale burst error is dispersed and data linear density is increased.

  An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an arrangement of data in a first form of an information recording medium. This first embodiment is based on an interleave system that separates encoded data that has been ECC-encoded by a product encoding system on a recording medium, as shown in FIG. Assuming that EB1 and EB2 are a set, the first row of the first ECC block EB1 is followed by the first row of the second ECC block EB2, and then the second row of the first ECC block EB1 is followed by the second As in the second row of the ECC block EB2, the r-th row of the second ECC block EB2 is arranged next to the r-th row of the first ECC block EB1, and data interleaving is performed row by row.

  That is, in the first embodiment, the data of the two ECC blocks EB1 and EB2 are alternately arranged on a row-by-row basis. The configuration of the two ECC blocks EB1 and EB2 is the product code block shown in FIG. Also, as in the case of a DVD, one row of PO parity is inserted in advance into 12 rows of data, and the rate of inclusion of parity in one sector is kept constant.

  Here, in the first embodiment, assuming that a large burst error of, for example, 18 rows of ECC blocks occurs as shown in FIG. 1, the error distribution included in each ECC block after deinterleaving during reproduction is shown in FIG. As shown in (B), errors are dispersed in nine rows of the first ECC block EB1 and nine rows of the second ECC block EB2.

  On the other hand, as shown in FIG. 14, in the conventional recording medium shown in FIG. 14, if the same 18-row burst error occurs in the first ECC block EB1, as shown in FIG. As shown in FIG. 2A, errors occur in 18 consecutive rows of the ECC block EB1.

  As can be seen by comparing FIGS. 2A and 2B, the error dispersion rate slightly changes depending on the start and end positions of the burst error in the row, but the first error shown in FIG. In the embodiment, the error is dispersed in half compared to the conventional case shown in FIG. That is, in the first embodiment, there is no error variance in each row and there is no effect of increasing the correction length, but the number of error rows included in each column is reduced to half of that in the related art.

  In this case, in the prior art shown in FIG. 2A, even if the erasure correction is performed by the PO parity, the error cannot be corrected because the error exceeds the correction limit of 16 rows. On the other hand, in the first embodiment, as shown in FIG. 2B, the number of error lines in each ECC block is nine, and the error can be corrected because the number of error lines does not exceed the error limit of 16 lines. When the recording linear density is の of that of a DVD, the burst error correction limit is about 3 mm for 16 rows in the conventional method, but the burst error correction up to about 6 mm, which is the same as the DVD linear density, is possible in the present method. If the recording linear density is the same as that of the DVD, burst error correction of about 12 mm can be performed. That is, the correction length can be doubled without changing the redundancy.

  Although not shown, n consecutive (n ≧ 2) product code blocks (ECC blocks) are set as one set, and the r-th row of each of the first to n-th ECC blocks is sequentially arranged in order. In this case, a large burst error is distributed to n ECC blocks, and an error included in one ECC block is about 1 / n of that of the conventional method, and a long burst error correction length is n times. Can be.

  Next, an information recording / reproducing apparatus will be described. FIG. 3 shows a block diagram of an embodiment of the information recording / reproducing apparatus. This embodiment is applied to a DVD recording / reproducing apparatus. First, the configuration and operation of a recording system will be described. First, video information and audio information are compression-encoded by an MPEG encoder 11 based on a known MPEG method. The data is supplied to a static random access memory (SRAM) 12 as data.

  In addition, a total of 4 bytes of ID consisting of a lower 3 byte sector address and an upper 1 byte of disk information data are supplied to the IED encoder 13, where a 2-byte ID error correcting parity IED is added and then supplied to the SRAM 12. Is done. The IED is generated by RS (6, 4, 3). Here, RS (a, b, c) means a Reed-Solomon code having a codeword length a, the number of information points b, and a minimum inter-code distance c.

  The SRAM 12 receives the main data, the ID and the IED, and the 6-byte copy protection information CP and temporarily stores them. The total of 2060 bytes is obtained by adding the ID, the IED and the CP to 2048 bytes of the main data. Is read as a unit and supplied to the EDC encoder 14, where an error detection parity (EDC: error detection code) is generated. CRC (Cyclic Redundancy Code: cyclic code) is used to generate the EDC. The generated EDC is written to the SRAM 12.

  Further, a total of 2064 bytes including the EDC generated by the EDC encoder 14 and the 2060-byte data are supplied to the main data scrambler 15, and only the 2048-byte main data portion is randomized using the sector address. Here, a detailed description of the scrambling method is omitted. This randomized main data, that is, 2048 bytes of scramble domain data, is written to the SRAM 12. It is assumed that the memory map on the SRAM 12 at this time is addressed so as to have the mapping shown in FIG. At this time, it is assumed that the area of the ECC parity generated in the subsequent processing is left empty.

  The above 2064-byte data is called a data sector in DVD, and is composed of 172 columns (bytes) × 12 rows as shown in FIG. It is assumed that the sector address which is the lower 3 bytes of the ID of the first 4 bytes is added to successive data sectors by +1. In FIG. 5, “CPR_MAI” indicates the copy protection information CP. “M0”, “M1” and “M2047” indicate the first, second and 2048th bytes of the main data, respectively.

  In the SRAM 12, the data sectors are alternately arranged as shown in FIG. 4A. Thus, the sector numbers on the memory map of the DRAM 19 after the interleaving, that is, the sector numbers of the data written on the disk are arranged in order. By doing so, even if some sector addresses cannot be read due to defects or the like during reproduction, which will be described later, it is possible to predict the addresses that could not be read by checking the continuity of the sector addresses. In FIG. 4A, the lower 5 bits of the sector address of the data sector 1 of the ECC block 1 are always "00000B" so that the beginning of the ECC block generated thereafter can be determined during reproduction. So that

  In this manner, when 32 data sectors are stored in the SRAM 12, a total of 16 data sectors, that is, 172 columns (bytes) × 192 rows of odd-numbered data sectors are obtained as shown in FIG. The data is accessed in the column direction of the SRAM mapping and supplied to the ECC PO encoder 16, where a 16-byte PO parity (outer parity) is generated by the RS (208, 192, 17), and the generated PO parity is stored in the SRAM 12 It is written to the PO parity area. This is performed for 172 columns, and is stored in the PO parity area indicated by I in the memory map of the SRAM 12 in FIG.

  Next, 172 bytes of data are accessed in the row direction of the SRAM mapping of FIG. 4A and supplied to the ECC PI encoder 17, where the RS (182, 172, 11) uses a 10-byte PI parity (inner). Parity) is generated, and the generated PI parity is written in the PI parity area of the SRAM 12. This is performed for 208 rows (= 192 rows + 16 rows), and is stored in the PI parity area of the SRAM 12 indicated by II in the memory map of FIG. The 182 columns × 208 rows constitute the ECC block 1.

  Similarly, of the 32 data sectors stored in the SRAM 12, a total of 16 data sectors, that is, data of 172 columns (bytes) × 192 rows, composed of even-numbered data sectors, are also product codes. A PO parity and a PI parity are generated and written into the SRAM 12, and an ECC block 2 of 182 columns × 208 rows is accumulated on the memory map of the SRAM 12, as shown in FIG. When the above product code is used, the PI parity may be generated 192 rows ahead, and then the PO parity may be generated 182 columns.

  Next, the interleave processing unit 18 accesses the data in the SRAM 12 in the order of the data actually recorded on the optical disc 23, that is, reads out the data while interleaving and writes the data in the DRAM 19. That is, the interleave processing unit 18 reads 182 bytes of the first row of the first ECC block 1 from the SRAM 12, reads 182 bytes of the first row of the second ECC block 2, and then reads After reading out the 182 bytes of the second row of the second ECC block 1, the 182 bytes of the second row of the second ECC block 2 are read, and thereafter, similarly, each row of the two ECC blocks is read alternately.

  Each row of the PO parity of the two ECC blocks is read out for each sector of each ECC block. For example, after the last row of the first sector of the second ECC block 2 (that is, the twelfth row) is read, the first row of the PO parity of the first ECC block 1 is read, Next, the first row of the PO parity of the second ECC block 2 is read. Thus, after reading each sector, the PO parity of one row is sequentially read from the two ECC blocks.

  The data and parity from the SRAM 12 read by the interleave processing unit 18 in this manner are written to a dynamic random access memory (DRAM) 19. Therefore, the memory map of the DRAM 19 is as shown in FIG. Thus, data is stored on the DRAM 19 in the same order as the data arrangement on the disk shown in FIG.

  Note that the DRAM 19 is for absorbing a transfer rate difference when the transfer rate of data sent from the MPEG encoder 11 is different from the transfer rate of writing to the optical disk 23. In this case, the transfer rate of writing to the optical disk 23 is set to be higher than the transfer rate of data sent from the MPEG encoder 11. By doing so, the transfer rate for reading from the DRAM 19 is lower than the transfer rate for writing to the DRAM 19, so that the DRAM 19 does not become full and the data sent from the MPEG encoder 11 is not discarded.

  When the DRAM 19 becomes empty, the drive stops writing to the optical disk 23 (reading from the DRAM 19) and waits until data is accumulated in the DRAM 19. Generally, the drive is in a still state (one track back jump every one rotation of a spindle motor (not shown) for rotating the optical disk 23), and when a certain amount of data is accumulated in the DRAM 19, writing to the optical disk 23 is stopped. Resume recording from where you left off.

  As described above, the modulation and frame sync addition unit 20 reads out the data and various parities stored in the DRAM 19 in order from left to right and from top to bottom in FIG. In the case of the above, 8/16 modulation), a frame sync for data synchronization at the time of reproduction is added at an interval of 91 bytes, and supplied to the NRZI converter 21.

  The NRZI conversion unit 21 performs NRZI conversion (inverted by 1) on the input signal and supplies the signal to the pickup 22, modulates the intensity of laser light emitted from the laser light source in the pickup 22, and converts the modulated laser light into a spindle (not shown). An optical disk (here, a writable DVD) 23 rotated by a motor is irradiated and recorded. Therefore, as shown in FIG. 1, each row of the two ECC blocks EB1 and EB2 is alternately recorded on the optical disc 23. After the ECC block EB2, each row of EB3 and EB4 is recorded alternately, and similarly, each row of two consecutive ECC blocks is recorded alternately.

  The interleaving is performed at the time of reading the SRAM 12, but may be performed at the time of writing to the DRAM 19, or the interleaving may be performed at the time of writing to the SRAM 12, and the data may be read while deinterleaving the EDC generation and the ECC generation.

  Although two memories, the SRAM 12 and the DRAM 19, are used, only the DRAM may be used. In this case, the interleaving may be performed at the time of writing to or reading from one DRAM. For example, if data is written so as to have the DRAM mapping shown in FIG. 4B, and EDC, scramble, and EDC processing are generated while accessing the DRAM, the data is sequentially read from the first row and written to the optical disk 23. Good.

  Next, the configuration and operation of the reproducing system will be described. A laser light having a constant intensity is irradiated from the pickup 22 to the optical disk 23 that is rotating by a spindle motor (not shown), whereby the reflected light reflected from the signal recording surface of the optical disk 23 enters the pickup 22 and is photoelectrically converted. The obtained read signal is supplied to the signal processing unit 24 and subjected to signal processing such as RF amplification, waveform shaping, and bit PLL. The bit clock extracted by the bit PLL is supplied to an NRZ conversion and sync detection unit 25, where it is subjected to NRZ conversion based on the bit clock, and further detects a frame sync to find a break of each data byte (ie, frame synchronization). Take).

  As will be described later, when performing frame synchronization by the NRZ conversion and sync detection unit 25, sector synchronization is performed after frame synchronization. As described above, the reproduced signal having undergone frame synchronization and sector synchronization is supplied to a demodulator 26 and demodulated (here, 8/16 demodulation), and then supplied to an ID detection unit 27 and a deinterleave processing unit 28. You. Here, the ID in the output signal of the demodulator 26 includes a 3-bit sector address, and the sector address is increased by one for each sector of the ECC block composed of 16 sectors. And changes in units of ECC blocks.

  The ID detection section 27 detects an ID in the reproduction signal, supplies the sector address in the ID to the servo control section 36, and uses the sector address in a seek operation of the drive. If the reproduction signal is not from the user's desired sector address of the optical disk 23, the servo control unit 36 performs a seek operation for moving the pickup 22 to a desired sector address position of the optical disk 23 and reproducing the data. If so, the reproduction signal is written into the SRAM 29 while being deinterleaved by the deinterleave processing unit 28.

  Based on the sector address from the ID detection unit 27, the deinterleave processing unit 28 determines which one of the head (ECC block sync) of the ECC block of the demodulated signal from the demodulator 26 and the two ECC blocks in which the ECC block is continuous. It is detected whether the block is an ECC block, and is written into the SRAM 29 while addressing (deinterleaving) so as to be the same as the memory map in FIG.

  However, it is assumed that data is written to the SRAM 29 from the first sector of the first ECC block of the two ECC blocks. This is because if two consecutive ECC blocks are not aligned, the ECC block is not completed and error correction cannot be performed. The first sector of the two ECC blocks can be determined by the lower 5 bits of the sector address being "00000B".

  The ECC PI correction unit 30 reads data in the row direction from the SRAM 29 every time data of at least one row (182 bytes) is accumulated in the SRAM 29, performs error correction using PI parity, and outputs the corrected data. Write to SRAM29. The ECC PO correction unit 31 starts the PO correction after the PI correction of all the rows of the two consecutive ECC blocks is performed and the corrected data is written in the SRAM 29.

  The PO correction is performed by reading out 208 bytes of data of one ECC block from the SRAM 29 in the column direction of the memory map and using the PO parity. After the PO correction of all columns, that is, 182 bytes, is performed, the ID detection unit 32 and the descrambler 33 determine the sector data of the first ECC block, that is, the ID, IED, CP, main data, and EDC parity. The combined 2064 bytes are sequentially accessed to read data from the SRAM 29.

  The ID detector 32 detects the ID again from the data read from the SRAM 29 and supplies the sector address to the descrambler 33. The descrambler 33 descrambles 2048 bytes of main data in the data read from the SRAM 29 using the sector address input from the ID detection unit 32. The data descrambled by the descrambler 33 is supplied to the EDC error detection unit 34, and the EDC determines whether there is an error.

  The EDC error detection unit 34 inputs the detection result indicating that there is no error to the DRAM 35 and writes the data descrambled by the descrambler 33 to the DRAM 35. If there is an error, the EDC error detection unit 34 inputs the detection result indicating that there is an error to the DRAM 35. Then, the writing to the DRAM 35 is stopped, and a command is sent to the servo control unit 36 to read the same data from the optical disk 23 again. The servo control unit 36 moves the pickup 22 so as to access the desired sector address again. Such an operation is generally called a retry.

  Actually, when an error is detected by the EDC, the descrambled data for one sector has already been written in the DRAM 35. If an error occurs, the write address pointer of the DRAM 35 is returned by one sector. There is a need. The data written in the DRAM 35 is sequentially read out by the MPEG decoder 37, and is subjected to a decompression process based on the MPEG method to be a video signal and an audio signal. The deinterleaving may be performed after reading the SRAM 29.

  Here, the ECC block is composed of a plurality of data sectors, but as will be described later, one data sector may be divided and allocated to two ECC blocks. As shown in FIG. 7A, when one data sector is made up of 6 rows × 344 columns and divided in half in the column direction, that is, the data sector of 12 rows × 172 columns shown in FIG. As shown in FIG. 7 (A), a first divided data sector of 6 rows × 172 columns consisting only of odd rows (i_1 in the i-th data sector) and a 6 row × 172 columns of even rows only It is divided into a second divided data sector (i_2 in the i-th data sector), and these are divided into two columns.

  The left divided data sector forms an ECC block 1 and the right divided data sector forms an ECC block 2. In the case of the above example, they are arranged as shown in FIG. In this case, the arrangement of the data sectors is different from that of FIG. 4B, but the memory address arrangement is the same. In this case, the arrangement of the data sectors is as shown in FIG. FIG. 9A shows a memory map before interleaving at this time.

  In the example of FIG. 9B, every time two divided data sectors are output in 12 rows (= 2 × 6 rows), the PO parities of the two ECC blocks 1 and 2 are output one by one. By doing so, the main data is arranged in order on the recording medium, so that memory access during reproduction is facilitated.

  This is because, when a data sector is given by M rows and N columns, the data sector is divided in half in the column direction, and the first divided data sector and the second divided data sector of M rows (N / 2) columns are respectively provided. To form two ECC blocks, and a PO row and one row of both ECC blocks for each (M × 2) row (every two data sectors) of the first divided data sector and the second divided data sector Interleaving, such as inserting In other words, a data sector given by R rows (= M × 2) and C columns (= N / 2) is replaced by a first divided data sector of odd rows (R / 2) and C columns and an R row consisting of even rows. / 2) divided into the second divided data sectors in the row C column to form two ECC blocks, and for each R row (every two data sectors) of the first divided data sector and the second divided data sector Interleaving such as inserting one PO row of both ECC blocks is performed.

  Next, the recording / reproducing method of the frame sync will be further described. In the frame sync detection by the NRZ conversion and sync detection unit 25, the position of the next frame sync from the normally detected frame sync is predicted by counting the number of bits, and within a few bits before and after the predicted bit number. If the next frame sync does not come, a case where the frame sync cannot be read due to a defect or the like is dealt with by inserting the frame sync at the predicted point.

  Here, for example, it is assumed that two consecutive frame syncs have been detected. In that case, it is determined that frame synchronization has been achieved, and then sector synchronization is performed. In the conventional DVD, a unique code different from other frame syncs is adopted as the first frame sync of each sector. This frame sync is called SY0. This SY0 appears at a constant interval of 26 sync frames. The NRZ conversion and sync detection unit 25 predicts the next position of SY0 from SY0 that was normally detected during reproduction. This can be done simply by counting 26 at the frame sync frequency and determining whether or not the next SY0 comes there. As described above, since the interval of SY0 is constant at 26 sync frames, prediction can be performed with a simple counter.

  However, in the above-described embodiment, according to the memory map of the DRAM 19 as shown in FIG. 4B, each row of two consecutive ECC blocks is alternately recorded on the optical disc 23 in units of one row. Similarly, when a unique sync SY0 is adopted only for the first frame of one sector, the physical sector of the signal recorded on the optical disk 23 has an irregular generation period of SY0 as shown in FIG. However, the sync code itself is not stored in the DRAM 19, but is recorded on the optical disk 23 after being added at an interval of 91 bytes in the modulation and frame sync adding unit 20.

  That is, in this method, as shown in FIG. 6, when protection is performed from the beginning of two ECC blocks, first, after the first sync frame SY0 of data sector 1 indicated by 41, the data sector indicated by 42 after two sync frames The first sync frame SY0 of data sector 3 indicated by 43 is located after the first sync frame of data sector 3 indicated by 43 after 50 sync frames, and the first sync frame SY0 of data sector 3 indicated by 44 is located after 50 sync frames. Thereafter, similarly, the interval of SY0 alternates between two sync frames and 50 sync frames.

  In this case, the determination of which SY0 of the two ECC blocks is performed is to first detect SY0 normally, and then simultaneously provide the predicted values to both the two-sync frame destination and the fifty-sync frame destination by using two counters. It may be determined whether the next SY0 comes. However, this method requires a complicated circuit.

  Therefore, in this embodiment, 2060 bytes consisting of main data, ID, IED, and CP are written to the SRAM 12 of FIG. 3 and then read out to read the 4-byte EDC so that the memory mapping shown in FIG. Is generated by the EDC encoder 14 and written into the SRAM 12. Here, as shown in FIG. 7A, one data sector is 6 rows × 344 columns, which is divided in half in the column direction, and an SRAM area for ECC PI parity generation performed later. Shall be opened.

  That is, as shown in FIG. 7A, a 12-row × 172-column data sector shown in FIG. 5 is converted into a 6-row × 172-column first divided data sector consisting of only odd-numbered rows (in the i-th data sector, i_1) and a second divided data sector (i_2 for the i-th data sector) of six rows and 172 columns consisting of even rows only, and divides them into two columns. The left divided data sector forms an ECC block 1 and the right divided data sector forms an ECC block 2.

  As shown in the SRAM mapping of FIG. 7A, after 192 rows and 32 sectors (= 192 rows, 16 sectors × 2) are prepared, the main data is randomized by the scrambler 15 as in the above-described example. The data is written to the SRAM 12. Next, 192 rows (bytes) of data are read from the SRAM 12 in the column direction by the ECC PO encoder 16, a 10-byte PO parity is generated, and written into the PO parity area of the SRAM 12. This is performed for 344 columns (= 172 columns × 2). Subsequently, as shown in FIG. 7A, 172 columns (bytes) of data are read from the SRAM 12 in the row direction by the ECC PI encoder 17, a 10-byte PI parity is generated, and written to the PI parity area of the SRAM 12. This is performed for 416 rows (= 208 rows × 2).

  As a result, as shown in the memory map of FIG. 7A, a total of two ECC blocks, that is, the first ECC block 1 in the left half and the second ECC block in the right half have been generated in the SRAM 12. Become. The sector address is assumed to be incremented by +1 for successive data sectors, as in the above-described example.

  Next, the data read from the SRAM 12 is written into the DRAM 19 while being interleaved by the interleave processing unit 18 as shown in FIG. As described above, the interleave reads the first row of the first ECC block, reads the first row of the second ECC block, and then reads the second row of the first ECC block. Thereafter, each row of the ECC block is added alternately so as to read the second row of the second ECC block. As the PO rows of two ECC blocks, one PO row on one side (182 bytes) is inserted for every 12 rows (6 rows × 2) of one data sector.

  As a result, data is accumulated on the memory map of the DRAM 19 as shown in FIG. At first glance, FIG. 7A and FIG. 7B are almost the same, and it seems that the interleaving is not performed between the data of the SRAM 12 and the data of the DRAM 19. This is the relationship between the ECC block and the data to be written on the optical disk 23. Since the data is written across the ECC block, it can be said that the data is interleaved.

  FIG. 8 illustrates the memory map of FIG. 7 in a different representation for easy understanding of interleaving, and both show the same thing. FIG. 8A is a memory map of the SRAM 12, in which the first divided data of 6 rows and 172 columns is composed of 32 sectors in total, 16 rows of 172 columns of PO parity, and 208 rows and 10 columns of PI parity. A first ECC block is constituted by 182 columns, and similarly, a second ECC block is constituted by 208 rows and 182 columns including 32 sectors of the second divided data sector. The contents are the same as in FIG. This is interleaved on the memory map of the DRAM 19 as shown in FIG. FIG. 8B is the same as FIG. 7B.

  The interleaved data sequentially read from the DRAM 19 is added to the modulation and frame sync at 91-byte intervals in the same manner as described above, and further subjected to NRZI conversion, and then recorded on the optical disk 23.

  As a result, the physical sector composed of the data and the frame sync recorded on the optical disk 23 is shown in FIG. 10, and the first frame sync SY0 of the sector is 26 syncs as indicated by 51, 52 and 53. The frames are arranged at equal intervals. In FIG. 10, Fn indicates a relative frame number. The data sectors 1-1a and 1-1b are composed of 91 columns (bytes) in the first half, 81 columns (bytes) in the second half, and a PI parity 10 shown in FIGS. 7B and 8B. Byte. Others are the same. As described above, since the sync frame SY0 can be recorded and reproduced at regular intervals, sector synchronization during reproduction can be performed by a simple circuit.

  The reproducing operation in this case is the same as that of the configuration of FIG. 6 described above, and therefore will be described only briefly. Each time at least one row (182 bytes) of data is accumulated in the SRAM 29, the ECC PI correction unit 30 in FIG. 3 reads data in the row direction from the SRAM 29, performs error correction using PI parity, and performs error correction. Is written in the SRAM 29. The ECC PO correction unit 31 starts the PO correction after the PI correction of all the rows of the two consecutive ECC blocks is performed and the corrected data is written in the SRAM 29.

  In PO correction, 208 bytes of data are read from the SRAM 29 in the column direction of the memory map, and PO correction is performed on all columns of 2 ECC blocks, that is, 364 columns (= 182 columns × 2) using PO parity. Thereafter, the sector data spanning two ECC blocks, that is, 2064 bytes including ID, IED, CP, main data, and EDC parity are sequentially accessed to read data from the SRAM 29.

  The above is an example of the data sector of 12 rows and 172 columns shown in FIG. 7A, but when the data sector is given by M rows and N columns, the data sector is divided in half in the column direction and each of M rows ( (N / 2) columns into a first divided data sector and a second divided data sector to form two ECC blocks, and each M row of the first divided data sector and the second divided data sector Interleaving may be performed such that one PO row of one ECC block is inserted into each (one data sector). In other words, a data sector given by R rows (= M × 2) and C columns (= N / 2) is divided into a first divided data sector of R / 2 rows and C columns composed of odd rows and R / 2 composed of even rows. It is divided into a second divided data sector in row C and forms two ECC blocks, and each (R / 2) row of the first divided data sector and the second divided data sector (each data sector) ) Is to insert one PO row of one ECC block.

  FIG. 11 shows an arrangement of data in the second form of the information recording medium. This second embodiment is based on an interleave system in which coded data ECC-coded by a product coding system is discretely recorded on a recording medium, as shown in FIG. Assuming that EB1 and EB2 are a set, the first byte of the first ECC block EB1 is the first byte, the second byte of the second ECC block EB2 is the second byte, and then the one of the first ECC block EB1 The second ECC block EB2 next to the odd-numbered byte of the first row of the first ECC block EB1, such as the fourth byte of the first row of the second ECC block EB2 next to the third byte of the row Is repeated until the end of the first line. In FIG. 11, this data combination is indicated by the EB1_1 (EB2_1) row.

  As described above, one ECC block has 182 columns (bytes) in each row and is composed of 208 rows (bytes). Therefore, the second ECC block EB2 follows the 181st byte in the first row of the first ECC block EB1. The 182nd byte of the first row is placed. Subsequently, the first byte of the first row of EB2 is arranged, the second byte of the first row of EB1 is arranged next, and the odd-numbered byte of EB2 is followed by the even-numbered byte of EB2. Is repeated byte by byte until the end of the first line. In FIG. 11, this data combination is indicated by the Eb2_1 (EB1_1) row.

  Next, for the second row of EB1 and EB2, similarly, the k-th byte of one ECC block of EB1 and EB2 is arranged, and then the (k + 1) -th byte of the other ECC block is arranged. As described above, data arrangement is repeatedly performed in byte units until the end of the second line. Such an arrangement of the data order is performed for all the rows of EB1 and EB2.

  Note that, as in the first embodiment, each row of the PO parity of the two ECC blocks is read out for each sector of each ECC block. For example, after the last byte of the last row of the first sector of the first ECC block EB1, that is, the 182nd byte is read, the first byte of the first row of the PO parity of the first ECC block EB1 is Then, the second byte of the first row of the PO parity of the second ECC block EB2 is read. As described above, data is written to the memory (DRAM 19 in FIG. 3) of the recording system of the information recording / reproducing apparatus in the same order as the data array on the optical disk shown in FIG.

  In this example, the interleaving is performed at the time of reading from the SRAM, but is not limited to this, and may be at the time of writing to the DRAM. Further, it may be performed at the time of writing to the SRAM, and EDC generation and ECC generation may be performed by reading data while deinterleaving.

  In the PI correction in the reproduction system of the optical disk according to the second embodiment, every time one row (182 bytes × 2) of both ECC blocks is written into the memory (corresponding to the SRAM 29 in FIG. 3), the PI is corrected. The error correction processing is performed twice (for each one row of two ECC blocks). The PO correction is performed in the same manner as in the first embodiment after the PI correction of all rows of the two ECC blocks is completed.

  Here, it is assumed that relatively small burst errors occur at three places during reproduction of the optical disk of the second embodiment. In FIG. 11, an 8-byte error occurred at a position indicated by 61, a 5-byte error occurred at a position indicated by 62, and a 10-byte error occurred at a position indicated by 63.

  FIG. 12 shows an error distribution of the deinterleaved data at the time of reproduction in this case. If even data is not replaced at the time of recording, the error remains in each row as it is, but in the second mode, the burst error is distributed to two ECC blocks, and the first ECC block EB1 has 4 bytes, 2 bytes, 5 bytes, and 4 bytes, 3 bytes, and 5 bytes are distributed to the second ECC block, respectively. Here, when the burst error has an odd data length, such as a 5-byte burst error that has occurred in the 20th row, the error length of one of the ECC blocks is increased by one byte. In FIGS. 11 and 12, Dn indicates the data of the relative data No. n in each row.

  As described above, the PI parity of a DVD is 10 bytes, and usually 5 symbols (bytes) can be corrected. Therefore, in a conventional case where even-numbered data is not replaced during recording, a 5-byte error can be corrected. However, the remaining 8 byte error and 10 byte error cannot be corrected. On the other hand, in the second embodiment, the error included in the row of each one ECC block can be reduced to about 1/2 for a relatively small burst error length. For a 10-byte error, the error is distributed to the two ECC blocks in units of 4 bytes or 5 bytes, so that all errors can be corrected.

  In the second embodiment, for a relatively small burst error length, errors contained in a row of each one ECC block can be reduced to about １ ／. As described above, assuming that there is no random error, the burst error length that can be corrected in the conventional DVD format is up to about 10 μm in DVD, and when the linear density is reduced to １ ／, the defect corrected by PI is reduced. Is a maximum of about 5 μm. On the other hand, in the second embodiment, the burst error can be corrected approximately twice as much, so that even if the linear density is reduced to １ ／, the defect corrected by the PI is at most about 10 μm. In the case of DVD linear density, burst errors up to about 20 μm can be corrected by PI.

  When a relatively small error occurs in the same row in two ECC blocks, the burst error length is equal to the number of errors in the row when the second mode is used. It will also lower it.

  In the second embodiment, each row of the PO parity of the two ECC blocks is read out one row for each sector of each ECC block. However, as shown in FIG. A sector of 6 rows × 344 columns is divided into a first divided data sector and a second divided data sector to form two ECC blocks, and two data sectors of 12 lines (the first divided data sector of 12 lines and the second of The interleaving described in the second embodiment may be performed after interleaving such that one PO row (= 182 bytes × 2) of both ECC blocks is inserted for every 12 divided data sectors. By doing so, also in the second embodiment, the main data is arranged in order on the medium, so that memory access during reproduction is facilitated.

  Further, as shown in FIG. 7A, one data sector of 6 rows × 344 columns is divided into a first divided data sector and a second divided data sector to constitute two ECC blocks. Interleaving was performed such that one PO row (= 182 bytes × 2) of one ECC block was inserted for each 12 data sectors (6 first divided data sectors and 6 second divided data sectors). Later, the interleaving described in the second embodiment may be performed. By doing so, also in the second embodiment, the unique frame sync SY0 at the head of the physical sector can be recorded at a constant cycle.

  The present invention is not limited to the above embodiment. For example, in the above embodiment, two types of product codes, PI parity and PO parity, are used. However, the present invention can be applied to a case where three or more types of product codes are used.

  In the second embodiment, the same row of the two product code blocks (EB1 and EB2) is alternately switched every byte. However, a prime number of 182 bytes per row is a 2-byte unit, a 13-byte unit, and a 14-byte unit. The switching may be performed alternately in byte units or 91 byte units. However, as the number of unit bytes is smaller, the correction capability for a relatively small error can be improved. Also, the digital signal after interleaving in each embodiment can be transmitted wirelessly or by wire, or can be distributed via the Internet.

FIG. 3 is a layout diagram of data of a first mode of the information recording medium. FIG. 15 is an error distribution diagram of an ECC block after deinterleaving at the time of reproduction in FIGS. 14 and 1. It is a block diagram of one form of an information recording and reproducing device. FIG. 4 is a diagram illustrating an example of a memory map of two memories before and after interleaving of the recording system in FIG. 3. FIG. 2 is a diagram illustrating a configuration of a data sector of a DVD. FIG. 4 is a configuration diagram of an example of a physical sector according to FIG. 3; FIG. 4 is a diagram illustrating another example of a memory map of two memories before and after interleaving of the recording system in FIG. 3. FIG. 8 is a diagram showing a memory map of the two memories of FIG. 7 in another expression method. FIG. 4 is a diagram showing still another example of a memory map of two memories before and after interleaving of the recording system in FIG. 3. FIG. 9 is a configuration diagram of an example of a physical sector according to FIGS. 7 and 8; FIG. 5 is a layout diagram of data in a second form of the information recording medium. FIG. 12 is an error distribution diagram of an ECC block after deinterleaving at the time of reproduction in the case of FIG. 11. It is a block diagram of a conventional ECC block. FIG. 11 is a layout diagram of an example of data on a conventional information recording medium.

Explanation of reference numerals

11 MPEG encoder 12, 29 Static random access memory (SRAM)
14 EDC encoder 15 Main data scrambler 16 ECC PO encoder 17 ECC PI encoder 18 Interleave processing unit 19, 35 Dynamic random access memory (DRAM)
Reference Signs List 20 Modulation and frame sync addition unit 21 NRZI conversion unit 22 Pickup 23 Optical disk 25 NRZ conversion / sync detection unit 26 Demodulator 27, 32 ID detection unit 28 Deinterleave processing unit 30 ECC PI correction unit 31 ECC PO correction unit 33 Descrambler 34 EDC error detection unit 36 Servo control unit 37 MPEG decoder
IPO parity area
II PI parity area

Claims (1)

An incoming digital information signal is divided in units of a predetermined number of words to form K continuous data sectors of M rows × N columns, and the K data sectors are each divided into two in the column direction. By doing so, first and second divided data sectors each having M rows × N / 2 columns are obtained, and the inner parity generated in row units of each divided data sector and each divided data sector are represented by K columns. An information signal processing method for performing signal processing so that it can be output together with outer parity generated by arranging in the direction,
For each data sector, the first row of the first divided data sector, the inner parity with respect to the first row of the first divided data sector, the first row of the second divided data sector, the second divided data sector From the first row of the first divided data sector to the inner parity for the Mth row of the second divided data sector, such as inner parity for the first row of
Next, when repeatedly outputting data from the first data sector to the K-th data sector, a first outer parity and a second outer parity generated from the K divided data sectors are output for each of the data sectors. An information signal processing method characterized by performing signal processing so that either one of parity and parity can be inserted alternately and output.

Images