JP2002190158A - Error-correcting coding method of disk medium, optical disk, error-correcting method, error-correcting coding circuit and error-correcting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome the problems such that the single burst error permits the correction of the correcting code in the line direction to be sometimes impossible, and a plurality of burst error occurrences permit the correction of the whole product code to become impossible, in a conventional error-correcting method for recording the product code two-dimensionally coded in the line direction. SOLUTION: By the product-code formation step, a reliable error correction can be carried out by alternately arranging two product codes stored on a memory every line and recording these in the slant direction, and in the case of coding, even if it is the recording in the slant direction, the address can be read at a fixed interval by performing a data transposition step and a one- way cyclic step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error correction encoding method for a disk medium such as a DVD, an optical disk, an error correction method, an error correction encoding circuit, and an error correction circuit.

[0002]

2. Description of the Related Art Conventionally, optical disks such as CDs, which are high-density and large-capacity recording media, have been used to correct errors caused by defects in the medium or dust or scratches adhering to the disk surface.
An error correction code such as an ed-Solomon code is used. Further, for example, by realizing higher capacity and higher density,
In a DVD that enables digital recording of data, data is arranged in a matrix, and error correction coding is performed in two dimensions in a row direction and a column direction. In this case, a product code obtained by Reed-Solomon coding is used. .

In general, a product code encodes each of a row and a column using a code having a relatively low error correction capability, and further realizes a high error correction capability by performing two-dimensional encoding. .

In the DVD, user data is arranged in a matrix of 172 bytes in the row direction and 192 bytes in the column direction, and a parity of 10 bytes is added in the row direction and a parity of 16 bytes is added in the column direction. Therefore, 182 bytes x 2
One product code is composed of 08 bytes, and is recorded on the disk in the row direction. Since the encoding in the row and column directions has the added parity of 10 bytes and 16 bytes, respectively, the minimum distance of the code is 11 and 17, respectively, and the correction of 5 and 8 corrections respectively. Have the ability.

When the minimum distance is d, the number of corrections t
Generally satisfies the relationship d ≧ 2 × t + 1 (Equation 1).

Further, when an error position is known at the time of performing a correction process, erasure correction using so-called known error position information is possible, and the number of corrections can be increased up to twice by performing erasure correction. Can be.

In the case of a product code, this error position information can be easily obtained by detecting that the code in the row or column direction cannot be corrected. If an uncorrectable flag is assigned to the entire uncorrectable row and column, and if an uncorrectable flag is assigned to the corresponding row in the row-direction correction, the error will be corrected in the next column-direction code when the error is corrected. If an uncorrectable flag is added to the corresponding column in the correction of the next column, the error correction of the code in the next row direction is performed, and the added uncorrectable flag is used as it is as the error position information, that is, the erasure flag. Alternatively, the row can be corrected by erasure correction.

Assuming that the number of erasure corrections is e, the relationship of d ≧ 2 × t + e + 1 (Equation 2) holds, and in the above-described DVD example, the row direction is
Since the minimum distance d = 11, when all the erasure corrections are performed, the correction capability of a maximum of 10 corrections (t = 0, e = 1
0) In the column direction, since the minimum distance d = 17, similarly, it has a correction capability of 16 corrections.

In a product code, so-called repetitive correction, which repeatedly executes correction of a code in a row direction and a column direction, is effective. One correction in a row direction or a column direction corrects all errors. Even if it is not possible, by repeating, it is often possible to gradually reduce the number of errors in the entire product code and finally correct all of them. , A highly reliable error correction is realized.

[0010]

Errors in a disk medium such as an optical disk often occur due to defects in the medium or dust on the disk surface. At this time, errors are generally burst errors, that is, continuous data often causes continuous errors. Furthermore, as the density increases in recent years, the influence of dust and the like on the disk surface becomes relatively more significant, and the occurrence of a larger burst error has become a problem. For example, a few μm to several tens μm of dust attached on the disk surface, and continuously from several tens of bytes to one
A large burst error of about 00 bytes may be caused. Further, a plurality of these burst errors may occur.

[0011] In the above-mentioned DVD, an HD-D which records an HD image from a conventional SD image as a next-generation DVD is also used.
As VD development research progresses, reducing the effects of burst errors has become a major issue.

However, the above-described error correcting code having a relatively low correction capability is converted into a product code obtained by performing error correction coding in two dimensions orthogonal to each other in the row and column directions.
Alternatively, according to the conventional error correction method of recording in the column direction, when such a long burst error occurs, a code coded in the same direction as the recording direction among the codes in two directions has a correction capability. There is a problem that an error greatly exceeds the value, causing an uncorrectable or erroneous correction, and one of the two-way codes becomes almost useless. Then, when a plurality of these long burst errors occur, there is a problem that the entire product code cannot be corrected at a high probability.

In view of the above-mentioned problems, the present invention is compatible with the conventional product code, that is, it can be corrected with high reliability even if a long burst error occurs with little change from the conventional method. An object of the present invention is to provide an error correction coding method for a disk medium, an optical disk, an error correction method, an error correction coding circuit, and an error correction circuit.

[0014]

SUMMARY OF THE INVENTION An error correction encoding method for a disk medium according to the present invention is to double-correct error-encode data in the row and column directions to obtain (s × m) rows × (s × n) columns. Generating a first product code and storing it in a memory; and alternately generating m rows of parity with respect to a column direction code of the first product code by one row for each data (s-1) row. And a parity row interleaving step of generating a second product code by dividing the second product code into square areas of s rows × s columns and exchanging rows and columns in each of the square areas A data transposition step of generating a third product code, and forming a first product code group by grouping the third product code by two, and forming one of the first product code group in the first product code group. Each row of each square area of the third product code is cyclically shifted by a predetermined number of rows in the column direction. A one-side cyclic step of generating a fourth product code, and arranging the third product code and the fourth product code in the first product code group alternately for each row to obtain 2 × (s × m) a second product code group generating step of generating a second product code group of rows × (s × n) columns;
An oblique reading step of obliquely reading the second product code group, and recording the second product code group on the disk medium in the order of reading in the oblique reading step.

In the optical disk of the present invention, the data is double-error-correction-coded in the row and column directions to obtain (s × m) rows × (s
Xn) a product code generation step of generating a first product code of a column and storing it in a memory; and a parity of m rows with respect to a column direction code of the first product code, A parity row interleaving step of alternately arranging one row at a time to generate a second product code;
A data transposing step of dividing into square areas of rows × s columns and generating a third product code in which the rows and columns in each of the square areas are exchanged, and a set of two of the third product codes To form a first product code group, and each row of each square area of one of the third product codes in the first product code group is cyclically shifted by a predetermined number of rows in the column direction. And a third product code in the first product code group and a fourth product code in the first product code group are alternately arranged for each row to obtain 2 × (s × m) rows. An error correction encoding method comprising: a second product code group generating step of generating a second product code group of × (s × n) columns; and an oblique reading step of reading the second product code group in an oblique direction. Characterized in that the second product code group generated by the above is recorded. It includes those were.

According to the error correction method of the present invention, the reproduced data read from the disk medium is obliquely stored as a second product code group into a 2 × (s × m) rows × (s × n) columns matrix memory. Diagonal writing step of storing the second product code group stored in the same direction,
A product code group dividing step of dividing into m rows × n columns of third and fourth product codes; and dividing the third and fourth product codes into s rows × s columns of square regions, A one-side cyclic step of converting the fourth product code into a product code having the same structure as the third product code by cyclically shifting each row of each square area of the product code in the column direction by a predetermined number of rows. And a row and a column in each square area of s rows × s columns of the third product code converted from the fourth product code and the third product code directly generated in the product code group dividing step. And a data transposing step of generating two second product codes by replacing the second product code, and (s−1) × m rows where the last row is a parity row for every s rows of the data of the second product codes. Parity row data that is sequentially arranged in the memory area next to the data of A motor Reeve step, the first
And an error correction step of performing an error correction on the product code of.

The error correction coding circuit of the present invention performs double error correction coding of data in the row and column directions (s × m).
A product code generating means for generating a first product code of a row × (s × n) column and storing it in a memory; and a parity of m rows with respect to a column direction code of the first product code is set to the data (s−n). 1) parity row interleaving means for alternately arranging one row per row to generate a second product code;
Data transposing means for generating a third product code by dividing a square region of rows × s columns and exchanging rows and columns in each of the square regions, and two sets of the third product code First
And forming each row of each square area of one of the third product codes in the first product code group,
A one-side cyclic means for cyclically shifting by a predetermined number of rows in the column direction to generate a fourth product code; and a third product code and a fourth product code in the first product code group, A second product code group generating means for generating a second product code group of 2 × (s × m) rows × (s × n) columns by alternately arranging the second product code groups in an oblique direction; And an oblique readout means for reading the data.

The error correction circuit according to the present invention converts the reproduced data read from the disk medium into a 2 × (s × m) rows × (s × n) columns matrix memory as a second product code group. Diagonal writing means for storing in a direction, and a product code group for dividing the stored second product code group alternately for each row and dividing it into two m rows × n columns of third and fourth product codes Dividing means and the third and fourth product codes
The fourth product code is divided into the square products of the fourth product code by dividing the four product codes by the predetermined number of rows in the column direction by dividing the fourth product code into the third product. One-side cyclic means for converting to a product code having the same structure as the product code, and a third product code converted from the fourth product code and a third product code directly generated by the product code group dividing means, By replacing the rows and columns in each square area of s rows × s columns, 2
Data transposing means for generating a plurality of second product codes, and the last one row for each s row of the data of each of the second product codes as a parity row, and a next row of (s-1) × m rows of data. Parity row deinterleaving means for generating a first product code by sequentially arranging them in a memory area; and error correcting means for performing error correction on the first product code. is there.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a first product code of an error correction coding method for a disk medium according to a first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a first product code. Reference numeral 102 denotes user data of the product code 101, reference numeral 103 denotes a PO parity which is a parity part of the PO code encoded in the column direction in the product code 101, and reference numeral 104 denotes a parity part of a PI code which is encoded in the row direction in the product code 101. PI parity. PO code and PI
The code is Reed-So in which all symbols are 1 byte.
and a PO parity 103
16 bytes × 182 columns, and 10 bytes × 192 rows as PI parity 104 are added. (Product code generation step) This is a step of generating the first product code 101 as described above. (Parity row interleaving step) Next, 182 columns ×
The product code 101 of 208 rows is divided into 16 sectors.
A sector is a unit for recording and reproducing data recorded on an optical disk, and each sector is provided with an address for searching for target data. One sector is composed of 182 columns × 13 rows, and all sectors have the same structure. Of the 13 lines, 12 lines are the user data section. Each row of the PO parity of the product code generated in the product code generation step is alternately arranged for every 12 rows of user data so that an address can be added to the head of the user data portion, and a second product code is generated. I do.

FIG. 2 shows the second product code after the parity row interleaving step. In FIG. 2, 201 is the second
, 202 is the user data of the product code 201, 2
03 is a PO parity which is a parity part of the PO code coded in the column direction in the product code 201, and 204 is a product code 2
01, a PI parity which is a parity part of a PI code coded in the row direction, 205 is a sector and is approximately 2K
The second product code is composed of 16 bytes of user data and parity of the correction code. Reference numeral 206 denotes an address assigned to the sector 205, which is a 6-byte address including a CRC check code.

The steps up to this step are the same as those of the well-known DVD error correction coding method. In the DVD, the second product code 201 is recorded in the row direction, and by executing a parity row interleaving step, all sectors have the same structure, and an address is added to the head of the user data section. Has been realized.

In the error correction encoding method for a disk medium according to the first embodiment of the present invention, encoding is performed by adding the following procedure. (Data transposition step) Next, the product code 201 is converted into 13 rows ×
Divided into 13 columns of squares, ie 14 per sector
A third product code is generated by dividing into square areas and exchanging rows and columns inside each of the divided square areas. FIG. 3 shows a third product code generated in this data transposition step. In FIG. 3, reference numeral 301 denotes a third product code, 3
02 is user data of the product code 301, 303 is a PO parity which is a parity part of the PO code encoded in the column direction in the product code 301, and 304 is a parity part of a PI code which is encoded in the row direction in the product code 201. PI parity, 305 is a sector, 306 is an address assigned to the sector 305, 307 is a square area, and by replacing the rows and columns of each square area 307, for example,
Although the address 206 in FIG. 2 is located on the upper side of each square area 307, in FIG. 3, the address 206 is located on the left side of the square area 307. (One-sided cyclic step) Next, the third product code is grouped into two sets to form a first product code group, and each square area of one of the two third product codes is arranged in the column direction. A fourth product code is generated by performing a cyclic shift by a predetermined number of rows.

FIG. 4 shows a fourth product code set (first product code group) generated from the third product code set. FIG. 5 is an explanatory diagram of a first product code group.
01 and 402 are two third product codes constituting the first product code group, and are the same as 301 in FIG. In FIG. 4, each square area in the lower third product code 402 is cyclically shifted by
Is generated. Upper third product code 401
Is denoted as 403 in FIG.

Here, only the lower third product code 402 is cyclically shifted by 6 lines in each square area, so that addresses are arranged at regular intervals when two product codes are combined as described later. I can do it. In the fourth product code 404, the address 405 is the address 406 at a position shifted by six rows.

In the above-described one-side cyclic step, each square area is cyclically shifted by six rows in the column direction. However, when two product codes are combined, it is intended that addresses can be arranged at regular intervals. Instead, a method of exchanging the upper six rows and the succeeding six rows of each square area may be used. Here, six lines are cyclically shifted or six lines are replaced. However, since the number of bytes of the address is 6 bytes including the CRC check code, the number of lines is set to 6 lines. By shifting or replacing the numbers, it becomes possible to arrange addresses at regular intervals.

Next, a second product code group generating step of combining the first product code group obtained by converting only one of the product codes into the fourth product code into a second product code group is executed. (Second Product Code Group Generation Step) This step will be described with reference to FIG. FIG. 5 is an explanatory diagram of the second product code group generation step. In FIG. 5, reference numeral 501 denotes a third product code, reference numeral 502 denotes a fourth product code shifted six rows in the column direction, and two product codes 501 and 503.
One product code group is formed.

The above two product codes are combined into one by alternately arranging one line from each product code. 509
As a combined second product code group. Second
Step 503: The first line of the third product code 501 is arranged as the first line of the second product code group 509.

Step 510: 1 of the fourth product code 502
The second row is arranged as the second row of the second product code group 509.

Step 504: Third product code 501-2
The line is arranged as the third line of the second product code group 509.

Step 511: Fourth product code 502-2
The second row is arranged as the second row of the second product code group 509.

Similarly, a second product code group 509 is formed by arranging each row one by one.

By executing this step as described above, the address 505 is arranged such that the second product code is divided every other line (step 506), and the address 507 is similarly arranged every other line. Placed (step 50
8). Similarly, the addresses of all the sectors are arranged at the position of the leading byte of each row every other row, with 13 rows as one unit, since one address is 6 bytes.

Next, an oblique reading step of obliquely reading the second product code group and recording it on the disk medium in the read order is executed. (Oblique reading step) This step will be described with reference to FIG. FIG. 6 is an explanatory diagram of the oblique reading step.
6, reference numeral 601 denotes a second product code group, which is the same as 509 in FIG.

Step 602: First, in the second product code group 601, the symbols in the first row and the first column are read out, and then the data of 182 symbols are read in the second row, the second column, and the third row and the third column. Is read.

Step 603: Next, the symbols are similarly read obliquely from the second row and first column. Similarly, all the symbols are read out diagonally.

Steps 605 and 606: When the bottom of the row of the second product code group 601 is reached, that is, at the 208th row, the process returns to the first row.

The reading is performed in the oblique direction as described above.
The data is recorded on the disk in the reading order.

By recording obliquely as described above,
Recording can be performed in the encoding direction, that is, in a direction different from the row direction or the column direction, and error correction with high correction capability can be performed. At this time, the address of the sector is 182.
One byte is recorded on the disk every byte × 2 rows, and when 13 rows of data are recorded in one sector, sector addresses can be equally recorded in each sector.

As described above, in the first embodiment of the present invention, a product code group in which two product codes are alternately arranged for each row is formed, and these are recorded diagonally. By adopting such a configuration, it is possible to perform error correction much more resistant to burst errors than before. For example, in the first embodiment of the present invention, recording is performed in an oblique direction.
Even if a byte error occurs, the six PI codes can be corrected by performing only one-byte error correction. Even if a plurality of 6-byte errors occur, the error cannot be corrected unless they overlap in both the PI code direction and the PO code direction. In this embodiment, two product codes are interleaved as a whole, and one error is distributed to two product codes, so that the coding method has a higher correction capability.

Further, in the first embodiment of the present invention, by performing the data transfer step and the one-side traveling step,
By combining two product codes and recording diagonally, the address address of the sector is 182 bytes.times.2 rows, that is, at equal intervals, while exhibiting an error correction capability much more resistant to burst errors than in the past. It is recorded and one address can be read periodically for each sector.

On the other hand, the conventional product code (10 in FIG. 1)
1) If the data is recorded in the row direction,
When a burst error occurs, the PI code in the corresponding row is corrected
Become impossible. This means that the PI code is a 10 byte PI parity.
Error, up to 5 bytes of error
This is because only corrections can be made. 1 error of 6 bytes or more
If 7 or more occur and overlap in the PO code direction, the entire product code
May be uncorrectable.

As described above, in the first embodiment of the present invention, when combining two product codes and recording them in an oblique direction, a plurality of second product codes after parity row interleaving are used. By performing a data transposition step of exchanging rows and columns within each square area, and a one-sided cyclic step, without changing the encoding method of the product code itself, that is, a configuration having high compatibility In addition, by adopting such a configuration, while exhibiting an error correction capability that is much more resistant to burst errors than before,
An error correction encoding method capable of periodically reading one address per sector has been described.

It should be noted that the fact that addresses are recorded at regular intervals and for each sector means that there is no means for knowing the current position of the optical head other than the addresses recorded periodically, for example, a ROM. This is a very important point in a disk, and if recording is not performed periodically or addresses are recorded only at intervals larger than a sector, the performance of the apparatus is deteriorated mainly in search performance. According to this embodiment, it is possible to record addresses periodically and for each sector while improving the correction capability.

In the first embodiment of the present invention, a parity row interleaving step, a data transposition step, a one-side cyclic step, a second product code step, and a first product code stored in a memory are performed. The encoding was performed in the order of the oblique readout step and the oblique readout step. However, instead of performing the steps one by one, all the steps are executed collectively, and the reading process is performed on the first product code stored in the memory so as to be finally equivalent to executing the above steps. May be performed.

The encoding of the first product code itself in the first embodiment is equivalent to that of the conventional DVD product code, and it goes without saying that it can be realized by the conventional product code generation method.

FIG. 7 is an external view of an optical disk according to the second embodiment of the present invention.

In FIG. 7, reference numeral 701 denotes an optical disk;
Reference numeral 2 denotes encoded data recorded on a spiral or concentric track of the optical disc 701. The encoded data 702 in the present embodiment records the error correction code of the first embodiment. On an optical disc, data is recorded as uneven pits or light and dark dots made of a phase change material. Generally, at the time of recording, encoded data is digitally modulated by a modulation code such as 8/16 modulation and then recorded on a disk track. Here, the modulation by the modulation code, the sync mark for data synchronization, and the like are omitted, and a state in which the encoded data is recorded as it is is shown.

The second product code group in the first embodiment is recorded on the disk in the order read out diagonally. One sector is composed of 182 symbols × 13,
One second product code group is recorded in 32 sectors. The address is recorded every 182 symbols × 2 = 362 symbols from the head of each sector, and the address in sector units is recorded periodically. In FIG. 7, the first byte and the second byte of the address are recorded in 703 and 704 of the first sector. 705 is the address of the first byte of the second sector.

In the optical disk according to the second embodiment of the present invention, by recording the encoded data shown in the first embodiment, even if a large burst error occurs in the recording direction, the recording direction is the product code. Since the two encoding directions are different from each other, it is possible to prevent the codes in the two directions of the product code from being uncorrectable, realize strong correction capability against burst errors, and achieve highly reliable error correction. , One address can be read periodically per sector.

FIG. 8 is a flowchart showing a correction algorithm of the error correction method according to the third embodiment of the present invention. In the present embodiment, a method of correcting an error correction code according to the first embodiment will be disclosed. (Diagonal writing step) Step 801: First, the reproduction data is stored in the RAM in a diagonal direction of 411 rows × 18.
This is stored as a two-column second product code group. At the time of storage, similarly to the oblique reading step of the first embodiment,
When it reaches the bottom of the line, it returns to the first line and stores it. Second
Are equivalent to 601 in FIG. (Product code group division step) Step 802: Second
Of the product code group 506 of the
, And a fourth product code 502.
This corresponds to the reverse process of the second product code group generation step of the first embodiment shown in FIG. (One-sided traveling step) Step 803: Third and fourth steps
Is divided into 13 rows × 13 columns square area,
Are shifted by six rows in the column direction to generate a third product code. In the one-sided cyclic step of the present embodiment, a process of shifting six rows in the direction opposite to the one-side cyclical step of the first embodiment and returning to the original state is performed. This is shown in FIG.
Corresponds to the reverse of the one-sided cyclic step of the first embodiment shown in FIG.

In the case where the upper six rows are replaced with the next six rows at the time of encoding instead of shifting by six rows, the same replacement processing is performed in this step. (Data transposition step) Step 804: Next, the rows and columns in each square area of the two third product codes are exchanged to generate two second product codes. This step is a reverse process of the data transfer step of the first embodiment, and corresponds to the conversion from FIG. 3 to FIG. 2, and the second product code corresponds to the product code 201 in FIG. (Parity row deinterleaving step) Step 80
5: Next, the second product code is sequentially arranged in the memory area next to the 192 rows of data, with the last one row being a parity row for every 13 rows, to generate a first product code. The first product code corresponds to the product code 101 in FIG. (Error Correction Step) Step 806: Finally, error correction of the first product code is performed. The error correction of the product code is performed in the same manner as the error correction of the conventional product code, using the repeated correction of the PO and PI codes and the erasure correction together.

According to the above-described correction algorithm, the error correction of the error correction code shown in the first embodiment is performed.
In the error correction method according to the third embodiment of the present invention, even if a large burst error occurs in the recording direction, the recording direction is different from the two encoding directions of the product code. There are two types of codes that have strong correction capability, exhibit strong correction capability, and can perform highly reliable error correction. Further, when reproducing data, it is possible to realize an optical disk error correction method capable of periodically reading one address for each sector.

In the third embodiment of the present invention, each of the steps 801 to 805 has been described as an independent step. However, as in the first embodiment, the first product code is directly formed from the reproduced data. Needless to say, it can be realized by a direct writing step of storing the data in a memory.

FIG. 9 shows the configuration of an error correction coding circuit according to the fourth embodiment of the present invention. In this embodiment,
An error correction encoding circuit that encodes the error correction code shown in the first embodiment will be described.

In FIG. 9, reference numeral 901 denotes an entire error correction coding circuit; 902, a semiconductor memory; RA used as a working memory of the error correction coding circuit 901;
M and 903 are bus / memory control circuits for controlling the recording and reproduction of the RAM 902 and the internal bus 910, and 904 is an input IF control circuit for inputting data to be recorded on the disk medium to the error correction circuit. Handshake control circuit, ATAPI and SCSI
Protocol control circuit. Reference numeral 905 denotes an encoding circuit for the first product code.
A PI code encoding circuit 908 for adding 0-byte PI parity to each row, and a 16-byte PI parity for 192 bytes of data.
It comprises a PO encoding circuit 907 for adding a PO parity of bytes to each column. 906 collectively executes the parity row interleaving step, the data transposition step, the data transposition step, the one-side cyclic step, the second product code group generation step, and the oblique reading step in the first embodiment, and executes the second product The RAM 9 is read in the reading order equivalent to the case where the code groups are read obliquely.
This is an output IF control circuit that reads each symbol from H.02 and sends it to the modulation circuit as error-correction-coded data 912. The output IF control circuit 906 includes an address generation circuit 913 that implements the direct read step in the first embodiment, and also performs IF control with the modulation circuit. 909
Is an overall control circuit for controlling the entire error correction encoding circuit 901 and is constituted by a microcontroller or the like.

All the encodings of the PO encoding circuit 907 and the PI encoding circuit 908 are Re
This is ed-Solomon encoding, and the encoding itself, including product encoding, can be configured by a well-known Reed-Solomon encoding circuit for DVD.

The operation of the error correction coding circuit according to the fourth embodiment of the present invention will now be described.

The user data 911 sent from the host microcomputer or the MPEG encoder is input I
F control circuit 904 and bus / memory control circuit 903
Are stored in the RAM 902 in a matrix of 192 rows × 172 columns.

First, PI encoding is performed on the stored user data by the PI encoding circuit 908, and a 10-byte PI parity is added to each row. Next, PO encoding is performed by a PO encoding circuit 907, and an 11-byte PO parity is added to each column. The product code encoding circuit 905 generates a first product code by the above processing.

This product code is output to the output IF control circuit 9
The address generation circuit 913 of 06 generates an address for the RAM 902 equivalent to the direct reading step of the first embodiment, reads out each symbol from the RAM 902, and sends out the symbols to the modulation circuit. Will be recorded. The overall control described above is performed by the overall control circuit 909.

FIG. 10 is a detailed block diagram of the address generation circuit 913. In FIG. 10, reference numerals 1001 and 1002 denote two-dimensional counters for reading a second product code group in an oblique direction. The X counter generates an address in a row direction, that is, a column address. Is a Y counter. Reference numeral 1003 denotes a circuit for converting between the second product code group and the two product codes, and a circuit for converting between the product code group and the product code (shown as a “product code group <−> product code conversion circuit”); Is a 6-row shift circuit for performing conversion between the fourth product code and the third product code, 1006 is a selector, 1007 is an X / Y switching circuit for replacing rows and columns in a square area, and 1008 is a parity row. It is an interleave circuit.

The operation of the address generation circuit configured as described above will be described below.

The address generation circuit converts the two first product codes stored in the RAM 902 through the series of encoding steps shown in the first embodiment, and finally, in the second product code group. In order to directly generate an address to be read in the oblique direction, the process is performed by sequentially going back through each step from the address as the second product code group and converting the addressing method, here, the addressing.

First, an X address and a Y address are generated by a two-dimensional counter, an X counter 1001 and a Y counter 1002 in order to finally read in the second product code group in an oblique direction. X counter 1001 and Y
The initial values of the counters 1002 are both 0, and if they are labeled (X address, Y address), 602 in FIG.
Addresses are generated in the order of (0, 0), (1, 1), (2, 2), etc. Then, 603 generates (0, 1), (1,
2), (2, 3)... In addition, in order to generate addresses corresponding to 605 and 606, the Y counter 1002 includes a clear circuit that returns to 0 after the value of 415. The above X counter 100
1. The Y counter 1002 can be composed of a general counter capable of setting an initial value and simple logic.

Next, the X address X and the Y address generated in the oblique direction by the second product code are
To perform conversion between a product code group of two and two product codes,
The product code group <−> is input to the product code conversion circuit 1003. Here, when the Y address is an even number, it is a third product code, and when the Y address is an odd number, it is a fourth product code. For example, the second
, And the two-dimensional address in each of the third and fourth product codes is [X address, Y address].
0) is the third product code [0,0], (1,1) is the fourth product code [0,1], and (2,2) is the fourth product code [1,4]. , The least significant bit of the X address is assigned to two product codes, and the other bits except the least significant bit are used as the X address in the product code.

Next, in the address conversion circuit 1004, not the two-dimensional X and Y addresses of the whole product code but the number for distinguishing each 13 × 13 square area and the square area In the form of a two-dimensional address.

It is clear that the product code group <-> product code conversion circuit 1003 and the address conversion circuit 1004 can be constituted by simple logic circuits.

Next, the Y address 1012 in the square area
Is input to a 6-row shift circuit 1005, and an address conversion for performing a 6-row shift operation in a square area is performed. Six-row shift circuit 1005 can be formed by an adder and a modulo circuit.

Next, only when the address within the square area (X) and the symbol corresponding to the fourth product code, the selector 1
The address (Y) in the square area, which is selectively shifted by six rows in 006, is input to the X, Y switching circuit 1007.

The X / Y exchange circuit 1007 is a circuit for exchanging rows and columns, and can be constituted by merely exchanging the wiring. The main address of the square area number 1010 and the X / Y exchange circuit 1007 is the second address. The product code is addressed in the form of a square area number and a two-dimensional address within the area.

Finally, the parity row interleave circuit 10
At 08, the address addressed by the second product code is converted to addressing by the first product code. This processing can be configured with a circuit equivalent to the parity row interleave circuit in the existing DVD. Further, here, an address conversion circuit 1009 for converting the address of the second product code, which has been addressed in the form of a square area number and a two-dimensional address in the area, into addressing for the entire product code is included. The address conversion circuit 1009 can be constituted by a simple logic circuit.

As described above, the address addressed as the second product code group is converted to the addressing as the first product code. Then, by reading out each symbol stored in the memory 902 as the first product code in accordance with the address of the address generation circuit 913,
Processing equivalent to sequentially executing a series of steps of the parity row interleaving step, the data transposition step, the one-side cyclic step, the second product code group generation step, and the diagonal read step shown in the first embodiment is sequentially performed. Can be executed collectively.

As described above, in the error correction encoding circuit according to the fourth embodiment of the present invention, even if a large burst error occurs in the recording direction, the recording direction is different from the two encoding directions of the product code. Since the direction is the same, the code in the two directions of the product code is prevented from being uncorrectable, and a strong correction capability against a burst error is realized, thereby enabling highly reliable error correction. It becomes possible to perform error correction coding on an optical disk capable of periodically reading one address per sector.

FIG. 11 is a configuration diagram of an error correction circuit according to the fifth embodiment of the present invention. In the present embodiment, an error correction circuit that performs the error correction of the error correction code shown in the first embodiment and that implements the error correction method shown in FIG. 8 is disclosed.

In FIG. 11, reference numeral 1101 denotes an entire error correction circuit; 1102, a RAM used as a working memory of the error correction circuit 1101;
Reference numeral 103 denotes recording / reproduction control to the RAM 1102 and the internal bus 1
A bus / memory control circuit 1100 controls an output IF control circuit 1104 for outputting error-corrected user data, and is a handshake circuit with an MPEG decoder and a protocol control circuit such as ATAPI and SCSI. Reference numeral 1105 denotes a product code error correction circuit, which includes a PI code error correction circuit 1108 for correcting a PI code obtained by adding a 10-byte PI parity to 172 bytes of data for each row, and a PI code error correction circuit 1108 for 192 bytes of data. 16
It is composed of a PO code error correction circuit 1107 for correcting an error of a PO code to which a PO parity of a byte is added for each column. 1106 stores the reproduction data in FIG.
The parity rows are deinterleaved from step 801 of storing diagonally above as a second product code group,
An input IF control circuit for directly storing the reproduced data in the form of the first product code in the RAM 1102, including an address generation circuit 1113 for collectively performing up to step 805 for generating the product code of Also performs IF control.
Reference numeral 1109 denotes an overall control circuit for controlling the entire error correction circuit 1101, which is constituted by a microcontroller or the like.

The PO code error correction circuit 110
7, and each error correction circuit of the PI code error correction circuit 1108 is an error correction of a Reed-Solomon code, and the error correction itself includes error correction as a product code.
It can be composed of a well-known Reed-Solomon error correction circuit of DVD.

The operation of the error correction circuit according to the fifth embodiment of the present invention will now be described.

Reproduction data 1 reproduced from a disk medium
1 via the input IF control circuit 1106 and the bus / memory control circuit 1103.
The product code corresponding to 01 is stored in the RAM 1102. In the input IF control circuit 1106, the reproduction data 11
11 are stored in the RAM 1102, the third symbol
Row address similar to the direct write step of the embodiment of
Generate and store column addresses. Address generation circuit 11
13 can be constituted by a circuit equivalent to the address generation circuit shown in FIG.

Next, error correction of the first product code stored in the RAM 1102 is executed by the product code error correction circuit 1105. First of all, PI code error correction
This is executed by the code error correction circuit 1108, and a PI parity of 10 bytes is added to each row, so that error correction of up to 5 bytes is executed. Next, error correction of the PO code is performed by the PO code error correction circuit 1107, and since a 16-byte PO parity is added to each column, error correction of up to 8 bytes is performed. Through the above processing, the error correction of the product code is executed. In the above error correction, more reliable error correction can be performed by using known repetition correction or erasure correction.

The user data of the product code for which the error correction has been performed is then output by the output IF control circuit 1104 to R
The data is read from the AM 1102 and sent to an MPEG decoding circuit or a host computer. The overall control in the above processing is performed by the overall control circuit 1109.

Although the PO code error correction circuit 1107 and PI code error correction circuit 1108 shown in FIG. 11 have been described as separate components, the circuit for decoding the Reed-Solomon code should be easy to use. Is clear.

Further, by partially sharing the error correction coding circuit of the fourth embodiment of the present invention and the error correction circuit of the fifth embodiment, the error correction coding /
It is also clear that the correction circuit can be easily configured.

As described above, in the error correction circuit according to the fifth embodiment of the present invention for performing error correction of the error correction code shown in the first embodiment, even if a large burst error occurs in the recording direction, Is in a direction different from the two encoding directions of the product code, so that the codes in the two directions of the product code are prevented from being uncorrectable, realize a strong correction capability against burst errors, and have a high reliability. High error correction is possible.
Further, error correction of an optical disk capable of periodically reading one address per sector can be performed.

[0086]

According to the present invention, since the product code is recorded in a direction different from the coding direction in the row and column directions, even if a large burst error occurs, the two codes of the product code cannot be corrected immediately. It will not be. Therefore, a strong correction capability against a burst error can be realized. Further, since one address can be read periodically for each sector, the disk medium can be accessed without deteriorating the search performance. Further, the product code of the present invention is highly compatible with the conventional product code, and there is little change from the conventional method. Disappears.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a first product code of an error correction encoding method for a disk medium according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second product code in the embodiment.

FIG. 3 is a diagram showing a configuration of a third product code in the embodiment.

FIG. 4 is a diagram showing a first product code group in the embodiment.

FIG. 5 is a diagram illustrating a second product code group generation step in the embodiment.

FIG. 6 is a diagram illustrating an oblique reading step in the embodiment.

FIG. 7 is an outline view of an optical disc in a second embodiment of the present invention.

FIG. 8 is a flowchart illustrating a correction algorithm of an error correction method according to a third embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of an error correction encoding circuit according to a fourth embodiment of the present invention.

FIG. 10 is a detailed block diagram of an address generation circuit.

FIG. 11 is a diagram illustrating a configuration of an error correction encoding circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

 101 first product code 201 second product code 205 sector 206, 306, 505, 506, 507 address 307 square area 401, 402, 403 third product code 404 fourth product code 701 optical disk 703 first sector The first byte address 704 The second byte address of the first sector 705 The first byte address 913, 1113 of the second sector Address generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 572 G11B 20/18 572C 572F 576 576F H03M 13/27 H03M 13/27 13/29 13/29 (72) Inventor Makoto Usui 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroyuki Yabuno 1006 Odaka, Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. 1006, Kadoma, Kadoma, Fumonma-shi Matsushita Electric Industrial Co., Ltd. (72) Inventor Ryoji Kobayashi 1006, Kadoma, Kadoma, Osaka, Japan Matsushita Electric Industrial Co., Ltd. Denki Sangyo Co., Ltd. (72) Inventor Shigeki Taira 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa (72) Inventor Osamu Kawamae 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Japan Digital Media Development Division, Hitachi, Ltd. (72) Inventor Taku Hoshizawa Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa 292 Hitachi Media, Ltd. Digital Media Development Division F-term (reference) 5B001 AA02 AA13 AB02 AC05 AD04 AE04 5D044 AB05 AB07 BC03 CC06 DE03 DE68 DE83 EF03 FG10 5J065 AA03 AC03 AD02 AG06 AH01 AH06

Claims (18)

[Claims] An error correction coding method for a disk medium for performing error detection and correction coding for error detection and correction of user data arranged in a matrix, wherein data is double-corrected in row and column directions. A product code generating step of generating a first product code of (s × m) rows × (s × n) columns by encoding and storing the first product code in a memory; A parity row interleaving step of alternately arranging the parity of the data (s-1) row by row for each row of data (s-1) to generate a second product code; Split,
A data transposing step of generating a third product code in which the rows and columns in each of the square areas are exchanged, and forming a first product code group by setting the third product code in pairs of two. A one-side cyclic step of cyclically shifting each row of each square area of one of the third product codes in the first product code group by a predetermined number of rows in a column direction to generate a fourth product code; The third product code and the fourth product code in the first product code group are alternately arranged for each row to obtain 2 × (s × m) rows × (s
× n) a second product code group generating step of generating a second product code group of columns, and a diagonal reading step of reading the second product code group in a diagonal direction. An error correction encoding method, wherein the information is recorded on the disk medium in the following order. 2. The method according to claim 1, wherein the parity row interleaving step, the data transposition step, the one-side cyclic step, the second product code group generation step, and the oblique reading step are constituted by a single direct reading step. The error correction coding method according to claim 1, wherein 3. The first product code is 208 rows × 182
A matrix matrix product code of columns, 16 bytes × 182 columns of PO parity in the row direction, and 10 bytes × 208 rows of PI in the column direction
The error correction coding method according to claim 1, wherein parity is added, and the square area includes 13 rows × 13 columns. 4. The method according to claim 1, wherein in the first product code, the user data is divided into sectors every s rows, and a sector address is recorded at the head of the user data in each sector. Item 4. The error correction encoding method according to any one of Items 1 to 3. 5. An optical disc in which user data arranged in a matrix is error-correction-coded for error detection and correction and recorded, wherein the data is double-error-corrected in the row and column directions (s × m) a product code generating step of generating a first product code of rows × (s × n) columns and storing the generated product code in a memory; and a parity of m rows with respect to a column direction code of the first product code, s-1) a parity row interleaving step of alternately arranging one row per row to generate a second product code; and dividing the second product code into a square area of s rows × s columns.
A data transposing step of generating a third product code in which the rows and columns in each of the square areas are exchanged, and forming a first product code group by setting the third product code in pairs of two. A one-side cyclic step of cyclically shifting each row of each square area of one of the third product codes in the first product code group by a predetermined number of rows in a column direction to generate a fourth product code; The third product code and the fourth product code in the first product code group are alternately arranged for each row to obtain 2 × (s × m) rows ×
An error correction encoding method comprising: a second product code group generating step of generating a second product code group of (s × n) columns; and a diagonal reading step of reading the second product code group in a diagonal direction. An optical disc, wherein the generated second product code group is recorded. 6. The method according to claim 1, wherein the parity row interleaving step, the data transposition step, the one-side cyclic step, the second product code group generation step, and the oblique reading step are constituted by a single direct reading step. The optical disk according to claim 5, wherein 7. The first product code is 208 rows × 182
A matrix matrix product code of columns, 16 bytes × 182 columns of PO parity in the row direction, and 10 bytes × 208 rows of PI in the column direction
7. The optical disk according to claim 5, wherein parity is added, and the square area is formed of 13 rows × 13 columns. 8. The method according to claim 1, wherein in the first product code, the user data is divided into sectors every s rows, and a sector address is recorded at the head of the user data in each sector. 8. The optical disk according to any one of 5 to 7. 9. The error correction method for a disk medium recorded on an optical disk according to claim 5, wherein the reproduction data read from the disk medium is set to a 2 × (s) as a second product code group. (Xm) a diagonal writing step of storing diagonally in a matrix memory of (rows) × (s × n) columns; and two m rows by alternately dividing the stored second product code group for each row. A product code group dividing step of dividing the product code group into × n columns of third and fourth product codes; and dividing the third and fourth product codes into s rows × s columns of square areas, Each row of each square area of
By cyclically shifting by a predetermined number of rows in the column direction,
A one-side cyclic step of converting the fourth product code into a product code having the same structure as the third product code; and a third product code converted from the fourth product code and the product code group dividing step. A data transposing step of generating two second product codes by exchanging rows and columns in each square area of s rows × s columns of the directly generated third product code; Parity row deinterleaving for generating a first product code by sequentially arranging the last one row every s rows of product code data as a parity row in a memory area next to (s-1) × m rows of data And an error correction step of performing error correction on the first product code. 10. The diagonal writing step, the product code group division step, the one-side cyclic step, the data transposition step, and the parity row deinterleaving step
10. The method according to claim 9, comprising a single direct write step. 11. The first product code is 208 rows × 18
A two-column matrix product code, 16 bytes x 182 in the row direction
Column PO parity, 10 bytes in column direction x 208 rows of P
I parity is added, and the square area is 13
The error correction method for a disk medium according to claim 8, wherein the error correction method is configured by rows × 13 columns. 12. An error correction coding circuit for performing error detection and correction coding for error detection and correction of user data arranged in a matrix, comprising: A product code generating means for generating a first product code of (s × m) rows × (s × n) columns and storing the generated product code in a memory; Parity row interleaving means for alternately arranging the data (s-1) rows one by one to generate a second product code; and dividing the second product code into a square area of s rows × s columns.
Data transposing means for generating a third product code in which the rows and columns in each of the square areas are exchanged; and forming a first product code group by grouping the third product codes in pairs. One-side cyclic means for cyclically shifting each row of each square area of one of the third product codes in the first product code group by a predetermined number of rows in a column direction to generate a fourth product code; The third product code and the fourth product code in the first product code group are alternately arranged for each row to obtain 2 × (s × m) rows × (s
× n) a second product code group generating means for generating a second product code group of a column; and a diagonal reading means for reading the second product code group in a diagonal direction. An error correction coding circuit characterized by having. 13. The parity row interleaving means, the data transposing means, the one-side cyclic means, the second product code group generating means, and the oblique reading means are constituted by a single direct reading means. The error correction encoding circuit according to claim 12, wherein 14. The first product code is 208 rows × 18
A two-column matrix product code, 16 bytes x 182 in the row direction
Column PO parity, 10 bytes in column direction x 208 rows of P
I parity is added, and the square area is 13
14. The error correction coding circuit according to claim 12, wherein the error correction coding circuit is constituted by rows × 13 columns. 15. In the first product code, user data is divided into sectors every s rows, and a sector address is recorded at the head of the user data in each sector. 15. The error correction encoding circuit according to any one of 12 to 14. 16. An error correction circuit for a disk medium recorded on an optical disk according to claim 5, wherein reproduced data read from the disk medium is set as a second product code group by 2 × A diagonal writing means for storing diagonally in a (s × m) row × (s × n) column matrix memory, and the stored second product code group is divided alternately for each row and a product code group dividing unit that divides the product code into third and fourth product codes of m rows × n columns; and divides the third and fourth product codes into a square area of s rows × s columns. Each row of each square area of the product code is
By cyclically shifting by a predetermined number of rows in the column direction,
A one-side cyclic means for converting the fourth product code into a product code having the same structure as the third product code; and a third product code converted from the fourth product code and the product code group dividing means. Data transposing means for generating two second product codes by exchanging rows and columns in each square area of s rows × s columns of the directly generated third product code; Parity row deinterleaving for generating a first product code by sequentially arranging the last one row every s rows of product code data as a parity row in the memory area next to (s-1) × m rows of data Means, and error correction means for performing error correction on the first product code. 17. The method according to claim 17, wherein the diagonal writing means, the product code group dividing means, the one-side cyclic means, the data transposing means, and the parity row deinterleaving means are constituted by a single direct writing means. The error correction circuit according to claim 16. 18. The first product code is 208 rows × 18
A two-column matrix product code, 16 bytes x 182 in the row direction
Column PO parity, 10 bytes in column direction x 208 rows of P
I parity is added, and the square area is 13
The error correction circuit according to claim 16, wherein the error correction circuit is configured by rows × 13 columns.