JP2002325354A - Rush current inhibiting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain, using a simple configuration, consumption electric current at a steady state, while securing sufficient electric current capacity, in a device 31 that inhibits rush current at supplying of power. SOLUTION: A latching relay 36 is employed as a mechanical relay, which is connected mutually in parallel with an SSR 35, that is capable of inhibiting rush electric current, while the latching relay 36 is brought into conduction and driven by the output current of SSR 35. This results in the rush current to be subsided at the time of the latching relay 36 being brought into conduction, through the use of operation time of both SSR 35 and the latching relay SSR 36, thereby eliminating the risk of fusing of contact points, thus realizing a highly reliable operation, and further eliminating the problems of heat generation and heat loss in steady state, and enabling securing of sufficient electric current capacity. This is realized further by a simple configuration which does not employ special structures, such as loaded electric current detectors, thermal sensors, or control circuits for the latching relay 36, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for suppressing an inrush current generated after power is turned on.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a schematic configuration of a typical prior art inrush current suppressing device 1. As shown in FIG. The inrush current suppression device 1 is interposed in series on a power supply line 4 from an AC power supply 2 to a load 3. This inrush current suppressing device 1
Is a power-on switch 5 and a solid-state relay (hereinafter referred to as SSR) 6 connected in series with each other.
Are provided in series with the power supply line 4 and include a limiting resistor 7 provided in parallel with the SSR 6. In the inrush current suppressing device 1, the switch 5 and the SSR 6 are controlled by individual control circuits (not shown). When the switch 5 is turned on, the generated inrush current is controlled by the limiting resistor 7, and the steady-state load current is SSR.
6 is controlled.

FIG. 11 is a block diagram showing a schematic configuration of another inrush current suppression device 11 according to the prior art. The inrush current suppression device 11 is provided with an SSR or a posistor 12 for performing a zero-cross operation on the power supply line 4 (in FIG. 11, it is a posistor). are doing.

FIG. 12 is a block diagram showing a schematic configuration of still another inrush current suppressing device 21 according to the prior art. The inrush current suppressing device 21 is disclosed in, for example,
The mechanical relay is similar to that disclosed in Japanese Patent Application Laid-Open No. 256908 and Japanese Patent Application Laid-Open No. H11-98683, in which a series circuit of a limiting resistor 7 and an SSR 6 is interposed in the power supply line 4 and the series circuit is short-circuited. 22 are provided. When the power is turned on, the limiting resistor 7 and the SSR or triac 6 (FIG. 12) are controlled by an SSR control circuit (not shown).
In the steady state, the control circuit 23 controls the load current with the mechanical relay 22. In JP-A-11-98683, FIG.
Although not shown in FIG. 2, a load current detector is provided, and the detection result is input to the control circuit 23.
Further, in Japanese Patent Application Laid-Open No. 8-256908, information from a load 3 such as a temperature sensor or an operation unit as shown in FIG.

[0005]

In the inrush current suppressing devices 1 and 11 of the prior art as described above, since the steady load current is controlled by the SSR, the ambient temperature is, for example, 40.degree. As described above, when controlling a current of 2 A or more, there is a problem that a heat sink of a considerable size must be attached as necessary, such as an external heat sink. There is also a problem that the loss is large.
Furthermore, in the inrush current suppression device 11, the posistor 12
In the case where the control is performed by the above-mentioned method, there is a problem that the load current of the posistor 12 that can be controlled capacitively is limited.

On the other hand, the inrush current suppressing device 21 uses the limiting resistor 7 and the SSR or the triac 6 only when the power is turned on. In this case, the load current detector and the like are required, and the control circuit 23 has a complicated structure for determining whether or not the load current exceeds a specified value when the power is turned on. Also, the control circuit 23 has a problem in that the control circuit 23 has a complicated configuration for processing information from a temperature sensor, an operation unit, and the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inrush current suppressing device which can suppress current consumption in a steady state with a simple configuration and can obtain a sufficient current capacity.

[0008]

A rush current suppressing device according to the present invention is a rush current suppressing device comprising a semiconductor device capable of suppressing an inrush current and a mechanical relay connected in parallel with each other, The mechanical relay includes a latching relay, and the latching relay is conductively driven by an output current of the semiconductor device.

According to the above configuration, the output current to the load rises by the operation of the semiconductor device, and the output current drives the latching relay to be conductive.
Once conductive, the conductive state is latched. Therefore, by utilizing the operation time of the semiconductor device and the operation time of the latching relay, for example, 50 μsec
When the semiconductor device is turned on after the operation time of the semiconductor device has reached about 10 msec, and the latching relay is turned on after the operation time of the latching relay has been about 10 msec, the rush current has converged at that time.

Therefore, even if the semiconductor device and the latching relay are provided in parallel with each other, the latching relay can be operated while avoiding a severe cycle of an inrush current,
There is no risk of contact welding, and highly reliable operation can be realized. In the steady state, the load current is controlled by the mechanical type latching relay, and a current flows between the input and output terminals of the semiconductor device. Does not flow, for example, even for a relatively large load current of 2 A or more, there is no problem of heat generation and loss, and a sufficient current capacity can be secured.
Further, the present invention can be realized with a simple configuration without using a special configuration such as a load current detector, a temperature sensor, and a control circuit for driving a latching relay.

Further, the inrush current suppressing device according to the present invention is an inrush current suppressing device in which a semiconductor device capable of suppressing an inrush current and a mechanical relay are connected in parallel with each other. A control circuit responsive to the operation output and for conducting the mechanical relay after a predetermined time has elapsed is provided.

According to the above configuration, the inrush current due to power-on is suppressed by the semiconductor device, and after the operation of the semiconductor device, the mechanical relay is turned on by the control circuit at a point in time when the inrush current converges. It is driven and its state is maintained. Therefore, even if a normal mechanical relay is used, the operation with high reliability can be realized, and there is no problem of heat generation and loss, and a sufficient current capacity can be secured. And it can be realized with a simple configuration without using a special configuration such as a load current detector or a temperature sensor.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 7.

FIG. 1 is a block diagram showing a schematic configuration of an inrush current suppressing device 31 according to one embodiment of the present invention. The inrush current suppression device 31 is provided by an AC power supply 32 and a load 33.
To the power supply line 34 in series. It should be noted in the present invention that the inrush current suppression device 31 is configured by connecting an SSR 35, which is a semiconductor device capable of suppressing inrush current, and a latching relay 36, which is a mechanical relay, in parallel with each other, That is, the latching relay 36 is conductively driven by the output current of the SSR 35. Note that the S
A limiting resistor 37 may be connected in series to the SR 35 as shown by the rush current suppressing device 31a in FIG.

FIG. 3 shows that the load 33 is 100 V / 1
FIG. 7 is a waveform diagram showing a change in load current when a 00 W lamp load is connected directly to a 100 V / 60 Hz AC power supply 32 without using an inrush current suppressing device. It is understood from FIG. 3 that the inrush current substantially converges in a half cycle to one cycle.

On the other hand, the operation time of SSR 35 is, for example, about 50 μsec, and the operation time of latching relay 36 is, for example, about 10 msec. Therefore, when the SSR 35 is turned on and the latching relay 36 is turned on with the output current, the rush current has substantially converged at that point. Then, once conducting, the latching relay 36 latches the conduction state.

Therefore, even if the SSR 35 and the latching relay 36 are provided in parallel with each other, the latching relay 3
6 can be operated while avoiding a severe cycle of inrush current, and there is no fear of welding of contacts, and highly reliable operation can be realized. In a steady state, the load current is controlled by a latching relay 36 which is a mechanical relay.
Since no current flows between the input / output terminals 35, there is no problem of heat generation or loss even for a relatively large load current of, for example, 2 A or more, and a sufficient current capacity can be secured. Then, it can be realized with a simple configuration without using a special configuration such as a load current detector, a temperature sensor, and a control circuit for the latching relay 36.

FIG. 4 is a diagram for explaining an example of the configuration of the SSR 35. As shown in FIG. In the example of FIG.
1, a photo triac 42, and an infrared light emitting diode 43, a non-zero cross built-in type SSR
In this case, since the triac 41 is turned on at an arbitrary phase, it is desirable to combine the triac 41 with the limiting resistor 37. A triac 41 is interposed between the terminals P1 and P2 to control the load current. Triac 41
A phototriac 42 is connected to the gate terminal of the SSR 35. When an input signal from the control circuit for the SSR 35 is input between the terminals P3 and P4, not shown in FIG. 43 lights up, the photo triac 42 turns on, and the triac 41
Can be turned on.

FIG. 5 is an equivalent circuit diagram of the phototriac 42. A series circuit of a P-type transistor Q1 and a gate resistor R1 is connected between the terminals P11 and P12, the base of the transistor Q1 is connected to the collector of an N-type phototransistor Q2, and the collector is the base of the transistor Q2. And the gate resistor R1. Similarly, a series circuit of a P-type transistor Q3 and a gate resistor R2 is connected between the terminals P12 and P11. The base of the transistor Q3 is connected to the collector of an N-type phototransistor Q4. Connected to the base of Q4 and gate resistor R2. Therefore, as described above, when an input signal is input between the terminals P3 and P4, the infrared light emitting diode 43
Lights up, the photo triac 42 is turned on, the triac 41 is turned on, and the portion between the terminals P11 and P12 is turned on.

FIG. 6 is a diagram for explaining another example of the configuration of the SSR 35. As shown in FIG. Parts similar to those in the configuration of FIG. 4 described above are denoted by the same reference numerals, and description thereof will be omitted. This example is an SSR with a built-in zero cross, and a zero cross circuit 44 is provided at the gate terminal of the triac 41. FIG. 7 is an equivalent circuit diagram of the phototriac 42 and the zero-cross circuit 44. F is connected between the base and the emitter of each of the transistors Q2 and Q4.
ETQ5, Q6 are provided, and their FET Q
The gates of Q5 and Q6 are connected to each other and to the bases of the transistors Q1 and Q3.

Thus, in a state where the input signal is input and the infrared light emitting diode 43 is lit,
Near the zero phase of the power supply voltage, the transistor Q2 (Q
4) turns on, the transistor Q1 (Q3) turns on,
SSR turns on. When the power supply voltage other than the vicinity of the zero phase is equal to or higher than a certain voltage, even if the transistor Q2 (Q4) attempts to turn on, the SSR does not turn on because the FET Q5 (Q6) turns on. Thus, a zero-cross operation can be performed.

Another embodiment of the present invention will be described below with reference to FIG.

FIG. 8 is a block diagram showing a schematic configuration of an inrush current suppressing device 51 according to another embodiment of the present invention.
The inrush current suppression device 51 is similar to the inrush current suppression device 31 described above, and corresponding portions are denoted by the same reference numerals, and description thereof is omitted. In the above-described inrush current suppression device 31, the latching relay 36 is an AC-driven relay.
A C-driven latching relay 56 is used. Therefore, the diode 52 is provided in series with the SSR 35.

In still another embodiment of the present invention,
This will be described below with reference to FIG.

FIG. 9 is a block diagram showing a schematic configuration of an inrush current suppressing device 61 according to still another embodiment of the present invention. It should be noted that in this rush current suppressing device 61,
The relay 66 interposed in the power supply line 34 from the AC power supply 32 to the load 33 does not have a latching function. Therefore, a control circuit 62 is provided between the SSR 35 and the relay 66. I have. This control circuit 62
Accordingly, the relay 66 is driven to conduct when a certain time has elapsed after the operation of the SSR 35, and that state is maintained. Therefore, the relay 66 can be conductively driven at the zero-cross timing in consideration of the delay time of the SSR 35 and the relay 66.

The control circuit 62 does not need to perform complicated processing such as comparison judgment and signal processing, unlike the control circuit 23 described in the section of the prior art, and is reset when the power is turned off. The output can be derived with a simple configuration such as a timer that derives the output after the predetermined time elapses from the output and maintains the output thereafter.

It goes without saying that the inrush current suppressing devices 51 and 61 may be provided with the limiting resistor 37 as in the inrush current suppressing device 31a.

[0028]

As described above, the inrush current suppressing device of the present invention connects a semiconductor device capable of suppressing an inrush current and a latching relay, which is a mechanical relay, in parallel with each other. The output current to the load is raised by the semiconductor device, and the latching relay is conductively driven by the output current.

Therefore, due to the response delay of the semiconductor device and the latching relay, the rush current substantially converges at the time of the conduction of the latching relay. It is possible to operate while avoiding severe cycles of current, there is no risk of welding of contacts, and it is possible to realize highly reliable operation, and at the time of steady state, load current is supplied by the latching relay which is a mechanical relay. Since no current flows between the input and output terminals of the semiconductor device, there is no problem of heat generation or loss even for a relatively large load current, and a sufficient current capacity can be secured. Furthermore, the present invention can be realized with a simple configuration without using a special configuration such as a load current detector, a temperature sensor, and a control circuit for driving a latching relay.

Further, as described above, the inrush current suppressing device of the present invention connects a semiconductor device capable of suppressing an inrush current and a mechanical relay in parallel with each other, and immediately after the power is turned on, the load is controlled by the semiconductor device. After a predetermined time has elapsed from the operation output of the semiconductor device, the control circuit conducts and drives the mechanical relay to maintain the state.

Therefore, even if a normal mechanical relay is used, the highly reliable operation can be realized, and there is no problem of heat generation or loss, and a sufficient current capacity can be secured. Furthermore, it can be realized with a simple configuration without using a special configuration such as a load current detector or a temperature sensor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an inrush current suppression device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing another configuration example of the rush current suppressing device according to the embodiment of the present invention.

FIG. 3 is a waveform diagram showing a change in load current when a lamp load is directly connected to an AC power supply.

FIG. 4 is a diagram for explaining a configuration example of an SSR in the inrush current suppression device shown in FIGS. 1 and 2;

5 is an equivalent circuit diagram of a phototriac in the SSR shown in FIG.

FIG. 6 is a diagram for explaining another configuration example of the SSR in the inrush current suppression device shown in FIGS. 1 and 2;

FIG. 7 is an equivalent circuit diagram of a phototriac and a zero-cross circuit in the SSR shown in FIG. 6;

FIG. 8 is a block diagram illustrating a schematic configuration of an inrush current suppression device according to another embodiment of the present invention.

FIG. 9 is a block diagram showing a schematic configuration of an inrush current suppression device according to still another embodiment of the present invention.

FIG. 10 is a block diagram showing a schematic configuration of a typical conventional inrush current suppression device.

FIG. 11 is a block diagram showing a schematic configuration of another conventional inrush current suppression device.

FIG. 12 is a block diagram showing a schematic configuration of another inrush current suppression device according to the related art.

[Explanation of symbols]

 31, 31a, 51, 61 Inrush current suppressor 32 AC power supply 33 Load 35 SSR (semiconductor device) 36, 56 Latching relay (mechanical relay) 37 Limiting resistor 41 Triac 42 Phototriac 43 Photodiode 44 Zero cross circuit 52 Diode 62 Control Circuit 66 relay (mechanical relay)

Claims (2)

[Claims] 1. A rush current suppression device comprising a semiconductor device capable of suppressing rush current and a mechanical relay connected in parallel with each other, wherein said mechanical relay comprises a latching relay, Wherein the latching relay is conductively driven by the output current. 2. An inrush current suppressing device comprising a semiconductor device capable of suppressing an inrush current and a mechanical relay connected in parallel with each other, wherein a predetermined time is provided in response to an operation output of the semiconductor device. An inrush current suppression device comprising: a control circuit that drives the mechanical relay to conduct after a lapse of time.