JP2002324720A - Laminated ceramic electronic component - Google Patents

Laminated ceramic electronic component

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Publication number
JP2002324720A
JP2002324720A JP2001126594A JP2001126594A JP2002324720A JP 2002324720 A JP2002324720 A JP 2002324720A JP 2001126594 A JP2001126594 A JP 2001126594A JP 2001126594 A JP2001126594 A JP 2001126594A JP 2002324720 A JP2002324720 A JP 2002324720A
Authority
JP
Japan
Prior art keywords
ceramic
electronic component
terminal electrode
ceramic electronic
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001126594A
Other languages
Japanese (ja)
Other versions
JP4691818B2 (en
Inventor
Satoru Noda
悟 野田
Kunihiko Hamada
邦彦 浜田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2001126594A priority Critical patent/JP4691818B2/en
Publication of JP2002324720A publication Critical patent/JP2002324720A/en
Application granted granted Critical
Publication of JP4691818B2 publication Critical patent/JP4691818B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable laminated ceramic electronic component which is provided with a terminal electrode made of Cu as a conductive element and is superior in mounting substrate expansion resistance (expansion strength) and mounting substrate bending resistance (bending strength). SOLUTION: This laminated ceramic electronic component is provided with a ceramic laminated body that a plurality of ceramic layers are laminated, a plurality of internal electrodes which are formed among the ceramic layers in a manner that their end edges are exposed over any end surface of the ceramic laminated body, and a terminal electrode made of Cu as a conductive element that is electrically connected with the end edge of the internal electrode, and the Young's modulus of the terminal electrode is within 1.00×10<10> -4.00×10<10> N/m<2> .

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層セラミック電
子部品に関するもので、特に基板実装時の熱衝撃による
基板の伸縮応力や、基板に加えられる外力による撓みに
起因する応力に耐え得る機械的強度を備える、積層セラ
ミック電子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic electronic component, and more particularly to a mechanical strength capable of withstanding a stretching stress of a substrate due to a thermal shock at the time of mounting the substrate and a stress caused by a bending due to an external force applied to the substrate. A multilayer ceramic electronic component comprising:

【0002】[0002]

【従来の技術】従来より積層セラミック電子部品、例え
ば積層セラミック電子部品は、主にセラミック積層体
と、内部電極と、端子電極とからなる。セラミック積層
体は、例えば、誘電体材料を含む生のセラミック層が複
数積層された生の積層体が焼成されてなる。内部電極
は、厚さ数百nm〜数μmからなり、セラミック積層体
内の厚さ数百nm〜30μmのセラミック層間にあっ
て、複数の生のセラミック層上に導電性ペーストが印刷
され、生のセラミック層とともに同時焼成されてなり、
内部電極のそれぞれの端縁は、上述のセラミック積層体
の何れかの端面に露出するように形成されている。端子
電極は、セラミック積層体の端面に露出した内部電極の
一端に接合されるように、導電性ペーストがセラミック
積層体の端面に塗布され焼付けられてなる。
2. Description of the Related Art Conventionally, a multilayer ceramic electronic component, for example, a multilayer ceramic electronic component mainly includes a ceramic laminate, internal electrodes, and terminal electrodes. The ceramic laminate is, for example, formed by firing a raw laminate in which a plurality of raw ceramic layers containing a dielectric material are laminated. The internal electrode has a thickness of several hundred nm to several μm, is located between ceramic layers having a thickness of several hundred nm to 30 μm in a ceramic laminate, and a conductive paste is printed on a plurality of raw ceramic layers to form a raw ceramic. Co-fired with the layers,
Each edge of the internal electrode is formed so as to be exposed at any one of the end surfaces of the above-described ceramic laminate. The terminal electrode is formed by applying and baking a conductive paste to the end face of the ceramic laminate so as to be joined to one end of the internal electrode exposed on the end face of the ceramic laminate.

【0003】端子電極形成用の導電性ペーストとして
は、例えば導電成分と、有機ビヒクルと、ガラスフリッ
トを含有してなり、導電成分としては例えば金属粉末が
挙げられ、このような金属粉末としては例えばAgやP
d等の貴金属に加えて、NiやCu等の卑金属が用いら
れる。また、積層セラミック電子部品はその小型化なら
びに薄層化が進み、これに伴い内部電極形成に用いる導
電性ペーストに含有する金属粉末の微粒化が求められ
る。
A conductive paste for forming a terminal electrode contains, for example, a conductive component, an organic vehicle, and a glass frit. Examples of the conductive component include metal powder. Ag or P
Base metals such as Ni and Cu are used in addition to noble metals such as d. In addition, the multilayer ceramic electronic component has been reduced in size and thickness, and accordingly, it has been required to reduce the metal powder contained in the conductive paste used for forming the internal electrodes.

【0004】このような積層セラミック電子部品は、回
路基板やプリント配線基板等の実装基板に搭載され、該
基板上に形成されたランドと積層セラミック電子部品の
端子電極とが、はんだによって電気的かつ機械的に接合
されて面実装される。
[0004] Such a multilayer ceramic electronic component is mounted on a mounting board such as a circuit board or a printed wiring board, and a land formed on the board and a terminal electrode of the multilayer ceramic electronic component are electrically and soldered. Mechanically bonded and surface mounted.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来技
術によれば、周囲温度が急激に変化したり熱衝撃が加え
られた場合、回路基板の伸縮応力により積層セラミック
電子部品の内部にクラックを生じ易い傾向があった。ま
た、積層セラミック電子部品が回路基板上に実装されて
いるため、回路基板にかかる外力による撓みに起因する
応力が積層セラミック電子部品に加わり易く、やはり積
層セラミック電子部品の内部にクラックが生じ易い傾向
があった。特に、内部電極の導電成分としてNiを、端
子電極の導電成分としてCuを用いた積層セラミック電
子部品の場合に、顕著な傾向が見られた。
However, according to the prior art, when the ambient temperature changes abruptly or a thermal shock is applied, cracks are easily generated inside the multilayer ceramic electronic component due to the expansion and contraction stress of the circuit board. There was a tendency. In addition, since the multilayer ceramic electronic component is mounted on the circuit board, the stress due to the bending due to the external force applied to the circuit board is likely to be applied to the multilayer ceramic electronic component, and cracks tend to occur inside the multilayer ceramic electronic component as well. was there. In particular, a remarkable tendency was observed in the case of a multilayer ceramic electronic component using Ni as the conductive component of the internal electrode and Cu as the conductive component of the terminal electrode.

【0006】本発明の目的は、上述の問題点を解消すべ
くなされたもので、Cuを導電成分とする端子電極を備
え、耐実装基板伸縮性(伸縮強度)ならびに耐実装基板
曲げ性(撓み強度)に優れた、高信頼性の積層セラミッ
ク電子部品を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems. The object of the present invention is to provide a mounting substrate with a terminal electrode containing Cu as a conductive component, a mounting substrate stretch resistance (stretching strength) and a mounting substrate bending resistance (bending resistance). It is an object of the present invention to provide a highly reliable multilayer ceramic electronic component having excellent strength.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明の積層セラミック電子部品は、複数のセラミ
ック層が積層状態にあるセラミック積層体と、それぞれ
の端縁がセラミック積層体の何れかの端面に露出するよ
うにセラミック層間に形成された複数の内部電極と、内
部電極の端縁と電気的に接続されるように設けられたC
uを導電成分とする端子電極と、を備え、端子電極のヤ
ング率は、1.00×1010〜4.00×1010N/m
2の範囲であることを特徴とする。
In order to achieve the above object, a multilayer ceramic electronic component according to the present invention comprises a ceramic laminate in which a plurality of ceramic layers are stacked and a ceramic laminate in which each edge is a ceramic laminate. A plurality of internal electrodes formed between the ceramic layers so as to be exposed at the end surfaces thereof, and C provided so as to be electrically connected to the edges of the internal electrodes.
a terminal electrode having u as a conductive component, and the terminal electrode has a Young's modulus of 1.00 × 10 10 to 4.00 × 10 10 N / m.
It is characterized by being in the range of 2 .

【0008】[0008]

【発明の実施の形態】端子電極のヤング率は、微小硬度
計を用いて荷重の負荷除荷曲線を求めることにより算出
できる。この方法は、長径数μmの圧子を使って端子電
極に荷重を与える方法であり、端子電極自体のバルク作
製を行わなくとも、積層セラミック電子部品の端子電極
を直接測定することが可能である。
BEST MODE FOR CARRYING OUT THE INVENTION The Young's modulus of a terminal electrode can be calculated by obtaining a load unloading curve of a load using a microhardness tester. This method is a method in which a load is applied to a terminal electrode using an indenter having a long diameter of several μm, and it is possible to directly measure the terminal electrode of a multilayer ceramic electronic component without producing a bulk of the terminal electrode itself.

【0009】端子電極のヤング率が変動する要因として
は、導電成分であるCu材料の粒径,ガラスフリットの
組成ならびに粒径,導電性ペースト中における各材料の
含有割合、ならびに端子電極の焼付け温度や焼付け時の
雰囲気等が挙げられる。
Factors that cause the Young's modulus of the terminal electrode to fluctuate include the particle size of the Cu material as the conductive component, the composition and particle size of the glass frit, the content ratio of each material in the conductive paste, and the baking temperature of the terminal electrode. And the atmosphere at the time of baking.

【0010】Cu材料の粒径が大きく、導電性ペースト
中におけるCuの含有割合が低く、ガラスフリットの軟
化点以下の低い温度によって焼付けを行うほど、端子電
極中の空隙が多くなり、ヤング率は低下する傾向が見ら
れる。また、ガラスフリットの軟化点以上の高い温度で
焼付ける場合であっても、導電性ペースト中におけるガ
ラスフリットの含有割合が高ければ、焼付け時にガラス
がセラミック積層体の内部に浸透して、端子電極の内部
に空隙が形成され、同様にヤング率は低下する傾向が見
られる。
[0010] The larger the particle size of the Cu material, the lower the Cu content in the conductive paste, and the lower the temperature below the softening point of the glass frit, the more the baking is performed, the larger the voids in the terminal electrode, and the lower the Young's modulus. There is a tendency to decrease. Further, even when baking is performed at a temperature higher than the softening point of the glass frit, if the content ratio of the glass frit in the conductive paste is high, the glass penetrates into the inside of the ceramic laminate at the time of baking, and the terminal electrode A void is formed in the inside of the alloy, and similarly, the Young's modulus tends to decrease.

【0011】このように、端子電極のヤング率はさまざ
まな要因によって変動するが、有限要素法を用いた応力
解析の結果、積層セラミック電子部品が実装基板に搭載
される際に生じる伸縮応力や撓み応力に耐える力、すな
わち積層セラミック電子部品の端子電極の伸縮強度なら
びに撓み強度は、端子電極のヤング率が小さいほど大き
くなる傾向が認められ、本発明者らの鋭意研究の結果、
積層セラミック電子部品の端子電極のヤング率は、1.
00×1010〜4.00×1010N/m2の範囲である
場合に、もっとも伸縮強度ならびに撓み強度が強いこと
を見出した。
As described above, the Young's modulus of the terminal electrode fluctuates due to various factors. As a result of the stress analysis using the finite element method, the expansion stress and the bending stress generated when the multilayer ceramic electronic component is mounted on the mounting board. The force to withstand the stress, that is, the expansion and contraction strength and the bending strength of the terminal electrode of the multilayer ceramic electronic component tend to increase as the Young's modulus of the terminal electrode decreases, and as a result of the inventors' earnest research,
The Young's modulus of the terminal electrode of the multilayer ceramic electronic component is 1.
It was found that the elastic strength and the flexural strength were the strongest in the range of 00 × 10 10 to 4.00 × 10 10 N / m 2 .

【0012】端子電極のヤング率が4.00×1010
/m2を上回ると、上述したような伸縮強度ならびに撓
み強度向上という、本発明の効果が得られにくい。すな
わち、セラミック積層体の内部に応力が集中することに
より、クラックが生じる恐れがある。
The Young's modulus of the terminal electrode is 4.00 × 10 10 N
/ M 2 , it is difficult to obtain the effects of the present invention, ie, the improvement in the expansion and contraction strength and bending strength as described above. That is, cracks may occur due to concentration of stress inside the ceramic laminate.

【0013】他方、端子電極のヤング率が1.00×1
10N/m2を下回ると、積層セラミック電子部品の端
子電極として用いることが困難になる。すなわち、例え
ば導電性ペースト中において、粒径の大きいCu材料の
含有割合が高い場合、焼付け形成後の端子電極の内部が
ポーラスになるため、耐湿性等の信頼性に問題が生じる
恐れがある。また、例えば、導電性ペースト中における
ガラスフリットの含有割合が高い場合、ガラスが端子電
極の表面に析出して、焼付け後に端子電極上にめっき膜
を形成する場合に、めっきシール不良が生じる恐れがあ
る。
On the other hand, the Young's modulus of the terminal electrode is 1.00 × 1
If it is less than 0 10 N / m 2 , it becomes difficult to use it as a terminal electrode of a multilayer ceramic electronic component. That is, for example, when the content ratio of the Cu material having a large particle size in the conductive paste is high, the inside of the terminal electrode after baking becomes porous, which may cause a problem in reliability such as moisture resistance. Further, for example, when the content ratio of the glass frit in the conductive paste is high, when glass is deposited on the surface of the terminal electrode and a plating film is formed on the terminal electrode after baking, there is a possibility that a plating seal failure may occur. is there.

【0014】次に、本発明の積層セラミック電子部品の
一つの実施形態について、図1に基づいて詳細に説明す
る。すなわち、セラミック電子部品1は、セラミック積
層体2と、内部電極3,3と、端子電極4,4と、めっ
き膜5,5とから構成される。
Next, one embodiment of the multilayer ceramic electronic component of the present invention will be described in detail with reference to FIG. That is, the ceramic electronic component 1 includes the ceramic laminate 2, the internal electrodes 3 and 3, the terminal electrodes 4 and 4, and the plating films 5 and 5.

【0015】セラミック積層体2は、BaTiO3を主
成分とする誘電体材料からなるセラミック層2aが複数
積層された生のセラミック積層体が焼成されてなる。
The ceramic laminate 2 is formed by firing a green ceramic laminate in which a plurality of ceramic layers 2a made of a dielectric material containing BaTiO 3 as a main component are laminated.

【0016】内部電極3,3は、セラミック積層体2内
のセラミック層2a間にあって、複数の生のセラミック
層2a上に導電性ペーストが印刷され、生のセラミック
積層体と同時焼成されてなり、内部電極3,3のそれぞ
れの端縁は、セラミック積層体2の何れかの端面に露出
するように形成されている。
The internal electrodes 3, 3 are located between the ceramic layers 2a in the ceramic laminate 2, and a conductive paste is printed on the plurality of green ceramic layers 2a and fired simultaneously with the green ceramic laminate. Each edge of the internal electrodes 3 is formed so as to be exposed at any end face of the ceramic laminate 2.

【0017】端子電極4,4は、セラミック積層体2の
端面に露出した内部電極3,3の一端と電気的かつ機械
的に接合されるように、上述したCuを導電成分とする
導電性ペーストがセラミック積層体2の端面に塗布され
焼付けられてなる。
The terminal electrodes 4 and 4 are made of a conductive paste containing Cu as a conductive component so as to be electrically and mechanically joined to one ends of the internal electrodes 3 and 3 exposed on the end faces of the ceramic laminate 2. Is applied to the end face of the ceramic laminate 2 and baked.

【0018】めっき膜5,5は、例えば、SnやNi等
の無電解めっきや、はんだめっき等からなり、端子電極
4,4上に少なくとも1層形成されてなる。
The plating films 5 and 5 are made of, for example, electroless plating of Sn or Ni, solder plating, etc., and are formed on the terminal electrodes 4 and at least one layer.

【0019】なお、本発明のセラミック電子部品のセラ
ミック積層体2の材料は、上述の実施形態に限定される
ことなく、例えばPbZrO3等,その他の誘電体材
料,絶縁体,磁性体,圧電体ならびに半導体材料からな
っても構わない。また、本発明の積層セラミック電子部
品の内部電極3の枚数は、上述の実施形態に限定される
ことなく、必ずしも備えている必要はなく、また何層形
成されていても構わない。また、めっき膜5,5は、必
ずしも備えている必要はなく、また何層形成されていて
も構わない。
The material of the ceramic laminate 2 of the ceramic electronic component of the present invention is not limited to the above embodiment, but may be PbZrO 3 or other dielectric materials, insulators, magnetic materials, piezoelectric materials. Also, it may be made of a semiconductor material. Further, the number of the internal electrodes 3 of the multilayer ceramic electronic component of the present invention is not limited to the above-described embodiment, and does not necessarily have to be provided, and any number of layers may be formed. Further, the plating films 5 and 5 are not necessarily required to be provided, and any number of layers may be formed.

【0020】[0020]

【実施例】積層セラミック電子部品の一実施例として、
定格電圧50V、静電容量10nF、長さ2.00mm
×幅1.25mm×厚さ0.60mmのサイズからな
る、積層セラミックコンデンサを作製する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS As one embodiment of the multilayer ceramic electronic component,
Rated voltage 50V, capacitance 10nF, length 2.00mm
A multilayer ceramic capacitor having a size of 1.25 mm in width and 0.60 mm in thickness is manufactured.

【0021】まず、BaTiO3を主成分とする生のセ
ラミック層を準備し、所定枚数の生のセラミック層の表
面上に一方の端縁が生のセラミック層の何れかの端面側
に露出するように、Niを導電成分とする内部電極とな
るべき電極膜を印刷し、これら複数の生のセラミック層
を所定枚数積層し圧着して、複数の生のセラミック素体
を準備した。次いで、これを1300℃で還元雰囲気で
焼成して、複数のセラミック積層体を得た。
First, a raw ceramic layer containing BaTiO 3 as a main component is prepared, and one edge of the raw ceramic layer is exposed on one of the end surfaces of the raw ceramic layer on the surface of a predetermined number of raw ceramic layers. Then, an electrode film to be an internal electrode containing Ni as a conductive component was printed thereon, and a predetermined number of these green ceramic layers were stacked and pressed to prepare a plurality of green ceramic bodies. Next, this was fired at 1300 ° C. in a reducing atmosphere to obtain a plurality of ceramic laminates.

【0022】次いで、平均粒径が1.0μmである球状
のCu粉末と、平均粒径が3.0μmである球状のCu
粉末と、平均粒径が15.0μmである扁平状のCu粉
末を準備し、これらを重量比率で40:20:6.7の
割合となるように混合し、Cu粉末(A種)を得た。同
様に、平均粒径が0.5μmである球状のCu粉末と、
平均粒径が3.0μmである扁平状のCu粉末を準備
し、これらを重量比率で55:3の割合となるように混
合し、Cu粉末(B種)を得た。
Next, a spherical Cu powder having an average particle size of 1.0 μm and a spherical Cu powder having an average particle size of 3.0 μm
A powder and a flat Cu powder having an average particle size of 15.0 μm are prepared, and these are mixed at a weight ratio of 40: 20: 6.7 to obtain a Cu powder (class A). Was. Similarly, a spherical Cu powder having an average particle size of 0.5 μm,
A flat Cu powder having an average particle size of 3.0 μm was prepared, and these were mixed at a weight ratio of 55: 3 to obtain a Cu powder (B type).

【0023】次いで、Cu粉末(A種,B種)と、ホウ
ケイ酸バリウムガラスフリットと、を表1に示した割合
で配合し、さらにアクリル樹脂,ブチルカルビトール,
テルピネオールを含有してなる有機ビヒクルを準備し
て、これらを配合して混練し、試料1〜11の導電性ペ
ーストを得た。
Next, Cu powder (types A and B) and barium borosilicate glass frit were blended in the proportions shown in Table 1, and an acrylic resin, butyl carbitol,
An organic vehicle containing terpineol was prepared, and these were blended and kneaded to obtain conductive pastes of Samples 1 to 11.

【0024】次いで、上述の導電性ペーストを、上述し
たセラミック積層体の長さ方向の両端面に塗布した後、
還元雰囲気中にて700〜800℃で焼付けして、一対
の端子電極を形成した後、この端子電極上に電気めっき
法によりNiめっき膜を形成し、さらにその上にSnめ
っき膜を形成して、試料1〜11の積層セラミックコン
デンサを得た。
Next, the above-mentioned conductive paste is applied to both longitudinal end surfaces of the above-mentioned ceramic laminate,
After baking at 700 to 800 ° C. in a reducing atmosphere to form a pair of terminal electrodes, a Ni plating film is formed on the terminal electrodes by electroplating, and a Sn plating film is further formed thereon. Thus, multilayer ceramic capacitors of Samples 1 to 11 were obtained.

【0025】そこで、試料1〜11の積層セラミックコ
ンデンサの端子電極のヤング率ならびにめっき付シール
性を測定し、これらを表1にまとめた。なお、ヤング率
は、上述したように、微小硬度計を用いて荷重の負荷除
荷曲線を求めることにより測定した。また、めっき付シ
ール性は、積層セラミックコンデンサを長さ方向に切断
し、端子電極内部へのめっき液の浸透状況によって判断
し、浸透していない試料について○、浸透が確認された
試料について×を付した。
Then, the Young's modulus of the terminal electrodes of the multilayer ceramic capacitors of Samples 1 to 11 and the sealing performance with plating were measured, and these are summarized in Table 1. As described above, the Young's modulus was measured by obtaining a load unloading curve of a load using a microhardness tester. The sealing performance with plating is determined by cutting the multilayer ceramic capacitor in the length direction and judging by the state of penetration of the plating solution into the terminal electrodes. Attached.

【0026】また、試料1〜11の積層セラミックコン
デンサを、長さ100mm×幅40mm×厚さ1.6m
mのガラスエポキシ基板の中央部にあるランド上にSn
/Pb共晶半田を用いて実装して、試料1〜11の撓み
試験試料を作製し、撓み強度を測定してこれを表1にま
とめた。なお、撓み強度は、EIAJ評価法に準拠し
て、ガラスエポキシ基板の両端を支持し、ガラスエポキ
シ基板の中央部裏面より押し棒を用いて表面方向に押圧
することで基板を撓ませ、ガラスエポキシ基板に実装さ
れた試料1〜11の積層セラミックコンデンサにクラッ
クが発生した時点での押し棒の移動距離(mm)を測定
した。
Further, the laminated ceramic capacitors of Samples 1 to 11 were measured to have a length of 100 mm × a width of 40 mm × a thickness of 1.6 m.
m on the land at the center of the glass epoxy substrate
/ Pb eutectic solder was used to prepare bending test samples of Samples 1 to 11, and the bending strength was measured. The flexural strength is measured by supporting both ends of the glass epoxy substrate in accordance with the EIAJ evaluation method, and pressing the glass epoxy substrate toward the front surface from the center rear surface using a push rod to bend the glass epoxy substrate. The moving distance (mm) of the push rod at the time when cracks occurred in the multilayer ceramic capacitors of Samples 1 to 11 mounted on the substrate was measured.

【0027】[0027]

【表1】 [Table 1]

【0028】表1から明らかであるように、ヤング率が
1.00×1010〜4.00×10 10N/m2の範囲内
である試料3〜5,11の積層セラミックコンデンサ
は、めっきシール性に優れ、撓み強度も6.56〜7.
84mmで強く優れた。特に、ヤング率が1.02〜
2.28N/m2である試料4,5,11の積層セラミ
ックコンデンサは、撓み強度が7.50〜7.84mm
であり、本発明の特に優れる範囲となった。
As is apparent from Table 1, the Young's modulus is
1.00 × 10Ten~ 4.00 × 10 TenN / mTwoWithin range
The multilayer ceramic capacitors of samples 3 to 5 and 11
Has excellent plating sealing properties and a flexural strength of 6.56 to 7.
It was strongly excellent at 84 mm. In particular, the Young's modulus is 1.02-
2.28 N / mTwoSample 4,5,11 laminated ceramic
The flex capacitor has a flexural strength of 7.50 to 7.84 mm.
This is a particularly excellent range of the present invention.

【0029】これに対して、ヤング率が4.00×10
10N/m2を上回る試料1,2,8〜10の積層セラミ
ックコンデンサは、めっきシール性は優れたが、撓み強
度が2.20〜5.23mmで弱く、上述した試料3〜
5,11の積層セラミックコンデンサと比較して劣った
ため、本発明の範囲外となった。
On the other hand, the Young's modulus is 4.00 × 10
The multilayer ceramic capacitors of Samples 1, 2, 8 to 10 exceeding 10 N / m 2 have excellent plating sealing properties, but have a weak flexural strength of 2.20 to 5.23 mm, and have a low flexural strength.
Since they were inferior to the multilayer ceramic capacitors of Nos. 5 and 11, they were outside the scope of the present invention.

【0030】また、ヤング率が1.00×1010N/m
2を下回る試料6,7の積層セラミックコンデンサは、
撓み強度は7.23〜7.45mmで強く優れたが、め
っきシール性が悪く、本発明の範囲外となった。
The Young's modulus is 1.00 × 10 10 N / m
The multilayer ceramic capacitors of Samples 6 and 7 below 2 are:
The flexural strength was 7.23 to 7.45 mm, which was excellent, but the plating sealability was poor, and was out of the range of the present invention.

【0031】[0031]

【発明の効果】以上述べたように、本発明による積層セ
ラミック電子部品は、複数のセラミック層が積層状態に
あるセラミック積層体と、それぞれの端縁がセラミック
積層体の何れかの端面に露出するようにセラミック層間
に形成された複数の内部電極と、内部電極の端縁と電気
的に接続されるように設けられたCuを導電成分とする
端子電極と、を備え、端子電極のヤング率は、1.00
×1010〜4.00×1010N/m2の範囲であること
を特徴とすることで、
As described above, in the multilayer ceramic electronic component according to the present invention, a ceramic laminate in which a plurality of ceramic layers are in a laminated state, and edges of the ceramic laminate are exposed at any one end face of the ceramic laminate. A plurality of internal electrodes formed between the ceramic layers, and a terminal electrode having a conductive component of Cu provided so as to be electrically connected to the edge of the internal electrode, and the Young's modulus of the terminal electrode is , 1.00
By being in the range of × 10 10 to 4.00 × 10 10 N / m 2 ,

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る一つの実施の形態の積層セラミッ
ク電子部品の断面図である。
FIG. 1 is a cross-sectional view of a multilayer ceramic electronic component according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 積層セラミック電子部品 2 セラミック積層体 2a セラミック層 3 内部電極 4 端子電極 REFERENCE SIGNS LIST 1 multilayer ceramic electronic component 2 ceramic laminate 2 a ceramic layer 3 internal electrode 4 terminal electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数のセラミック層が積層状態にあるセ
ラミック積層体と、それぞれの端縁が前記セラミック積
層体の何れかの端面に露出するように前記セラミック層
間に形成された複数の内部電極と、前記内部電極の端縁
と電気的に接続されるように設けられたCuを導電成分
とする端子電極と、を備える積層セラミック電子部品で
あって、 前記端子電極のヤング率は、1.00×1010〜4.0
0×1010N/m2の範囲であることを特徴とする、積
層セラミック電子部品。
1. A ceramic laminate in which a plurality of ceramic layers are stacked, and a plurality of internal electrodes formed between the ceramic layers such that respective edges are exposed at any one end face of the ceramic laminate. A terminal electrode having Cu as a conductive component provided so as to be electrically connected to an edge of the internal electrode, wherein the Young's modulus of the terminal electrode is 1.00. × 10 10 to 4.0
A multilayer ceramic electronic component characterized by being in the range of 0 × 10 10 N / m 2 .
JP2001126594A 2001-04-24 2001-04-24 Multilayer ceramic electronic components Expired - Lifetime JP4691818B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
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JP2002324720A true JP2002324720A (en) 2002-11-08
JP4691818B2 JP4691818B2 (en) 2011-06-01

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Country Status (1)

Country Link
JP (1) JP4691818B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02232914A (en) * 1989-03-07 1990-09-14 Kyocera Corp Chip capacitor
JP2002015944A (en) * 2000-06-30 2002-01-18 Kyocera Corp Ceramic capacitor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02232914A (en) * 1989-03-07 1990-09-14 Kyocera Corp Chip capacitor
JP2002015944A (en) * 2000-06-30 2002-01-18 Kyocera Corp Ceramic capacitor

Also Published As

Publication number Publication date
JP4691818B2 (en) 2011-06-01

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