JP2002315334A - Switching power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce switching loss in a power supply circuit. SOLUTION: First, a drive voltage V3 is generated by a driving winding N3, to switching-drive a secondary-side active clamping circuit 32, which is conduction-angle-controlled for stabilization. A gate voltage Vgs of a specified level is generated by causing a driving power supply circuit 33 to perform amplification, utilizing the driving voltage V3. Consequently, the on-resistance of an auxiliary switching element, when it is turned on is lowered, since it is possible to generate a gate voltage Vgs amplified to a level sufficient to saturate the auxiliary switching element for example as a MOS-FET, and the voltage can be applied to the auxiliary switching element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply circuit provided as a power supply for various electronic devices.

[0002]

2. Description of the Related Art As a switching power supply circuit, a circuit employing a switching converter of a type such as a flyback converter or a forward converter is widely known. Since these switching converters have a rectangular switching operation waveform, there is a limit in suppressing switching noise. Also, due to its operating characteristics,
It has been found that there is a limit in improving the power conversion efficiency. Therefore, the present applicant has previously proposed various switching power supply circuits using various resonance type converters.
The resonance type converter can easily obtain high power conversion efficiency and realize low noise because the switching operation waveform is sinusoidal. It also has the advantage that it can be configured with a relatively small number of parts.

FIG. 6 is a circuit diagram showing an example of a prior art switching power supply circuit which can be constructed based on the invention proposed by the present applicant. As a basic configuration of the power supply circuit shown in this figure, a voltage resonance type converter is provided as a primary side switching converter.

The power supply circuit shown in FIG.
To perform a switching operation. This DC input voltage 1 is applied to the primary winding N of the converter transformer 3.
The signal is input to the main switching element 4 on the primary side via 1. The main switching element 4 is formed by connecting a damper diode 5 and a primary-side parallel resonance capacitor 6 for forming a reverse current path at the time of a switching operation in parallel with each other. The main switching element 4 is turned on / off by a drive signal output from the oscillation / drive circuit 31 to perform a switching operation.

The oscillation / drive circuit 31 drives the main switching element 4 at a fixed frequency set arbitrarily, or at a switching frequency synchronized with an external synchronization signal such as a horizontal deflection synchronization signal in a television receiver. The turn-on timing is a so-called ZVS (Zero Voltage Switch-in), which is turned on after a resonance voltage pulse generated at both ends of the main switching element 4 reaches a zero level.
g) to perform switching drive.

The converter transformer 3 transmits the switching output of the primary side switching circuit obtained on the primary winding N1 to the secondary winding N2. In this case, the converter transformer 3 employs a structure in which a loosely coupled state can be obtained between the primary winding N1 and the secondary winding N2, so that, for example, a leakage inductance 2 can be obtained.

On the primary side, the primary winding N1
The primary side parallel resonance circuit is formed by the leakage inductance 2 and the capacitance of the primary side parallel resonance capacitor 6, so that the switching operation of the primary side switching circuit becomes a voltage resonance type.

The secondary winding N of the converter transformer 3
As shown in the figure, a rectifier circuit including a rectifier diode 11 and a smoothing capacitor 12 is connected to the end of the second terminal 2 to generate and output, for example, a 135V secondary-side DC output voltage EO1. . Further, in this case, a rectifier circuit including a rectifier diode 13 and a smoothing capacitor 14 is connected to the tap output provided on the secondary winding N2 to obtain, for example, a secondary DC output voltage EO2 of 15V. It has also been.

Also, the secondary side parallel resonance capacitor 15 is connected in parallel to the secondary winding N2,
The leakage inductance 2 of the secondary winding N2 and the capacitance of the secondary parallel resonance capacitor 15 form a secondary parallel resonance circuit. That is, in the power supply circuit shown in this figure, the primary side of the converter transformer is provided with a parallel resonance circuit for making the switching operation a voltage resonance type, and the secondary side is provided with a parallel resonance circuit for obtaining the voltage resonance operation. Be provided. In the present specification, such a switching converter configured to operate with a resonance circuit provided for the primary side and the secondary side is also referred to as a “composite resonance type switching converter”. In this case, the converter transformer 3 is loosely coupled to obtain the leakage inductance 2, but the converter transformer 3 may be tightly coupled and have a configuration in which a choke coil is connected instead of the leakage inductance 2. It is.

The secondary side formed as described above further includes a secondary side active clamp circuit 3.
2 are provided. This secondary side active clamp circuit 3
2 is a clamp capacitor 16 as shown in the figure.
And an auxiliary switching element 17. In this case, a MOS-FET is selected as the auxiliary switching element 17, and a body diode is connected to the MOS-FET in the direction shown to form a path for flowing a reverse current. I have. The auxiliary switching element 17 is switched by applying a gate voltage Vgs to the gate. In this circuit, the drive winding N3
Is wound, and the alternating voltage excited in the drive winding N3 can be obtained through a series connection circuit of a resistor 51 and a capacitor 52.

The control circuit 20 includes, for example, an error amplifier, and is provided for controlling the conduction angle of the auxiliary switching element 17. In this case, the control circuit 20 converts the secondary side DC output voltage EO1 into a voltage dividing resistor R2 as shown in the figure.
1-Detected by R22 and input to error amplifier 24.
The error amplifier 24 applies a bias voltage of a level changed according to the error between the detection voltage and the reference voltage 23 to the gate of the auxiliary switching element 17. In this case, the bias voltage is made higher as the secondary side DC output voltage EO1 fluctuates so as to rise, and becomes lower as it fluctuates so as to fall. When this bias voltage is superimposed on the drive voltage V3 applied from the drive winding N3, the gate voltage Vgs applied to the gate of the auxiliary switching element 17 changes. The period (ON period) can be variably controlled. Note that, for example, when the gate voltage Vgs increases, the on-time increases and the conduction angle increases. By variably controlling the conduction angle in this manner, an operation of stabilizing the secondary DC output voltage can be obtained as described later.

FIG. 7 shows the operation of the main part of the power supply circuit shown in FIG. The main switching element 4 on the primary side is turned off during the period TOFF1 and turned on during the period TON1, and in this case, the switching operation is performed at a fixed frequency. And the period TOFF1
7, the voltage resonance pulse V1 is generated as shown in FIG.

The operation on the secondary side is as follows. When the main switching element 4 on the primary side is turned off and reaches time point t1, the secondary parallel resonance circuit (secondary winding N2 // secondary parallel resonance capacitor 15) shown in FIG.
Of the rectifier diode 11 with respect to the secondary side DC output voltage EO1
It becomes lower than the voltage level EO1 + VD on which D is superimposed. Thus, the period DOFF during which the rectifier diode 11 is turned off
Is started. When the rectifier diode 11 is turned off, the current that has flowed through the secondary winding N2 until then flows through the secondary-side parallel resonance capacitor 15 as shown as a secondary-side resonance current I5 in FIG. Become. For this reason, the secondary side resonance voltage V5 increases in the negative polarity direction as shown after time t1 in FIG. 7B.

Next, at time t2, when the variation width of the secondary side resonance voltage V5 becomes equal to or higher than the voltage level corresponding to the initial charge stored in the clamp capacitor 16, the body diode of the auxiliary switching element 17 becomes conductive. , The secondary winding current obtained in the secondary winding N2 flows through the path from the body diode to the clamp capacitor 16. As a result, the clamp current I flowing through the clamp capacitor 16 is
6 flows in the negative polarity direction for a predetermined period from the start of the period TON2 during which the auxiliary switching element 17 is turned on, as shown in FIG. 7C. The secondary parallel resonance capacitor 15 and the clamp capacitor 16
Is selected so that the value of the clamp capacitor 16 is about 10 times or more larger than that of the secondary side parallel resonance capacitor 15, and the voltage change of the clamp capacitor 16 is small.

The drive winding N3 has a secondary winding N2.
The drive voltage V3, which is an alternating voltage having a polarity opposite to that of the obtained alternating voltage, is induced. After the time point t2, the alternating voltage V3 of the positive polarity level is applied as a gate voltage to the auxiliary switching element 17. Therefore, while the body diode of the auxiliary switching element 17 is conducting, the auxiliary switching element 17 is turned on, and the resonance current flowing through the secondary winding N2 is inverted. In other words, the current flows to the MOS-FET forming the auxiliary switching element 17 in the forward direction and increases. For this reason, the clamp current I6 is inverted in the negative direction from the positive direction to the positive direction and flows in a sawtooth waveform within the period TON2 shown in FIG. 7C.

The gate voltage Vgs applied to the gate of the auxiliary switching element 17 (MOS-FET) shown in FIG. 7 (g). As can be seen from the above operation, the auxiliary switching element 17 is turned on. Period TON2
Has a value close to the gate threshold voltage (Vth). For this reason, when the forward current increases and reaches time point t3, the auxiliary switching element 17 becomes unsaturated due to the current value caused by the forward admittance of the MOS-FET, and the drain switch shown in FIG. The source-to-source voltage V7 increases. In response to this, the drive winding voltage V3 excited in the drive winding N3 decreases as shown in FIG. 7F, and accordingly, the drain-source of the auxiliary switching element 17 is reduced. The inter-voltage V7 will further rise. Thereby, the auxiliary switching element 17 is turned off.

After time t3, the resonance current of the secondary winding N2 is changed to the secondary side resonance current I5 shown in FIG.
Flows through the secondary-side parallel resonance capacitor 15, whereby the secondary-side resonance voltage V5 increases. Then, at time t4, when the voltage reaches a level equal to or higher than EO1 + VD obtained by adding the secondary side DC output voltage EO1 and the forward voltage VD of the rectifier diode 11, a period DON during which the rectifier diode 11 is turned on.
Is started to supply current to the load side.

Here, depending on the control circuit 20, the conduction angle of the auxiliary switching element 17 is variably controlled according to the level change of the secondary DC output voltage EO1 as described above. That is, by changing the bias voltage, the level of the gate voltage Vgs shown in FIG. 7G becomes close to the gate threshold voltage Vth during the period T.
ON2 (t2 to t3) is variably controlled.

Here, if it is assumed that the secondary active clamp circuit 32 is not provided, the secondary resonance voltage V5
Is a waveform indicated by a broken line in FIG. The amplitude of the secondary side resonance voltage V5 indicated by this broken line is 1
Since the switching frequency of the secondary side main switching element 4 is constant, the output voltage cannot be kept constant because it varies depending on the voltage level of the DC input voltage 1 and the amount of power supplied to a load circuit connected as a load. Therefore, by providing the secondary side active clamp circuit 32 and controlling the conduction angle as described above, the level of the secondary side resonance voltage V5 is variably controlled.
The conduction angles of the first and the first 13 are variably controlled, whereby the secondary side DC output voltages EO1 and EO2 are stabilized.

[0020]

As can be seen from the above operation description, the switching operation of the auxiliary switching element 17 is obtained by applying a gate voltage near the gate threshold voltage Vth of the MOS-FET. It is. Therefore, the gate voltage level when the MOS-FET is turned on must be lowered. For this reason, it is difficult to bring the device into a sufficiently saturated state, so that the on-resistance increases, and the power loss increases. As a countermeasure,
It is necessary to select a large capacity MOS-FET and to provide a heat sink having a relatively large size. The auxiliary switching element 1 shown in FIG.
In the configuration of the drive circuit system for No. 7, the gate charge is not actively extracted and turned off at the time of turn-off. For this reason, the fall time is long,
The switching loss due to this has also increased.

Further, although the gate threshold voltage Vth of the MOS-FET varies from element to element, the circuit shown in FIG. 6 uses a gate voltage near the gate threshold voltage Vth. The influence of the variation of the voltage Vth on the control characteristics cannot be ignored. For this reason, it is necessary to manage the characteristics of the component element as the MOS-FET. In other words, there is a problem in manufacturing efficiency.

[0022]

In view of the above-mentioned problems, the present invention is configured as a switching power supply circuit as follows. That is, a switching means formed by including a main switching element for switching an input DC input voltage, and a switching output obtained by winding a primary winding and a secondary winding and obtaining a primary winding, to the secondary winding. And a converter transformer for transmitting to the winding. Further, the operation of the switching means is formed by a leakage inductance of the primary winding or an inductance of an inductance element connected in series with the primary winding and a capacitance of the primary side resonance capacitor so that the operation of the switching means is a voltage resonance type. A primary side parallel resonance circuit is provided, and a secondary side resonance circuit formed by a secondary winding and a secondary side resonance capacitor is provided. In addition, there is provided a DC output voltage generation means for obtaining a DC output voltage by inputting an alternating voltage obtained to the secondary side resonance circuit and performing a rectification operation. In addition, it is formed by connecting a series connection circuit of a clamp capacitor and an auxiliary switching element in parallel with a primary side parallel resonance capacitor or a secondary side resonance capacitor, and performs a switching operation to form a primary side parallel resonance circuit or a secondary side resonance capacitor. An active clamp means is provided to clamp a peak level of a resonance voltage generated in the secondary parallel resonance circuit. Also,
Utilizing the alternating voltage obtained in the primary winding or the secondary winding to input a driving alternating voltage generating means for generating a driving alternating voltage of a required level and amplifying by inputting the driving alternating voltage. A driving signal generating means for generating and outputting a driving pulse signal of a predetermined level or more to be applied to the auxiliary switching element, and according to a level change of the DC output voltage,
Constant voltage control means is provided for controlling the DC output voltage to be constant by variably controlling the conduction period of the auxiliary switching element driven by the drive pulse signal.

According to the above configuration, a composite resonance type converter having a primary side parallel resonance circuit for obtaining an operation as a voltage resonance type converter on the primary side and a secondary side resonance circuit on the secondary side is formed. ing. And, it is connected in parallel to the primary side parallel resonance circuit or the secondary side parallel resonance circuit,
An active clamp circuit that performs a switching operation by clamping the resonance voltages of these resonance circuits is provided. In this active clamp circuit, the conduction angle of the auxiliary switching element is variably controlled in accordance with the secondary-side DC output voltage level, whereby a constant voltage is achieved. Then, under the above configuration, as a switching drive circuit system for switching the auxiliary switching element of the active clamp circuit, a driving alternating voltage is generated by a driving alternating voltage generating means, and the driving alternating voltage is generated by a driving signal generating means. A drive pulse signal of a predetermined level or more is generated by utilizing the drive pulse signal. When the auxiliary switching element is driven by such a drive pulse signal, for example, the auxiliary switching element can be brought into a sufficiently saturated state when turned on.

[0024]

FIG. 1 shows a configuration example of a switching power supply circuit according to a first embodiment of the present invention. In the power supply circuit shown in FIG.
To perform a switching operation. The DC input voltage 1 is obtained by, for example, rectifying and smoothing a commercial AC power supply, and the primary winding N of the converter transformer 3 is provided.
The signal is input to the main switching element 4 via 1.

In this case, an NPN transistor is selected as the main switching element 4. A damper diode 5 and a primary side parallel resonance capacitor 6 for forming a reverse current path during the switching operation are connected in parallel between the collector and the emitter of the main switching element 4. Then, the main switching element 4 is turned on / off by a drive signal output from the oscillation / drive circuit 31, so that the switching element performs a switching operation.

The oscillation / drive circuit 31 drives the main switching element 4 at an arbitrarily set fixed frequency or at a switching frequency synchronized with an external synchronization signal such as a horizontal deflection synchronization signal in a television image receiver. It is configured to Then, the so-called ZVS which is turned on after the resonance voltage pulse generated at both ends of the main switching element 4 becomes zero level,
(Zero Voltage Switching).

The converter transformer 3 transmits the switching output of the primary side switching circuit obtained on the primary winding N1 to the secondary winding N2. In this case, the converter transformer 3 adopts a structure in which, for example, a gap is provided to the center magnetic leg of the EE type core, so that loose coupling of the primary winding N1 and the secondary winding N2 by a required coupling coefficient is achieved. A state is obtained so that a leakage inductance 2 is obtained in the converter transformer 3.

On the primary side of the converter transformer 3, the leakage inductance 2 of the primary winding N1
And the capacitance of the primary-side parallel resonance capacitor 6, a primary-side parallel resonance circuit is formed, whereby the switching operation of the primary-side switching circuit is of a voltage resonance type. That is, 1 is on the primary side
A voltage resonant converter formed with a stone main switching element 4 will be provided.

The secondary winding N of the converter transformer 3
A rectifier circuit formed by a rectifier diode 11 and a smoothing capacitor 12 is connected to the end 2 as shown. Depending on the rectifier circuit, for example, 1
The secondary-side DC output voltage EO1 of 35 V is generated and output. In this case, a tap output is provided to the secondary winding N2, and another tap formed by the rectifier diode 13 and the smoothing capacitor 14 is provided for the tap output.
They also connect two rectifier circuits. Then, depending on the rectifier circuit, the secondary DC output voltage EO2 of, for example, 15 V, which is set to a voltage lower than the secondary DC output voltage EO1.
Is generated and output.

A secondary parallel resonance capacitor 15 is connected in parallel to the secondary winding N2. The leakage inductance 2 of the secondary winding N2 and the capacitance of the secondary parallel resonance capacitor 15 are connected. This forms a secondary parallel resonance circuit. That is, also in the power supply circuit shown in this figure, a parallel resonance circuit for obtaining an operation as a voltage resonance type switching converter is provided on the primary side of the converter transformer 3, and a parallel resonance circuit for obtaining a voltage resonance operation is provided on the secondary side. This embodiment employs a configuration as a complex resonance type switching converter provided with a resonance circuit. It should be noted that the converter transformer 3 is tightly coupled with a choke coil instead of the leakage inductance 2, and the primary side parallel resonance circuit and the secondary side resonance circuit can be formed by using the inductance of the choke coil. it can.

On the secondary side of the power supply circuit formed as described above, a secondary side active clamp circuit 32 is provided. As shown in the figure, the secondary side active clamp circuit 32
6 and an auxiliary switching element 17. In this case, a MOS-FET is selected as the auxiliary switching element 17, and a body diode is connected to the MOS-FET in the direction shown to form a path for flowing a reverse current. I have. The drain of the auxiliary switching element 17 is connected to the clamp capacitor 16.
Is connected to the end of the secondary winding N2 through the series connection of The source is connected to the secondary side ground. That is, the secondary side active clamp circuit 32 is connected to the secondary winding N
A series connection circuit including an auxiliary switching element 17 and a clamp capacitor 16 is connected in parallel to a secondary parallel resonance circuit including the secondary and secondary parallel resonance capacitors 15.

On the secondary side of the converter transformer 3, a drive winding N3 is wound. A drive winding voltage V3, which is an alternating voltage induced by the secondary winding N2, is generated in the drive winding N3. The alternating voltage has a polarity opposite to that of the alternating voltage (secondary resonance voltage V5) obtained in the secondary winding N2 due to the relationship of the winding direction with the secondary winding N2.

The drive winding voltage V3 is applied to the gate of the auxiliary switching element 17 through the series connection of the resistor 51 and the capacitor 52 and further through the drive power supply circuit 33. The drive power supply circuit 33 includes:
As described later, the input drive winding voltage V3
To generate a drive voltage (gate voltage Vgs) having a waveform suitable for switching driving of the auxiliary switching element 17.

The driving power supply circuit 33 is formed by the following circuit configuration. This drive power supply circuit 33
For example, as shown, transistors 54, 55, and transistor 57 are provided. An NPN transistor is selected for the transistors 54 and 55, and a PNP transistor is selected for the transistor 57. Transistor 54
, The Zener diode 53 and the resistor 6
1 is connected, and the series connection circuit of the zener diode 53 and the resistor 61 is further connected to the drive winding N3 via the series connection circuit of the resistor 51 and the capacitor 52. The collector of the transistor 54 is connected to the line of the secondary side DC output voltage EO2 via the resistor 58, so that the amplifying operation is performed using the secondary side DC output voltage EO2 as an operation power supply. The emitter is connected to the secondary side ground.

The transistor 55 includes the transistor 5
4 is provided to invert the polarity of the amplified output of No. 4, and its base is connected to the collector of the transistor 54. The collector of the transistor 55 also receives the secondary DC output voltage EO2 as a power supply, and is connected to the line of the secondary DC output voltage EO2 via the resistor 59. The collector output of the transistor 55 is applied to the gate of the auxiliary switching element 17 via the anode → the cathode of the diode 56.

The transistor 57 is provided for extracting a gate charge at a timing when the auxiliary switching element 17 is turned off. The base of transistor 57 is connected to the collector of transistor 55, and the emitter is connected to the gate of auxiliary switching element 17.
The collector is connected to the primary side ground.

The control circuit 20 includes, for example, an error amplifier, and is provided for controlling the conduction angle of the auxiliary switching element 17. In the control circuit 20 in this case, as shown in the figure, a voltage dividing resistor R21-R22 is connected in parallel between the secondary side DC output voltage EO1 and the secondary side ground. The connection point of the voltage dividing resistors R21 and R22 is connected to the non-inverting input of the error amplifier 24. Further, a reference voltage 23 of a predetermined level set corresponding to the level of the specified secondary-side DC output voltage EO1 is input to the inverted input of the error amplifier 24. Accordingly, the error amplifier 24 outputs a voltage whose level is varied in accordance with an error between the voltage level of the secondary DC output voltage EO1 detected by the voltage dividing resistors R21 and R22 and the reference voltage 23. You. This output voltage is the secondary side DC output voltage E
It changes to increase as O1 increases, and
It is generated so that it becomes lower as it descends. The voltage output from the error amplifier 24 in this manner is supplied to the Zener diode 53 through the backflow preventing diode.
It is output as a bias voltage to a point A which is a connection point between the capacitor and the capacitor 52. The point A is an input terminal of the drive power supply circuit 33, as can be seen from the drawing.

Although the operation of the power supply circuit of the present embodiment configured as described above will be described later, the following configuration is employed to drive the secondary-side active clamp circuit 32. That is, the ON / OFF timing (turn-on timing and conduction time width) for switching driving the auxiliary switching element 17 is obtained by the drive voltage V3 obtained in the drive winding N3 and the control operation of the control circuit 20. The gate voltage Vgs applied to the auxiliary switching element 17 is generated by the drive power supply circuit 33 by inputting the drive voltage V3 that determines the switching timing. At this time, the drive power supply circuit 33 obtains the operating power for performing the amplifying operation from the secondary side DC output voltage EO2.

FIG. 2 shows operation waveforms of main parts of the power supply circuit shown in FIG. In the power supply circuit shown in FIG. 1, the primary-side main switching element 4 is turned off in the period TOFF1 and turned on in the period TON1, and is driven to perform a switching operation at a fixed frequency. In the period TOFF1, the voltage resonance pulse V1 is generated as shown in FIG. 2A, indicating that the switching operation of the primary side main switching element 4 is of the voltage resonance type.

The operation on the secondary side is as follows. The secondary-side resonance voltage V5 shown in FIG.
2 // Alternating voltage obtained in the secondary parallel resonance circuit including the secondary parallel resonance capacitor 15. When the primary side main switching element 4 is turned off and reaches the time point t1, the secondary side resonance voltage V5 becomes the secondary side DC output voltage EO1.
Is lower than EO1 + VD where the forward voltage VD of the rectifier diode 11 is superimposed. Thus, a period DOFF in which the rectifier diode 11 is turned off starts. When the rectifier diode 11 is turned off, the current that has been flowing through the secondary winding N2 until then flows through the secondary-side parallel resonance capacitor 15 as shown as a secondary-side resonance current I5 in FIG. Become. For this reason, the secondary side resonance voltage V5 is
As shown after time T1 in (b), it increases in the negative polarity direction.

At the subsequent time point t2, the secondary side resonance voltage V
5 becomes equal to or higher than the voltage corresponding to the initial charge stored in the clamp capacitor 16, the body diode of the auxiliary switching element 17 conducts, and the secondary winding current obtained in the secondary winding N2 becomes Body diode →
It flows through the path of the clamp capacitor 16. As a result, the clamp current I6 flowing through the clamp capacitor 16
As shown in FIG. 2C, in the first period of the period TON2 in which the auxiliary switching element 17 is turned on, a sawtooth waveform in the negative polarity direction is obtained. The capacitances of the secondary parallel resonance capacitor 15 and the clamp capacitor 16 are selected so that the value of the clamp capacitor 16 is about 10 times or more larger than that of the secondary parallel resonance capacitor 15. The change in the voltage of the clamp capacitor 16 is smaller than that of the capacitor 15.

The drive winding N3 has a secondary winding N2.
A drive voltage V3, which is an alternating voltage having a polarity opposite to that of the obtained alternating voltage, is induced. The drive voltage V3 reverses and rises from the negative polarity to the positive polarity after the period t1 as shown in FIG. 2 (f). Then, the period TON reaches the period t2.
When 2 is started, the damper diode of the auxiliary switching element 17 conducts. This damper current is
It flows as the clamp current I6 in FIG. 2C and is shown as a sawtooth wave of negative polarity in the period TON2. As a result, the drive voltage V3 has a waveform that maintains a constant level due to the positive polarity. The drive voltage V3 changes to a waveform that decreases linearly as shown by the voltage A at the point A in FIG. 2G through the resistor 51 and the capacitor 52.

FIG. 2 (g) shows the waveform of the voltage VA at the point A by comparison with the threshold voltage VZD. Threshold voltage VZD
Is the threshold voltage VZD of the Zener voltage of the Zener diode 53 due to the base-emitter voltage of the transistor 54.
Is a voltage level obtained by superimposing. The point A voltage V
When the level of A is equal to or higher than the threshold voltage VZD, the transistor 54 is turned on and the transistor 55 is turned off. Therefore, the voltage of the gate of the auxiliary switching element 17 from the line of the secondary side DC output voltage EO2 via the resistor 59 and the diode 56 is
It will be applied as the gate voltage Vgs. This gate voltage Vgs rises sharply at time t2 as shown in FIG. 2 (h), and the secondary-side DC output voltage E
Maintain O2 levels. The level at this time is, for example, 15
Since it is set to V, it can be brought to a sufficiently saturated state due to the characteristics of the MOS-FET. Therefore, the on-resistance of the MOS-FET in the auxiliary switching element 17 at this time can be sufficiently reduced.

The level of the voltage A at the point A gradually decreases linearly after time t2.
Then, for example, when the voltage falls below the threshold voltage VZD at time t3, the transistor 54 is turned off and the transistor 55 is turned on. At this time, since the base current flows through the transistor 57 which is a PNP, the auxiliary switching element 17
The gate charge of the MOS-FET at is rapidly discharged through the emitter-collector of the transistor 57. For this reason, the gate voltage Vgs shown in FIG. 2H is at the 0 level so as to fall sharply at the time t3. This indicates that the turn-off of the auxiliary switching element 17 is performed rapidly, and the descent time is shortened accordingly, so that the switching loss is reduced.

The gate voltage Vgs of the present embodiment is
Is approximately 15 when turned on, as shown in FIG.
While V is applied, the waveform has a waveform that sharply changes to the 0 level when off. The waveform of the gate voltage Vgs shown in FIG. 2H is close to the gate threshold voltage Vth like the gate voltage (FIG. 7G) generated in the power supply circuit of the prior art shown in FIG. Indicates that the operation is not performed. Therefore, in the present embodiment, the MOS-
The variation in the gate threshold voltage Vth of the FET does not affect the control characteristics. For this reason, in the present embodiment, it is not necessary to manage the characteristics of the MOS-FET in consideration of the variation in the gate threshold voltage, so that the manufacturing efficiency can be increased and the manufacturing cost can be reduced accordingly.

By the switching operation of the auxiliary switching element 17 as described above, the voltage V7 across the auxiliary switching element 17 decreases during the period t1 to t2 as shown in FIG. , Period t2
At t3, the level becomes 0, and the period t3 to t3
The waveform rises at 4 and maintains the level of the secondary side DC output voltage EO1 until the next time point t1.

When the secondary active clamp circuit 32 is not provided, the secondary winding N2 is turned off during the period DOFF during which the secondary rectifier diode 11 is turned off.
, A current flows to the secondary-side parallel resonant capacitor 15 and the charge increases considerably. Therefore, the secondary-side resonance voltage V5, which is the voltage across the secondary-side parallel resonance capacitor 15,
Generates a peak level like a waveform shown by a broken line in FIG.

On the other hand, in the present embodiment,
By the switching operation of the auxiliary switching element 17 in the secondary side active clamp circuit 32 as described above, the current to flow through the secondary side parallel resonance capacitor 15 is increased during the period TON2 in the period DOFF as shown in FIG. As shown in c), the current flows as the clamp current I6.
Accordingly, as shown in FIG. 2E, the secondary-side resonance current I5 is divided into periods t1 to t, which are periods before and after the period TON2.
Only during the period 2 and the period t3 to t4, the charge flows into the secondary side parallel resonance capacitor 15, and the charge in the secondary side parallel resonance capacitor 15 decreases accordingly.
As a result, the secondary resonance voltage V5, which is a voltage across the secondary parallel resonance capacitor 15, has a waveform that is clamped so that the peak level in the period TON2 is suppressed.

In the present embodiment, the operation of clamping the secondary side resonance voltage V5 is obtained as described above, and further, the output voltage of the control circuit 20 is applied to the point A. I am trying to do it. That is, a bias voltage having a level varied according to the level change of the secondary DC output voltage EO1 is applied. Therefore, the point A voltage VA
Is obtained by changing the amplitude level obtained based on the drive voltage V3 by the bias voltage. And
The operation of the drive power supply circuit 33 described above is executed by inputting the point A voltage VA whose amplitude is variably controlled. Thereby, for example, the conduction time (period TON) of the auxiliary switching element 17 within one switching cycle
2) is variably controlled. In this case, if the level of the gate voltage Vgs increases, the conduction time (the period TON
2) becomes longer and the conduction angle is enlarged.

As described above, the auxiliary switching element 1
7, the period in which the secondary-side resonance current I5 flows through the secondary-side parallel resonance capacitor 15 is varied, and the secondary-side resonance voltage V
5 levels will be varied. Further, as a result of varying the period TON2, which is the conduction time of the auxiliary switching element 17, the period DOFF including this period TON2 is also varied. That is, variable control is also performed on the conduction period (conduction angle) of the secondary rectifier diodes 11 and 13. In this way, the level of the secondary-side resonance voltage V5 and the conduction angle of the rectifier diodes 11, 13 are variably controlled, so that
This stabilizes the secondary side DC output voltages EO1 and EO2.

The drive voltage V3 shown in FIG. 2 (f) rises during the period t1 to t2, but during the period t1 to t2, the drive voltage V3 shown in FIG.
As shown in (e), the secondary side parallel resonance capacitor 1
5, a secondary side resonance current I5 flows. This period t1 to t2
, The auxiliary switching element 17 (MOS-FE
Since the drain-source voltage T) is applied to some extent, if the auxiliary switching element 17 is turned on at this time, a surge current flows at turn-on and switching loss occurs. Would be.

Therefore, in this embodiment, the transistor 5
By connecting a capacitor 62 between the base and the emitter of No. 4, a delay circuit is formed together with the resistor 61. The delay circuit adjusts the gate voltage Vgs to be applied to the auxiliary switching element 17 after the time point t2. However, if the delay time of the delay circuit is set too long, the switching timing will be such that the gate voltage vgs is not applied even when the current flowing through the body diode of the auxiliary switching element 17 ends. At the timing of applying the gate voltage vgs, the output voltage increases because a proper conduction time cannot be secured. For this reason, the delay time is adjusted so that the gate voltage is applied during the period when the current flows through the body diode of the auxiliary switching element 17.

FIG. 3 shows a configuration example of a power supply circuit according to a second embodiment of the present invention. In FIG. 3, the same parts as those in FIG. In the power supply circuit shown in FIG.
A is provided. In the drive power supply circuit 33A,
For example, instead of the amplifier circuit formed with the transistors 54 and 55 in the drive power supply circuit 33 shown in FIG.
The configuration including the comparator 50 is adopted.

For the non-inverting input terminal of the comparator 50, the drive voltage V3 obtained in the drive winding N3
Is input through a series connection of a resistor 51 and a capacitor 52. The voltage input to the non-inverting input terminal is the same as the point A voltage VA in the case of the circuit shown in FIG. 1, for example. Further, a voltage level obtained at both ends of the resistor 72 is input to the inverting input terminal. In this case, a current is caused to flow from the error amplifier 24 in the control circuit 20 to the resistor 72. Therefore, a voltage having a level corresponding to a change in the secondary DC output voltage EO1 is applied to both ends of the resistor 72. Will be obtained.

Then, the comparator 50 compares the level of the voltage A at the point A input to the non-inverting input terminal with the level of the voltage (output of the error amplifier 24) input to the inverting input terminal, and finds that the voltage VA is higher. For example, a positive polarity voltage of more than 10 V is applied to the gate of the auxiliary switching element 17 (MOS-FET). On the other hand, if the voltage VA is lower, by outputting a negative voltage, the PN
The transistor 57 of P is turned on. Thereby, the auxiliary switching element 17 (MOS-FET)
The gate charge will be rapidly withdrawn and will be rapidly turned off. The operating power supply of the comparator 50 is obtained from the line of the secondary DC output voltage EO2.

In the configuration according to the second embodiment, the switching timing is the same as the drive voltage V3
Is determined by In addition, the driving power supply circuit 33A also uses the secondary DC output voltage EO2, which is another power supply, to reduce the on-resistance by setting a sufficient saturation state at the time of ON, and to rapidly extract the gate charge at the time of turn-off. In this way, the descent time is shortened.

FIG. 4 shows a configuration example of a power supply circuit according to a third embodiment of the present invention. Note that in this figure, the same parts as those in FIGS. In the power supply circuit shown in this figure, the collector of a main switching element 4 forming a voltage resonance type converter on the primary side is connected to the positive line of the DC input voltage 1. The emitter is connected to the end of the primary winding N1 of the converter transformer. That is, in the circuit shown in FIG.
Of the primary winding N with respect to the DC input voltage
The order of connection between 1 and the main switching element 4 is reversed.

A damper diode is connected in parallel to the main switching element 4 to form a reverse current path during the switching operation. In this case, the primary side parallel resonance capacitor 6 is
It is connected between the winding start end of the primary winding N1 and the primary side ground. That is, it is connected in parallel with the primary winding N1. Therefore, in this power supply circuit as well, the leakage inductance 2
And the capacitance of the primary-side parallel resonance capacitor 6 form a primary-side parallel resonance circuit for making the switching operation of the main switching element 4 a voltage resonance type.

In this case, the secondary-side active clamp circuit 32 shown in FIGS. 1 and 3 is deleted, and a primary-side active clamp circuit 32A is provided for the primary side instead. ing. Accordingly, the drive winding V3 for generating the drive voltage V3 for the auxiliary switching element 17 is wound around the primary side of the converter transformer 3. Further, a drive power supply circuit 33B for generating a gate voltage Vgs applied to the auxiliary switching element 17 is also provided on the primary side. That is, in the present embodiment, the auxiliary switching element 17 in the primary side active clamp circuit 32A is described later.
In this case, the stabilization can be achieved by controlling the conduction angle of.

The primary side active clamp circuit 32A
Also, an auxiliary switching element 17 in which a MOS-FET and a body diode are connected in parallel, and a clamp capacitor 1
6 are formed. In this case, the drain of the auxiliary switching element 17 is connected to the connection point between the emitter of the main switching element 4 and the primary winding N1 via the series connection of the clamp capacitor 16. The source of the auxiliary switching element 17 is connected to the primary side ground. Thus, the primary side active clamp circuit 32
A is formed by connecting a series connection circuit in which an auxiliary switching element 17 and a clamp capacitor 16 are connected in series to a primary-side parallel resonance circuit including a primary-side parallel resonance capacitor 6 and a primary winding N1. Things.

The drive voltage V3 obtained on the drive winding N3
In this case as well, through the resistor 51 and the capacitor 52, the voltage A at a point A having a waveform whose peak level decreases linearly is obtained. Then, the point A voltage VA is input to the drive power supply circuit 33B. The circuit configuration of the drive power supply circuit 33B is the same as that of the drive power supply circuit 33 shown in FIG. 1, and the description of this point is omitted here. However, since the drive power supply circuit 33B is provided for the primary side, the operation power supply is not input from the secondary DC output voltage line. That is, in this case, a tap is provided for the primary winding N1, and a half-wave rectifier circuit including a diode 63 and a capacitor 64 is provided for the tap output as shown in FIG. DC voltage is obtained. Then, this low-voltage DC voltage is connected to the collector of the transistor 54 via the resistor 58 and to the transistor 55 via the resistor 59. The output voltage from the error amplifier 34 in the control circuit 20 is applied to the point A at which the point VA voltage VA is obtained. The configuration of the error amplifier 34 shown in this figure may be the same as the circuit configuration in the control circuit 20 shown in FIG. 1, for example. However, in practice, it is necessary to insulate the primary side and the secondary side in a DC manner, so that the error amplifier 3
The output voltage applied from the point 4 to the point A is transmitted through, for example, a photocoupler.

Therefore, also in the circuit shown in FIG. 4, the conduction angle of the auxiliary switching element 17 is controlled according to the level of the secondary DC output voltage O1 fluctuating. In this case, the voltage resonance pulse V
1 will be varied. Voltage resonance pulse V
If the level of 1 is changed, the voltage level transmitted from the primary side to the secondary side of the converter transformer 3 also changes, and as a result, the secondary side DC output voltage EO1 obtained on the secondary side Can be variably controlled.
That is, the power supply circuit is stabilized.

Also in such a configuration, the switching timing of the auxiliary switching element 17 is determined by the drive voltage V3.
The switching operation is performed by applying the gate voltage Vgs generated by the above operation. When the auxiliary switching element 17 performs a switching operation, a current that should flow through the primary-side parallel resonance capacitor 6 is caused to flow through the clamp capacitor 16.
The peak level of the voltage resonance pulse V1 obtained at both ends of the primary side parallel resonance capacitor 6 is suppressed. That is, the primary-side active clamp circuit 32A provides an operation of clamping and suppressing the peak level of the voltage resonance pulse V1. In this case, the drive power supply circuit 33B for driving the auxiliary switching element 17 has the same circuit configuration as the drive power supply circuit 33 shown in FIG. , The auxiliary switching element 17 can be driven by obtaining a sufficient saturation state at the time of turning on, and rapidly extracting the gate charge at the time of turning off. You. Thus, even with the configuration of the power supply circuit shown in FIG. 4, the same effects as those of the above embodiments can be obtained.

In the power supply circuit shown in FIG. 4, since the operating power supply of the drive power supply circuit 33 is not required on the secondary side, a rectifying circuit system for generating the secondary side DC output voltage EO2 is provided. Omitted. However, in actuality, the circuit may be configured so that the secondary DC output voltage EO2, which is lower in voltage than the secondary DC output voltage EO1, can be generated and supplied to a required circuit unit. is there.

FIG. 5 shows a configuration example of a power supply circuit according to a fourth embodiment of the present invention. In this figure, the same parts as those in FIGS. 1, 3, and 5 are denoted by the same reference numerals, and description thereof will be omitted.

The basic circuit configuration on the primary side of the circuit shown in FIG. 5 is the same as that of the circuit shown in FIG.
That is, the main switching element 4 is inserted in series between the DC input voltage 1 and the primary winding. As the active clamp circuit, a primary side active clamp circuit 32A is provided on the primary side, and a driving power supply circuit 33B is also provided on the primary side.

In the circuit shown in this figure, the first converter transformer 3A and the second converter transformer 7
1, two converter transformers are provided. The first converter transformer here is, for example, a part equivalent to the converter transformer 3 shown in FIG. That is,
A primary converter N1 and a secondary winding N2 are wound around the first converter transformer 3A, so that the switching output obtained on the primary side is transmitted to the secondary side. A rectifier circuit for generating the DC output voltage EO1 is connected. A drive winding N3 is wound around the primary side of the first converter transformer 3A to generate a drive voltage V3 on the primary side.
In order to supply DC power to the drive power supply circuit 33B provided on the primary side, a diode 63 is connected to the primary winding side.
And a rectifier circuit comprising a capacitor 64.
In the first converter transformer 3A, the secondary parallel resonance capacitor 15 is connected in parallel to the secondary winding N2, thereby forming a secondary parallel resonance circuit. Therefore, as this power supply circuit, a configuration of a composite resonance type switching converter provided with a primary side parallel resonance circuit and a secondary side parallel resonance circuit is provided.

The second converter transformer 71 is configured by winding a primary winding N1-1 and a secondary winding N2-1. Second
The winding start end of the primary winding N1-1 of the converter transformer 71 is connected to a connection point between the winding start end of the primary winding N1 and the main switching element 4, and the winding end end is connected to the primary side ground. Connected. Thus, the primary winding N1-
With the connection of 1, the switching output of the main switching element 4 is supplied not only to the primary winding N1 of the first converter transformer 3A but also to the primary winding N1-1 of the second converter transformer 71. It will be supplied branched. Then, in the second converter transformer 71, the alternating voltage is excited in the secondary winding N2-1 by the switching output transmitted to the primary winding N1-1 in this manner. A rectifier diode 1 is used for the secondary winding N2-1.
3 and a rectifying circuit composed of a smoothing capacitor 14,
The secondary side DC output voltage EO2 is obtained. Thus, in the power supply circuit shown in FIG. 5, a plurality of converter transformers are provided, and each converter obtains a required level of secondary-side DC output voltage.

Then, in the circuit shown in FIG.
In addition to the control circuit 20, a frequency control / drive circuit 33 is provided. First, the control circuit 20 includes an error amplifier 34, for example, like the control circuit 20 shown in FIG.
An output voltage having a level varied according to the level change of the secondary DC output voltage EO2 is applied to the point A. Thereby, the primary side active clamp circuit 32
In the auxiliary switching element 17 of A, the variable control of the conduction period is performed according to the level change of the secondary side DC output voltage EO2.

The frequency control / drive circuit 33
Although a detailed description is omitted here, the main-side main switching element 4 is switched by self-excited or separately excited. That is, in this case, a drive signal (base current) for switching drive is caused to flow to the base of the main switching element 4. The secondary side DC output voltage EO1 is branched and input to the frequency control / drive circuit 33. The frequency control / drive circuit 33 generates and outputs a drive signal capable of changing the switching frequency of the main switching element 4 according to the change in the level of the input secondary-side DC output voltage EO1.

By operating the control circuit 20 and the frequency control / drive circuit 33 as described above, stabilization is achieved in the present embodiment as follows. That is, in this case, the control circuit 20 operates by detecting the level change of the secondary side DC output voltage EO2, but the control circuit 20 operates to reduce the conduction period of the auxiliary switching element 17. By being variably controlled, the peak level of the voltage resonance pulse V1 is variably controlled following the level change of the secondary DC output voltage EO2. In the circuit configuration shown in FIG. 5, the primary winding voltage e2 obtained at both ends of the primary winding N1-1 of the second converter transformer 71 changes according to the change in the peak level of the voltage resonance pulse V1. Become. Accordingly, the secondary DC output voltage EO2 generated by inputting the alternating voltage excited on the secondary side of the second converter transformer 71 is also varied.
That is, depending on the control circuit 20, a stabilizing operation for controlling the secondary side DC output voltage EO2 to be constant can be obtained.

Further, the frequency control / drive circuit 33
By variably controlling the switching frequency of the main switching element 4, an operation of changing the resonance impedance of the primary parallel resonance circuit to change the transmission energy from the primary side to the secondary side in the converter transformer can be obtained. Therefore, the level of the secondary DC output voltage can be variably controlled by variably controlling the switching frequency of the primary switching converter.

The frequency control / drive circuit 33 in this case operates so as to variably control the switching frequency in accordance with the level change of the secondary DC output voltage EO1. Depending on the operation, the secondary side DC output voltage EO1 is controlled to be constant. In this way, the circuit shown in FIG. 5 is configured to independently control the stabilization of the secondary DC output voltage EO1 and the secondary DC output voltage EO2. In the power supply circuit of FIG. 4 having such a configuration, the primary side active clamp circuit 3 is also provided.
The switching drive for the auxiliary switching element 17 in 2A is performed by inputting the drive voltage V3 and the drive power supply circuit 33B generating the gate voltage Vgs. Therefore, the same effects as those of the respective embodiments described above are obtained. It is possible to obtain.

Although the explanation by the illustration is omitted,
The following configuration can be adopted as a modification of the power supply circuit shown in FIG. That is, for the active clamp circuit and the drive power supply circuit, for example, the first converter transformer 3 according to the configuration of the power supply circuit shown in FIG.
Provided on the secondary side of A. Then, the conduction period of the auxiliary switching element 17 of the active clamp circuit is variably controlled in accordance with the level change of the secondary side DC output voltage EO1 obtained on the first converter transformer 3A side, so that the secondary side DC output The voltage EO1 is stabilized. On the other hand, regarding the stabilization of the secondary side DC output voltage EO2 obtained on the secondary side of the second converter transformer 71, the frequency control / drive circuit 33 performs main switching in accordance with the level change of the secondary side DC output voltage EO2. This is performed by variably controlling the switching frequency of the element 4. Further, the present invention can be applied to a power supply circuit including an active clamp circuit under combinations other than the above-described embodiments and the above-described modifications. For example, in the above-described embodiment, an example in which a parallel resonance circuit is provided on the secondary side as a composite resonance type switching converter has been described. For example, a composite resonance type switching converter having a series resonance circuit on the secondary side May be adopted.

[0075]

As described above, according to the present invention, a drive voltage (alternating voltage for driving) is generated by a drive winding for switching driving of an active clamp circuit whose conduction angle is controlled for stabilizing a power supply. The drive power supply circuit (drive signal generation means) uses the drive voltage to amplify and generate a gate voltage Vgs (drive pulse signal) at a predetermined level by amplification. With such a configuration, for example, it is possible to generate the gate voltage Vgs amplified to a level sufficient to bring the auxiliary switching element as a MOS-FET into a sufficiently saturated state and apply the gate voltage Vgs to the auxiliary switching element. For this reason, the ON resistance at the time of ON is reduced, and the switching loss is accordingly reduced. Thus, for example, a low-capacity auxiliary switching element can be selected. The low-capacity switching element is small and inexpensive. In addition, since heat generation is also reduced along with the loss reduction, for example, the heat radiating plate can be eliminated or the area can be reduced. That is, according to the present invention, the power supply circuit can be reduced in size and weight.

If the gate voltage Vgs is generated by the configuration of the present invention, for example, if a MOS-FET is selected for the auxiliary switching element,
The switching operation is not affected by variations in the characteristics of the gate threshold voltage Vth of the S-FET. Therefore, circuit design is facilitated, and component characteristic management is facilitated, so that manufacturing efficiency is improved.

In addition, under the above-mentioned configuration, by making the operation of extracting the electric charge when the auxiliary switching element is turned off, the descent time is shortened.
Switching losses will be further reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a switching power supply circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of a main part in the power supply circuit shown in FIG.

FIG. 3 is a circuit diagram illustrating a configuration example of a switching power supply circuit according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a configuration example of a switching power supply circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration example of a switching power supply circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a switching power supply circuit as a prior art.

7 is a waveform chart showing an operation of a main part in the power supply circuit shown in FIG.

[Explanation of symbols]

2 Leakage inductance, 3 converter transformer, N
1 Primary winding, N2 secondary winding, N3 drive winding, 4
Main switching element, 6 Primary parallel resonance capacitor, 31 Oscillation / drive circuit, 6 Primary parallel resonance capacitor, EO1, EO2 Secondary DC output voltage, 15
Secondary side parallel resonance capacitor, 20 control circuit, 21, 22
2 voltage dividing resistor, 24 error amplifier, 32 secondary side active clamp circuit, 32A primary side active clamp circuit, 16 clamp capacitor, 17 auxiliary switching element, 33 frequency control / drive circuit, 34 error amplifier, 51 resistor, 52 capacitor, 33, 33
A, 33B drive power supply circuit, 54, 56, 57 transistor, 71 second converter transformer, N1-1
Primary winding, N2-2 secondary winding

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[Procedure amendment]

[Submission date] May 9, 2001 (2001.5.9)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H730 AA02 AA14 AA16 AS01 BB23 BB57 BB77 BB82 DD02 DD41 EE02 EE07 EE19 EE30 EE59 EE65 FD01 FG07

Claims (2)

[Claims] 1. A switching means formed by including a main switching element for switching an input DC input voltage, a primary winding and a secondary winding are wound, and a switching output obtained on the primary winding is provided. To the secondary winding, formed by the leakage inductance of the primary winding or the inductance of an inductance element connected in series to the primary winding, and the capacitance of the primary side resonance capacitor. A primary-side parallel resonance circuit provided to make the operation of the switching means a voltage resonance type; a secondary-side resonance circuit formed by the secondary winding and a secondary-side resonance capacitor; DC output voltage generating means for obtaining a DC output voltage by inputting an alternating voltage obtained to the side resonance circuit and performing a rectification operation; The primary-side parallel resonance circuit or the secondary-side resonance capacitor is formed by connecting a series connection circuit including a switching capacitor and an auxiliary switching element in parallel with the primary-side parallel resonance capacitor or the secondary-side resonance capacitor and performing a switching operation. Active clamping means provided to clamp the peak level of the resonance voltage generated in the secondary parallel resonance circuit, and driving of a required level using the alternating voltage obtained in the primary winding or the secondary winding. A driving alternating voltage generating means for generating an alternating voltage, and amplifying by inputting the driving alternating voltage to generate and output a driving pulse signal having a predetermined level or more to be applied to the auxiliary switching element. Drive signal generating means, and an auxiliary switch driven by the drive pulse signal in accordance with a level change of the DC output voltage The conduction period of the grayed elements by variably controlling the switching power supply circuit, characterized in that the DC output voltage is provided with a constant voltage control means is controlled to be constant. 2. The charge extracting device according to claim 1, further comprising: a charge extracting unit that operates to extract electric charges of the auxiliary switching element based on the drive pulse signal at a timing of turning off the auxiliary switching element. Switching power supply circuit.