JP2002314038A - Power semiconductor module - Google Patents

Power semiconductor module

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Publication number
JP2002314038A
JP2002314038A JP2001118999A JP2001118999A JP2002314038A JP 2002314038 A JP2002314038 A JP 2002314038A JP 2001118999 A JP2001118999 A JP 2001118999A JP 2001118999 A JP2001118999 A JP 2001118999A JP 2002314038 A JP2002314038 A JP 2002314038A
Authority
JP
Japan
Prior art keywords
power semiconductor
semiconductor module
package
circuit pattern
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001118999A
Other languages
Japanese (ja)
Other versions
JP4465906B2 (en
Inventor
Akihiro Tanba
昭浩 丹波
Ryuichi Saito
隆一 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001118999A priority Critical patent/JP4465906B2/en
Publication of JP2002314038A publication Critical patent/JP2002314038A/en
Application granted granted Critical
Publication of JP4465906B2 publication Critical patent/JP4465906B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor module of an insulating transfer mold package which is reliable and suitable for water cooling. SOLUTION: The power semiconductor module comprises a power semiconductor chip, a circuit pattern to which the power semiconductor chip is bonded, a main terminal for supplying a current to the outside, and a control terminal for controlling the power semiconductor chip. In is sealed with a transfer mold package of a thermosetting resin. The upper surface of the package is provided with an opening part through which the circuit pattern is exposed, with the terminal bonded to the circuit pattern, and the terminal is disposed on the upper surface of the package. On the bottom surface of the package, a metal plate is exposed to surround the circuit pattern so that the metal plate makes direct contact with the cooling water.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、パワーＭＯＳＦＥ
Ｔ，ＩＧＢＴ(Insulated gate bipolar transistor）
等、高発熱パワー半導体素子を有するモジュール、及
び、このモジュールを備えたインバータに関する。The present invention relates to a power MOSFET.
T, IGBT (Insulated gate bipolar transistor)
The present invention relates to a module having a high heat-generating power semiconductor element and an inverter including the module.

【０００２】[0002]

【従来の技術】ハイブリッド電気自動車用モータ等、大
出力モータを制御する大容量インバータに使用する従来
技術のパワー半導体モジュールの断面構造模式図を図２
に示す。2. Description of the Related Art FIG. 2 is a schematic sectional view of a conventional power semiconductor module used in a large-capacity inverter for controlling a high-output motor such as a motor for a hybrid electric vehicle.
Shown in

【０００３】図２に示すように、ＩＧＢＴチップ２０，
ＦＷＤチップ２１を高温はんだ293で窒化アルミ基板２
９の銅パターンに接着し、ＩＧＢＴチップを搭載した窒
化アルミ基板を、ニッケルメッキ銅ベース２６に共晶は
んだ２９４で接着している。本構造で、ＩＧＢＴチップ
２０，ＦＷＤチップ２１とモジュール取付板でもある銅
ベース２６は電気的に絶縁され、同時にチップの熱は、
銅ベース２６に固着される放熱装置で、窒化アルミ基板
２９，銅ベース２６を通して放熱される。窒化アルミ基
板が搭載された銅ベース２６には、主端子２９１，空隙
２４，上ナット２２，制御端子２９０、及び、それに付
随した配線がケース中に一体成型した、いわゆるインサ
ートケース２３を、シリコーン接着材２５で接着する。
しかる後、チップと各端子はアルミニウムワイヤ２９２
で電気的に接続する。チップの封止は、いわゆる軟質レ
ジンであるシリコーンゲル２８で行い、モジュールのカ
バーを、蓋２７をシリコーン接着材２５で接着する。銅
ベース２６は、図２では平板であるが、より大容量のモ
ジュールで、さらに熱抵抗を低下する必要がある場合に
は、フィンを形成する。As shown in FIG. 2, an IGBT chip 20,
Aluminum nitride substrate 2 with FWD chip 21 using high-temperature solder 293
An aluminum nitride substrate having an IGBT chip mounted thereon is bonded to the copper pattern No. 9 with a eutectic solder 294 to the nickel-plated copper base 26. In this structure, the IGBT chip 20, the FWD chip 21 and the copper base 26 which is also a module mounting plate are electrically insulated, and at the same time, the heat of the chip is
A heat radiating device fixed to the copper base 26 radiates heat through the aluminum nitride substrate 29 and the copper base 26. A so-called insert case 23 in which a main terminal 291, an air gap 24, an upper nut 22, a control terminal 290, and wiring associated therewith are integrally formed in a case is bonded to a copper base 26 on which an aluminum nitride substrate is mounted by silicone bonding. Adhering with material 25.
Thereafter, the chip and each terminal are connected to the aluminum wire 292.
To make an electrical connection. The chip is sealed with a silicone gel 28 which is a so-called soft resin, and the cover of the module is adhered to the lid 27 with a silicone adhesive 25. Although the copper base 26 is a flat plate in FIG. 2, it is a module having a larger capacity, and a fin is formed when it is necessary to further reduce the thermal resistance.

【０００４】この従来技術では、窒化アルミ基板２９の
線膨張係数αが約４ppm ／℃であり、シリコンの線膨張
係数α３ppm ／℃に近く、チップ下はんだ２９３のはん
だ歪みが小さい。さらに、絶縁モジュールのため、例え
ばインバータ等への取付時に、電気的絶縁に配慮しなく
ても良い。このことは、銅ベース２６に直接冷却水を当
てて冷却する場合、絶縁への配慮無しに、銅ベース２６
で水路を強固に塞ぐことができる。In this prior art, the coefficient of linear expansion α of the aluminum nitride substrate 29 is about 4 ppm / ° C., which is close to the coefficient of linear expansion of silicon α 3 ppm / ° C., and the solder distortion of the solder 293 under the chip is small. Furthermore, because of the insulation module, it is not necessary to consider electrical insulation when attaching the module to, for example, an inverter. This means that when cooling is performed by directly applying cooling water to the copper base 26, the copper base 26 is
Can tightly close the waterway.

【０００５】図１４に、定格電圧／電流，６００Ｖ／１
５Ａクラスの別の従来技術による小容量３相ＩＧＢＴモ
ジュールを示す。図示していないが、リードフレーム
（Ｌ／Ｆ）上に、ＩＧＢＴ，ＦＷＤチップを接着し、こ
のリードフレームを、樹脂で絶縁したヒートシンクとと
もに、エポキシ樹脂１４０でトランスファモールド封止
している。主端子、及び、制御端子１４１は、リードフ
レームを切断して形成されている。本モジュールは取付
穴１４２部をネジで固定して、フィンが形成されたヒー
トシンクに固着される。FIG. 14 shows a rated voltage / current, 600 V / 1
5 shows another prior art small capacity three phase IGBT module of the 5A class. Although not shown, IGBT and FWD chips are bonded on a lead frame (L / F), and the lead frame is transfer-mold sealed with epoxy resin 140 together with a heat sink insulated with resin. The main terminal and the control terminal 141 are formed by cutting a lead frame. The module is fixed to a heat sink having fins by fixing the mounting holes 142 with screws.

【０００６】[0006]

【発明が解決しようとする課題】前記従来のパワー半導
体モジュールの構造、及び、その水冷構造には、冷却性
能，信頼性の面で以下の問題がある。図２の従来技術の
場合、窒化アルミ基板とシリコンの線膨張係数αが近い
為、チップ下はんだの高命が長い。しかし、銅ベースの
線膨張係数αは約１８ppm ／℃のため、窒化アルミ基板
とのミスマッチが大きく、窒化アルミ基板下はんだ２９
４は高歪みとなる。さらに、チップから冷媒への熱抵
抗、Ｒｔｈ（ｊ−ａ）を低減するために、銅ベース２６
にフィン等を形成し、冷却水を当てて直接水冷したとし
ても、窒化アルミ基板の熱抵抗が高いため全体の熱抵抗
が下がらない。The structure of the conventional power semiconductor module and its water-cooled structure have the following problems in terms of cooling performance and reliability. In the case of the prior art shown in FIG. 2, since the linear expansion coefficient α between the aluminum nitride substrate and silicon is close, the life of the solder under the chip is long. However, since the linear expansion coefficient α of the copper base is about 18 ppm / ° C., the mismatch with the aluminum nitride substrate is large, and the solder 29
No. 4 has high distortion. Further, in order to reduce the thermal resistance from the chip to the refrigerant, Rth (ja), the copper base 26
Even if fins or the like are formed and water cooling is performed directly by applying cooling water, the overall thermal resistance does not decrease because the aluminum nitride substrate has a high thermal resistance.

【０００７】図１４に示す従来技術のトランスファモー
ルドパッケージ（ＴＭ ＰＫＧ）は、端子をトランスフ
ァモールドパッケージ側面より出した構造であるため、
金属製の冷却装置に取り付けた場合、絶縁距離の確保が
困難であり、大容量パワー半導体モジュールに適用する
ことが困難である。The transfer mold package (TM PKG) of the prior art shown in FIG. 14 has a structure in which terminals are exposed from the side of the transfer mold package.
When it is attached to a metal cooling device, it is difficult to secure an insulation distance, and it is difficult to apply it to a large-capacity power semiconductor module.

【０００８】本発明の目的は、信頼性が高く、特に水冷
に適した、絶縁型トランスファモールドパッケージを提
供することである。An object of the present invention is to provide an insulating transfer mold package having high reliability and particularly suitable for water cooling.

【０００９】[0009]

【課題を解決するための手段】本発明のパワー半導体モ
ジュールでは、図１に示すように制御端子１３、及び、
主端子１４を搭載する為の開口部１１，１２をトランス
ファモールドパッケージ１７上面に設け、この開口部に
別部品である制御端子１３、及び、主端子１４を、リー
ドフレーム１５で構成した回路パターンに電気的に接着
し、端子をパッケージ上面に配置した。According to the power semiconductor module of the present invention, as shown in FIG.
Openings 11 and 12 for mounting the main terminals 14 are provided on the upper surface of the transfer mold package 17, and the control terminals 13 and the main terminals 14, which are separate components, are formed in the openings on the circuit pattern formed by the lead frame 15. Electrically bonded, the terminals were placed on the top of the package.

【００１０】本発明のパワー半導体モジュールの内部構
造は、図３に示すように、リードフレーム１５で回路パ
ターンを形成し、ＩＧＢＴ，ＦＷＤ等のパワー半導体チ
ップを、リードフレームに電気的に接着し、絶縁をリー
ドフレーム１５下面に接着した絶縁層３３で行う。As shown in FIG. 3, the internal structure of the power semiconductor module of the present invention is such that a circuit pattern is formed on a lead frame 15 and a power semiconductor chip such as IGBT or FWD is electrically bonded to the lead frame. Insulation is performed by the insulating layer 33 adhered to the lower surface of the lead frame 15.

【００１１】トランスファモールドパッケージ１７裏面
に直接冷却水を当てて冷却する場合、水路をパッケージ
１７底面で塞ぐ必要がある為、ネジ締め等で、冷却装置
に強固に取り付ける。本発明のパワー半導体モジュール
では、パッケージ外周底面にリードフレーム１０を配置
し、本リードフレーム１０と冷却装置を、パッケージ１
７の４隅の取付穴１６部をネジで強固に締め付ける。In the case of cooling by directly applying cooling water to the back surface of the transfer mold package 17, it is necessary to close the water channel with the bottom surface of the package 17, so that it is firmly attached to the cooling device by screwing or the like. In the power semiconductor module of the present invention, the lead frame 10 is disposed on the outer peripheral bottom surface of the package, and the lead frame 10 and the cooling device are connected to the package 1.
7 are firmly tightened at the four corner mounting holes 16 with screws.

【００１２】[0012]

【発明の実施の形態】本発明の実施例を、以下図面を使
用して詳細に説明する。 （実施例１）本実施例を、図１，図３から図８、及び図
１５から図１７を用いて説明する。本実施例は、定格電
圧／電流，６００Ｖ／２００ＡのＩＧＢＴ、及び、ＦＷ
Ｄチップを、各々２チップ並列接続した、定格電圧／電
流，６００Ｖ／４００Ａの１アームモジュール（パッケ
ージ）である。図１は本実施例のパッケージ(ＰＫＧ)外
観模式図であって、図３〜図５はパッケージ製造工程を
示す説明図、図６，図７はパッケージに接着される端子
の模式図、図８は図１の断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) This embodiment will be described with reference to FIGS. 1, 3 to 8 and FIGS. In this embodiment, an IGBT having a rated voltage / current of 600 V / 200 A and a FW
This is a one-arm module (package) having a rated voltage / current of 600 V / 400 A and two D chips connected in parallel. FIG. 1 is a schematic view of an external appearance of a package (PKG) according to this embodiment. FIGS. 3 to 5 are explanatory views showing a package manufacturing process. FIGS. 6 and 7 are schematic views of terminals bonded to the package. FIG. 2 is a sectional view of FIG.

【００１３】図３は本実施例のＩＧＢＴモジュールであ
って、ＩＧＢＴチップ２０，ＦＷＤチップ２１，チップ
抵抗３０各２チップを、共晶はんだ２９３でリードフレ
ーム（Ｌ／Ｆ）１５へ接着し、アルミニウムワイヤ２９
２，３６，３７でチップとリードフレーム１５間の接続
を行った後の平面図、及び断面図である。図３で、ＩＧ
ＢＴ２０，ＦＷＤ２１のチップサイズは各々概略１０mm
×１０mm，１０mm×６mmであり、チップ厚は約０.５mm
である。共晶はんだ２９３の膜厚は、０.１mmである。FIG. 3 shows an IGBT module according to this embodiment, in which two chips each of an IGBT chip 20, an FWD chip 21, and a chip resistor 30 are adhered to a lead frame (L / F) 15 by eutectic solder 293, and aluminum Wire 29
It is a top view and a sectional view after connection between a chip and a lead frame 15 is performed in 2, 36, and 37. In FIG.
BT20, FWD21 chip size is approximately 10mm each
× 10mm, 10mm × 6mm, chip thickness is about 0.5mm
It is. The thickness of the eutectic solder 293 is 0.1 mm.

【００１４】本実施例では、スクリーン印刷が容易な共
晶はんだ２９３のペーストをチップ接着に使用し工程を
簡素化した。もし、端子はんだ付け等で、封止後にパッ
ケージを１８０℃以上に加熱する場合があれば、チップ
接着はんだを、高温はんだとしても良い。アルミニウム
ワイヤの線径は３００μｍφで、ゲートワイヤ３６，補
助エミッタワイヤ３７を除くアルミニウムワイヤ数は、
ＩＧＢＴ２０，ＦＷＤ２１各チップ２４本である。な
お、ゲートワイヤ３６，補助エミッタワイヤ３７以外の
アルミニウムワイヤは、図面の簡略化のため、一対のＩ
ＧＢＴ２０，FWD２１チップのみについて示す。In this embodiment, the process is simplified by using a paste of eutectic solder 293, which is easy to screen-print, for chip bonding. If the package is heated to 180 ° C. or more after sealing by terminal soldering or the like, the chip bonding solder may be a high-temperature solder. The wire diameter of the aluminum wire is 300 μmφ, and the number of aluminum wires excluding the gate wire 36 and the auxiliary emitter wire 37 is:
The IGBT 20 and the FWD 21 each have 24 chips. In addition, aluminum wires other than the gate wire 36 and the auxiliary emitter wire 37 are a pair of I wires for simplification of the drawing.
Only the GBT20 and FWD21 chips are shown.

【００１５】リードフレーム１５の大きさは、７０mm×
６０mm、材質は無酸素銅（Ｃ1020)で表面にニッケルメ
ッキを３〜６μｍ形成しており、板厚は１mmである。IG
BT20，ＦＷＤ２１は、リードフレーム１５のコレクタパ
ターン３１に接着され、エミッタは、同じくエミッタパ
ターン３２へアルミニウムワイヤ２９２で接続される。
補助エミッタワイヤ３７は、リードフレームパターン３
４へ接続される。リードフレームパターン３５に接着さ
れた、ゲートに接続されるチップ抵抗３０は並列接続さ
れたＩＧＢＴ２０の発振を防止する為の抵抗である。冷
却に重要な大きさであるコレクタパターン３１の大きさ
は約５０mm×２５mmである。The size of the lead frame 15 is 70 mm ×
60 mm, the material is oxygen-free copper (C1020), nickel plating is formed on the surface at 3 to 6 μm, and the plate thickness is 1 mm. IG
The BT20 and the FWD 21 are bonded to the collector pattern 31 of the lead frame 15, and the emitter is connected to the emitter pattern 32 by the aluminum wire 292.
The auxiliary emitter wire 37 is connected to the lead frame pattern 3
4 is connected. The chip resistor 30 connected to the gate and bonded to the lead frame pattern 35 is a resistor for preventing oscillation of the IGBT 20 connected in parallel. The size of the collector pattern 31, which is important for cooling, is about 50 mm × 25 mm.

【００１６】リードフレームパターン３１の裏面には、
電気的絶縁用に、ビスマス酸化物系ガラス３３（熱伝導
率：３Ｗ／ｍ・℃）を膜厚２０μｍ塗布している。リー
ドフレーム１５の４隅には、パッケージ取付用穴１６を
形成しており、本取付穴１６は、各工程の位置決め用と
しても使用する。On the back surface of the lead frame pattern 31,
Bismuth oxide glass 33 (thermal conductivity: 3 W / m · ° C.) is applied to a thickness of 20 μm for electrical insulation. At four corners of the lead frame 15, package mounting holes 16 are formed, and the mounting holes 16 are also used for positioning in each process.

【００１７】アルミニウムワイヤボンディング後、タイ
バー４５の内側を、エポキシ樹脂でトランスファモール
ドする（第１トランスファモールド(１ｓｔ ＴＭ)、図
４）。使用した樹脂は、日立化成工業製エポキシ樹脂，
ＣＥＬ−９２００である。樹脂の種類は、パッケージの
反り，応力等を考慮して、最適な線膨張係数のものを選
択する。After aluminum wire bonding, the inside of the tie bar 45 is transfer-molded with epoxy resin (first transfer mold (1st TM), FIG. 4). The resin used was Hitachi Chemical's epoxy resin,
CEL-9200. The type of resin is selected from those having an optimum coefficient of linear expansion in consideration of the warpage, stress, and the like of the package.

【００１８】パッケージ４０形状は約５０mm×４０mm
で、リードフレーム下面からの厚さは約７mmであって、
この厚さが厚くなると、樹脂の硬化に長時間を要し、製
造タクトが悪くなるのでできるだけ薄くする。パッケー
ジ表面には、リードフレーム表面が露出した、コレクタ
電極はんだ接着用開口部４１，エミッタ電極接着用切り
欠き部４２が形成される。さらに、タイバー４５とパッ
ケージ切断後、制御用エミッタ端子接着部４３、及び、
ゲート端子接着部４４が形成される。コレクタ電極はん
だ接着用開口部４１の大きさは、約１７mm×１７mmであ
る。The shape of the package 40 is about 50 mm × 40 mm
The thickness from the bottom of the lead frame is about 7mm,
When the thickness is increased, it takes a long time to cure the resin, and the production tact is deteriorated. An opening 41 for soldering the collector electrode and a cutout 42 for bonding the emitter electrode are formed on the package surface so that the lead frame surface is exposed. Furthermore, after cutting the tie bar 45 and the package, the control emitter terminal bonding portion 43, and
A gate terminal bonding portion 44 is formed. The size of the collector electrode solder bonding opening 41 is about 17 mm × 17 mm.

【００１９】タイバー４５と切り離されたパッケージ
を、再び、タイバー４５とともにトランスファモールド
する（図５）。エポキシ樹脂で形成されたパッケージ５
０表面には、前述の開口部４１，切り欠き部４２、及
び、制御端子接続部４３，４４と同じ位置に、コレクタ
端子接着用開口部５２，エミッタ端子接着用開口部５
１，補助エミッタ端子接着用開口部５３，ゲート端子接
着用開口部５４が形成される。冷却装置に全面が固着さ
れるパッケージ外周底面のリードフレーム部５８、及
び、冷却水が当てられるリードフレーム部５７を除き、
パッケージ全体はエポキシ樹脂で封止される。パッケー
ジ５０裏面に回り込んだ樹脂部５５の厚みを加えた、パ
ッケージの厚さは約８.５mm である。樹脂部５５は、リ
ードフレーム５７をしっかりとかしめるため、リードフ
レーム５７上へ、オーバーラップした構造である。本実
施例では、オーバーラップ部の長さ５６は１.５mm とし
た。この長さは、長いほどしっかりとかしめることがで
きるので、パッケージの防水性は向上するが、熱伝達面
積が減少して熱抵抗が上昇するので、防水性，熱抵抗の
両者から長さ５６を決定する。図３に示すリードフレー
ム１５外周の切り欠き部３８は、リードフレーム１５を
樹脂でしっかりとかしめるためのものである。The package separated from the tie bar 45 is again transfer-molded together with the tie bar 45 (FIG. 5). Package 5 made of epoxy resin
In the surface 0, the collector terminal bonding opening 52 and the emitter terminal bonding opening 5 are located at the same positions as the opening 41, the notch 42, and the control terminal connecting parts 43 and 44.
1. An opening 53 for bonding an auxiliary emitter terminal and an opening 54 for bonding a gate terminal are formed. Except for a lead frame portion 58 on the outer peripheral bottom surface of the package where the entire surface is fixed to the cooling device, and a lead frame portion 57 to which cooling water is applied,
The entire package is sealed with epoxy resin. The thickness of the package is approximately 8.5 mm, including the thickness of the resin portion 55 that has wrapped around the back surface of the package 50. The resin portion 55 has a structure overlapping the lead frame 57 in order to firmly crimp the lead frame 57. In this embodiment, the length 56 of the overlap portion is 1.5 mm. The longer the length, the more firmly it can be swaged, so that the waterproofness of the package is improved. However, since the heat transfer area is reduced and the thermal resistance is increased, the length 56 is reduced from both the waterproofness and the thermal resistance. decide. The notch 38 on the outer periphery of the lead frame 15 shown in FIG. 3 is for firmly caulking the lead frame 15 with resin.

【００２０】図６は本実施例のモジュールの主端子（コ
レクタ，エミッタ端子）の模式図（斜視図，断面図）で
ある。端子６０は、ネジ締め用の貫通穴６４が形成され
た厚さ１.５mm のニッケルメッキ無酸素銅（Ｃ１０１
０）製銅板６１と、ナット６３とを、熱可塑性樹脂であ
るポリフェニレンサルファイド（ＰＰＳ）樹脂でインサ
ート成型して製造される。樹脂中には、ネジ逃げ用空隙
６２が形成され、端子６０底面にははんだ接着用の端子
露出部６５が形成されている。FIG. 6 is a schematic view (perspective view, sectional view) of the main terminals (collector and emitter terminals) of the module of this embodiment. The terminal 60 is a 1.5 mm-thick nickel-plated oxygen-free copper (C101) having a through hole 64 for screw fastening.
0) The copper plate 61 and the nut 63 are manufactured by insert-molding a polyphenylene sulfide (PPS) resin which is a thermoplastic resin. A screw clearance space 62 is formed in the resin, and a terminal exposed portion 65 for solder bonding is formed on the bottom surface of the terminal 60.

【００２１】図７は、本実施例のモジュールの制御端子
７０の模式図(斜視図，断面図)であって、図６の主端子
と同じく、厚さ１.５mm の無酸素銅製制御ピン７１がＰ
ＰＳ樹脂でインサート成型されている。端子下面には、
はんだ接着用露出部７２が形成されている。FIG. 7 is a schematic view (perspective view, cross-sectional view) of the control terminal 70 of the module of this embodiment. As in the case of the main terminal of FIG. 6, a control pin 71 made of oxygen-free copper having a thickness of 1.5 mm is provided. Is P
Insert molded with PS resin. On the underside of the terminal,
An exposed portion 72 for solder bonding is formed.

【００２２】上記、図６，図７に示した端子を図５に示
したパッケージにはんだ接着して、モジュール（パッケ
ージ）として完成させたのが、図１である。図１のＢ−
Ｂ断面を図８に示す。エミッタ端子８０，コレクタ端子
８１がリードフレーム上に共晶はんだ８２で接着されて
いる。本端子に、バスバーがネジ締めされる。この際、
端子にも締め付けトルクが加えられる、この力が、はん
だ８２に直接加えられると、はんだにクラックが発生す
ることもあるので、本実施例では、パッケージと端子８
０，８１の隙間に端子接着用硬質レジン８３を流して、
接着しクラック発生を回避している。図示していない
が、制御端子部にも同じ樹脂がポッティングされてい
る。FIG. 1 shows that the terminals shown in FIGS. 6 and 7 are soldered to the package shown in FIG. 5 to complete a module (package). B- in FIG.
FIG. 8 shows a cross section B. The emitter terminal 80 and the collector terminal 81 are adhered on the lead frame by eutectic solder 82. The bus bar is screwed to this terminal. On this occasion,
A tightening torque is also applied to the terminals. If this force is applied directly to the solder 82, cracks may occur in the solder.
The hard resin 83 for terminal bonding is flowed into the gap between 0 and 81,
Adhesion prevents cracks. Although not shown, the same resin is also potted on the control terminal portion.

【００２３】以上、主端子，制御端子が接続され、完成
したパッケージ１７を冷却装置に接続した断面図を図１
５に示す。様々な回路部品が搭載される回路ケース１５
０に、ガスケット１５１を配置し、このガスケットでパ
ッケージ１７底面の周囲に配置されたパッケージ取付リ
ードフレーム１０と回路ケース１５０を固着させて、パ
ッケージ１７底面と水路カバー１５２とで水路１５３を
形成する。この水路幅１５４は５mmである。使用する樹
脂製ガスケット１５１の平面図を図１６に示す。モジュ
ール取付部１６０以外の幅は５mmである。パッケージを
ネジで締め付けて冷却水をシールする場合、締付けネジ
間のパッケージがたわむと冷却水が漏洩し易くなる。ト
ランスファモールド樹脂でリードフレーム１０を補強し
て、取付部の剛性を増大させると漏洩防止に効果があ
る。FIG. 1 is a cross-sectional view in which the main terminal and the control terminal are connected, and the completed package 17 is connected to the cooling device.
It is shown in FIG. Circuit case 15 on which various circuit components are mounted
A gasket 151 is disposed on the package 17, and the package mounting lead frame 10 disposed around the bottom surface of the package 17 is fixed to the circuit case 150 with the gasket. The channel width 154 is 5 mm. FIG. 16 shows a plan view of the resin gasket 151 to be used. The width other than the module mounting portion 160 is 5 mm. When the package is tightened with a screw to seal the cooling water, if the package is bent between the tightening screws, the cooling water is likely to leak. Reinforcing the lead frame 10 with transfer mold resin to increase the rigidity of the mounting portion is effective in preventing leakage.

【００２４】上記のように構成した水路１５３に、エチ
レングリコールを主成分とした冷却水を流し、漏水試験
をした。２００ＫＰａの水圧を印加し、数分経過しても
水路外への冷却水の漏洩はなかった。さらに、パッケー
ジ１７の全端子と回路ケース間の絶縁耐圧が３.５ＫＶ
ｒｍｓ／１ 分以上であることを確認し、併せて素子の
リーク電流増加も全く見られないことや、パッケージ中
への冷却水浸入も全く問題ないことを確認した。ハイブ
リッド自動車用等への応用では、現実的なポンプ能力
は、数１０ＫＰａであるので、本実施例のパッケージ構
造は、実際の水冷用パッケージとして十分である。また
ＩＧＢＴチップジャンクションから冷却水への熱抵抗、
Ｒｔｈ（ｊ−ｗ）は、０.１８℃／Ｗ(冷却水流速：３ｍ
／ｓ）と低い値であった。A water leak test was conducted by flowing cooling water containing ethylene glycol as a main component through the water channel 153 configured as described above. After applying a water pressure of 200 KPa, there was no leakage of the cooling water outside the water channel even after several minutes. Further, the withstand voltage between all terminals of the package 17 and the circuit case is 3.5 KV.
It was confirmed that the rate was rms / min or more, and it was also confirmed that there was no increase in the leak current of the device and that there was no problem in infiltration of cooling water into the package. In an application to a hybrid vehicle or the like, the actual pumping capacity is several tens of KPa, so the package structure of the present embodiment is sufficient as an actual water cooling package. Also, the thermal resistance from the IGBT chip junction to the cooling water,
Rth (j−w) is 0.18 ° C./W (cooling water flow rate: 3 m
/ S), which is a low value.

【００２５】図１７は、本パッケージで構成した３相イ
ンバータの断面図である。図１７ではインンバータの入
出力端子は省略している。インバータケース兼水路カバ
ー１７０４に本実施例のパッケージ１７を６個固着して
水路１７０を構成している。絶縁板１７０７をＮバスバ
ー１７３，Ｐバスバー１７４でサンドイッチして低イン
ダクタンス配線とし、ネジ１７０８でパッケージ１７に
固着している。出力配線１７５も同様にネジ１７０８で
パッケージに固着され、カレントトランス１７０２に接
続される。スナバコンデンサである電解コンデンサ１７
７をインバータケース１７０４底面に熱伝導シート等で
固着する。電解コンデンサ１７７，ゲートドライバー１
７００，トランス１７８等が搭載された、電源回路及び
ゲート回路基板であるプリント回路基板１７２は、パッ
ケージの制御端子に、前記バスバー上に配置されてスル
ーホールはんだ接着してある。マイコン１７９等が搭載
されたプリント回路基板１７１は、インバータ底蓋１７
０３に固定され、インタフェースケーブル１７０１で電
源回路及びゲート回路基板１７２に接続される。インバ
ータ上蓋１７０５，インバータケース１７０４，底蓋１
７０３は全てネジ１７０６で固着される。なお、各ケー
スの締付けには、必要に応じメタルガスケットが使用さ
れる。以上の構成で、パワー回路，制御回路とも熱的に
問題無い構造が実現できた。FIG. 17 is a sectional view of a three-phase inverter constituted by this package. In FIG. 17, the input / output terminals of the inverter are omitted. The water passage 170 is formed by fixing six packages 17 of the present embodiment to the inverter case / water passage cover 1704. The insulating plate 1707 is sandwiched between the N bus bar 173 and the P bus bar 174 to form a low inductance wiring, and is fixed to the package 17 with screws 1708. The output wiring 175 is similarly fixed to the package with screws 1708 and connected to the current transformer 1702. Electrolytic capacitor 17 which is a snubber capacitor
7 is fixed to the bottom of the inverter case 1704 with a heat conductive sheet or the like. Electrolytic capacitor 177, gate driver 1
A printed circuit board 172, which is a power supply circuit and a gate circuit board, on which the 700, the transformer 178, and the like are mounted, is disposed on the bus bar to the control terminal of the package, and is through-hole soldered. The printed circuit board 171 on which the microcomputer 179 and the like are mounted is
03, and is connected to the power supply circuit and the gate circuit board 172 by the interface cable 1701. Inverter top cover 1705, inverter case 1704, bottom cover 1
703 are all fixed with screws 1706. A metal gasket is used for tightening each case as necessary. With the above configuration, a structure having no thermal problem in both the power circuit and the control circuit was realized.

【００２６】（実施例２）図９に本実施例を示す。本実
施例では、ＩＧＢＴ２０，ＦＷＤ２１チップを搭載する
パターンをリードフレームではなく、窒化アルミ基板９
０に形成し、この基板に高温はんだ９２でチップを接着
する。リードフレーム９１はタイバー４５，エミッタ配
線パターン３２，補助エミッタパターン３４，ゲートパ
ターン３５，パッケージ取付穴１６を備えており、窒化
アルミ基板９０を取り囲む。チップ抵抗３０は、チップ
接着と同時に高温はんだでリードフレームに接着され
る。窒化アルミ基板９０とリードフレーム９１の裏面は
同一面となるように配置され、アルミニウムワイヤ２９
２，３６，３７で電気的な配線をする。封止は、前記図
４，図５と同様な構造であり、パッケージサイズも同一
である。本実施例で、冷却水が当たる面９３は、窒化ア
ルミ基板９０の裏面銅板であり、この銅板にはニッケル
メッキが３〜６μｍ施されている。従って、冷却水に対
する腐食問題が無い。さらに、窒化アルミの熱伝導率は
１７０℃／ｍ・Ｗであり、熱抵抗も十分小さく、実施例
１と同じ、流速３ｍ／ｓの冷却水の条件測定したＲｔｈ
（ｊ−ｗ）は０.１８℃／Ｗ である。また、冷却装置へ
の取付は実施例１と同じくタイバー４５で行い、冷却水
の十分なシール性を確認した。(Embodiment 2) FIG. 9 shows this embodiment. In this embodiment, the pattern for mounting the IGBT 20 and FWD 21 chips is not a lead frame but an aluminum nitride substrate 9.
0, and the chip is bonded to this substrate with a high-temperature solder 92. The lead frame 91 includes a tie bar 45, an emitter wiring pattern 32, an auxiliary emitter pattern 34, a gate pattern 35, and a package mounting hole 16, and surrounds the aluminum nitride substrate 90. The chip resistor 30 is bonded to the lead frame by high-temperature solder simultaneously with the chip bonding. The aluminum nitride substrate 90 and the back surface of the lead frame 91 are arranged so as to be flush with each other.
Electrical wiring is performed at 2, 36, and 37. The sealing has the same structure as in FIGS. 4 and 5, and the package size is also the same. In this embodiment, the surface 93 to which the cooling water is applied is a copper plate on the back surface of the aluminum nitride substrate 90, which is plated with nickel to 3 to 6 μm. Therefore, there is no corrosion problem with the cooling water. Further, the thermal conductivity of the aluminum nitride is 170 ° C./m·W, the thermal resistance is sufficiently small, and the Rth measured under the same conditions as in Example 1 with the cooling water flow rate of 3 m / s.
(J−w) is 0.18 ° C./W. Further, attachment to the cooling device was performed using the tie bar 45 as in Example 1, and sufficient sealing performance of the cooling water was confirmed.

【００２７】（実施例３）冷却水の純度を上昇させた
り、冷却媒体に絶縁性のオイルを使用すれば、パッケー
ジ外で絶縁できるため、絶縁層は削除することができ
る。本実施例は、非絶縁モジュールの実施例であって、
実施例１のガラス層３３を削除している以外はパッケー
ジ４０，１００の形状を含め、実施例１と同一である。
本実施例では、冷却水の純度管理が重要であるが、熱抵
抗は、上記二つの実施例よりも低減できた。実施例１と
同条件で測定したＲｔｈ（ｊ−ｗ）は０.１６℃／Ｗ で
あった。(Embodiment 3) If the purity of the cooling water is increased, or if an insulating oil is used for the cooling medium, the insulation can be achieved outside the package, so that the insulating layer can be omitted. This embodiment is an embodiment of a non-insulated module,
It is the same as the first embodiment including the shapes of the packages 40 and 100 except that the glass layer 33 of the first embodiment is omitted.
In this embodiment, although the purity control of the cooling water is important, the thermal resistance was able to be reduced as compared with the above two embodiments. Rth (j−w) measured under the same conditions as in Example 1 was 0.16 ° C./W 2.

【００２８】（実施例４）主端子も制御端子と同様に、
ピンのはんだ接着とした本実施例を図１１に示す。図
１，図８のコレクタ，エミッタ端子形状が、コレクタ端
子１１０，エミッタ端子１１１に代わっている以外は、
実施例１と同じである。端子１１０，１１１のピンの断
面形状は制御端子１３と同一であり、電流容量を考慮し
て、各６本のピンをＰＰＳ樹脂でインサート成型して端
子としている。この構造で、端子の抵抗は、実施例１の
端子８０，８１とほぼ同じであった。バスバーへの接続
は、例えば、制御回路基板であるプリント回路基板（Ｐ
ＣＢＢ）に、主電流用の厚い銅板を接着して、この銅
板、及び、プリント回路基板にスルーホールを形成して
共晶はんだでスルーホールはんだ接着すれば良い。(Embodiment 4) The main terminals are also similar to the control terminals.
FIG. 11 shows this embodiment in which the pins are bonded by soldering. 1 and 8, except that the collector and emitter terminals are replaced by the collector terminal 110 and the emitter terminal 111.
This is the same as the first embodiment. The cross-sectional shapes of the pins of the terminals 110 and 111 are the same as those of the control terminal 13, and in consideration of the current capacity, each of the six pins is insert-molded with PPS resin to form the terminals. In this structure, the resistance of the terminals was almost the same as the terminals 80 and 81 of the first embodiment. The connection to the bus bar is made, for example, by a printed circuit board (P
A thick copper plate for the main current may be bonded to CBB), a through hole may be formed in the copper plate and the printed circuit board, and the through hole may be bonded by eutectic solder.

【００２９】（実施例５）本実施例は、第２モールドを
トランスファモールドでなく、熱硬化型硬質レジンのポ
ッティング封止とした。図１２に第２モールド前の平面
構造模式図、図１３にポッティング後の平面図、及び側
面図を示す。図１２は図４に示した第１トランスファモ
ールドパッケージに、主端子８０，８１、制御端子１３
をはんだ接着した形状を示す。実施例１ではタイバー４
５もトランスファモールド封止後に端子を接着している
が、本実施例では、第２モールド実施前に接着してい
て、信頼性に全く問題の無い構造である。Embodiment 5 In this embodiment, the second mold is not a transfer mold but a potting seal of a thermosetting hard resin. FIG. 12 shows a schematic plan view before the second mold, and FIG. 13 shows a plan view and a side view after potting. FIG. 12 shows the main terminals 80 and 81 and the control terminals 13 in the first transfer mold package shown in FIG.
Shows the shape in which is solder-bonded. In the first embodiment, the tie bar 4 is used.
5 also has terminals bonded after transfer molding sealing, but in this embodiment, the terminals are bonded before the second molding is performed, and the structure has no problem in reliability at all.

【００３０】本実施例では、第２モールドをＰＰＳ等の
熱可塑性樹脂で封止しても良い。さらに、リードフレー
ム形状によっては、第１，２モールドに分けずに一回の
ポッティングで封止しても良い。In this embodiment, the second mold may be sealed with a thermoplastic resin such as PPS. Further, depending on the shape of the lead frame, sealing may be performed by one potting without dividing into the first and second molds.

【００３１】[0031]

【発明の効果】本発明によれば、熱抵抗が低く、信頼性
が高いトランスファモールド型半導体モジュールを容易
に実現できる。According to the present invention, a transfer mold type semiconductor module having low thermal resistance and high reliability can be easily realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施例１の半導体モジュールの説明図である。FIG. 1 is an explanatory diagram of a semiconductor module according to a first embodiment.

【図２】従来技術の半導体モジュールの断面模式図であ
る。FIG. 2 is a schematic sectional view of a conventional semiconductor module.

【図３】実施例１の半導体モジュールの製造工程の説明
図である。FIG. 3 is an explanatory diagram of a manufacturing process of the semiconductor module of the first embodiment.

【図４】実施例１の半導体モジュールの製造工程の説明
図である。FIG. 4 is an explanatory diagram of a manufacturing process of the semiconductor module according to the first embodiment.

【図５】実施例１の半導体モジュールの製造工程の説明
図である。FIG. 5 is an explanatory diagram of a manufacturing process of the semiconductor module of the first embodiment.

【図６】実施例１の半導体モジュールの主端子の説明図
である。FIG. 6 is an explanatory diagram of main terminals of the semiconductor module according to the first embodiment.

【図７】実施例１の半導体モジュールの制御端子の説明
図である。FIG. 7 is an explanatory diagram of control terminals of the semiconductor module according to the first embodiment.

【図８】実施例１の半導体モジュールの断面模式図であ
る。FIG. 8 is a schematic cross-sectional view of the semiconductor module according to the first embodiment.

【図９】実施例２の半導体モジュールの断面模式図であ
る。FIG. 9 is a schematic sectional view of a semiconductor module according to a second embodiment.

【図１０】実施例３の半導体モジュールの断面模式図で
ある。FIG. 10 is a schematic sectional view of a semiconductor module according to a third embodiment.

【図１１】実施例４の半導体モジュールの断面模式図で
ある。FIG. 11 is a schematic sectional view of a semiconductor module according to a fourth embodiment.

【図１２】実施例５の半導体モジュールの平面図であ
る。FIG. 12 is a plan view of a semiconductor module according to a fifth embodiment.

【図１３】実施例５の半導体モジュールのポッティング
封止の説明図である。FIG. 13 is an explanatory diagram of potting sealing of the semiconductor module of the fifth embodiment.

【図１４】従来技術のトランスファモールドパッケージ
の説明図である。FIG. 14 is an explanatory diagram of a transfer mold package according to the related art.

【図１５】実施例１の半導体モジュールを実装し、水路
を形成した説明図である。FIG. 15 is an explanatory diagram in which the semiconductor module of Example 1 is mounted and a water channel is formed.

【図１６】図１６の水路を形成する際に用いるガスケッ
トの模式図である。FIG. 16 is a schematic view of a gasket used when forming the water channel of FIG.

【図１７】実施例１の半導体モジュールを用いた水冷イ
ンバータの断面図である。FIG. 17 is a sectional view of a water-cooled inverter using the semiconductor module of the first embodiment.

【符号の説明】[Explanation of symbols]

１０，５８…パッケージ（ＰＫＧ）取付け用リードフレ
ーム（Ｌ／Ｆ）、１１…制御端子接着用開口部、１２…
主端子接着用開口部、１３，７０…制御端子、１４，６
０…主端子、１５，９１…リードフレーム、１６…パッ
ケージ取付穴、１７…トランスファーモールドパッケー
ジ（ＴＭ ＰＫＧ）、２０…ＩＧＢＴチップ、２１…Ｆ
ＷＤチップ、２２，６３…主端子取付け用ナット、２３
…インサートケース、２４，６２…ネジ逃げ用空隙、２
５…シリコーン接着材、２６…銅ベース、２７…モジュ
ール蓋、２８…シリコーンゲル、２９，９０…窒化アル
ミ基板、３０…チップ抵抗、３１…リードフレームコレ
クタパターン、３２…リードフレームエミッタパター
ン、３３…ガラス層、３４…リードフレーム補助エミッ
タパターン、３５…リードフレームゲートパターン、３
６…ゲートアルミニウムワイヤ、３７…補助エミッタア
ルミニウムワイヤ、３８…リードフレーム切り欠き部、
４０…第１トランスファモールドパッケージ、４１…コ
レクタ端子はんだ接着用開口部、４２…エミッタ端子は
んだ接着用切り欠き部、４３…補助エミッタ端子接着
部、４４…ゲート端子接着部、４５…タイバー、５０，
１００…第２トランスファモールドパッケージ、５１…
エミッタ端子接着用開口部、５２…コレクタ端子接着用
開口部、５３…補助エミッタ端子接着用開口部、５４…
ゲート端子接着用開口部、５５…パッケージ裏面封止樹
脂、５６…リードフレームコレクタパターン／樹脂オー
バーラップ長さ、５７…放熱用リードフレーム部、６１
…主端子用銅板、６４…ネジ締付け用穴、６５，７２…
接着用端子露出部、７１…制御端子銅ピン、８０，１１
１…エミッタ端子、８１，１１０…コレクタ端子、８２
…端子接着用はんだ、８３…端子接着用硬質レジン、９
２，２９３…チップ接着はんだ、９３…冷却面、１３０
…パッケージ（ポッティングで形成）、１４０…従来の
トランスファモールドパッケージ、１４１…主端子、及
び、制御端子、１４２…パッケージ取付穴、１５０…回
路ケース、１５１…ガスケット、１５２…水路カバー、
１５３，１７０…水路、１５４…水路幅、１６０…パッ
ケージ取付部穴、１７１，１７２…プリント回路基板、
１７３…Ｎ（グランド）バスバー配線、１７４…Ｐ（電
源）バスバー配線、１７５…出力配線、１７６，１７７
…電解コンデンサ、１７８…トランス、１７９…マイコ
ン、２９０…制御端子、２９１…主端子、２９２…アル
ミワイヤ、２９４…基板接着はんだ、1700…ゲートドラ
イバー、１７０１…インタフェースケーブル、１７０２
…カレントトランス、１７０３…インバータ底蓋、１７
０４…インバータケース兼水路カバー、１７０５…イン
バータ上蓋、１７０６…ケース取付ネジ、１７０７…
Ｐ，Ｎバスバー絶縁板。10, 58: Lead frame (L / F) for mounting package (PKG), 11: Opening for bonding control terminals, 12:
Openings for main terminal bonding, 13, 70 ... control terminals, 14, 6
0: Main terminal, 15, 91: Lead frame, 16: Package mounting hole, 17: Transfer mold package (TM PKG), 20: IGBT chip, 21: F
WD chip, 22, 63 ... Main terminal mounting nut, 23
... insert case, 24, 62 ... screw clearance, 2
5 Silicone adhesive, 26 Copper base, 27 Module lid, 28 Silicon gel, 29, 90 Aluminum nitride substrate, 30 Chip resistance, 31 Lead frame collector pattern, 32 Lead frame emitter pattern, 33 Glass layer, 34: lead frame auxiliary emitter pattern, 35: lead frame gate pattern, 3
6 ... gate aluminum wire, 37 ... auxiliary emitter aluminum wire, 38 ... lead frame notch,
Reference numeral 40: a first transfer mold package; 41, an opening for solder bonding of a collector terminal; 42, a cutout for solder bonding of an emitter terminal; 43, a bonding portion of an auxiliary emitter terminal; 44, a bonding portion of a gate terminal;
100 ... second transfer mold package, 51 ...
Opening for bonding emitter terminals, 52: Opening for bonding collector terminals, 53: Opening for bonding auxiliary emitter terminals, 54:
Gate terminal bonding opening, 55: package back sealing resin, 56: lead frame collector pattern / resin overlap length, 57: heat dissipation lead frame, 61
... Copper plate for main terminal, 64 ... Hole for screw tightening, 65, 72 ...
Exposed terminal for bonding, 71 ... copper pin for control terminal, 80, 11
1: Emitter terminal, 81, 110: Collector terminal, 82
... Solder for terminal bonding, 83 ... Hard resin for terminal bonding, 9
2,293: chip bonding solder, 93: cooling surface, 130
... package (formed by potting), 140 ... conventional transfer mold package, 141 ... main terminal and control terminal, 142 ... package mounting hole, 150 ... circuit case, 151 ... gasket, 152 ... water channel cover,
153, 170: water channel, 154: water channel width, 160: package mounting portion hole, 171, 172: printed circuit board,
173 ... N (ground) bus bar wiring, 174 ... P (power) bus bar wiring, 175 ... output wiring, 176,177
... Electrolytic capacitor, 178 ... Transformer, 179 ... Microcomputer, 290 ... Control terminal, 291 ... Main terminal, 292 ... Aluminum wire, 294 ... Board adhesive solder, 1700 ... Gate driver, 1701 ... Interface cable, 1702
... Current transformer, 1703 ... Inverter bottom cover, 17
04 ... Inverter case and water channel cover, 1705 ... Inverter top cover, 1706 ... Case mounting screw, 1707 ...
P, N busbar insulating plate.

Claims (19)

【特許請求の範囲】[Claims] 【請求項１】パワー半導体チップと、該パワー半導体チ
ップが接着される回路パターンと、該パワー半導体チッ
プの電流を外部へ通電する主端子と、該パワー半導体チ
ップを制御する制御端子、とを備え、熱硬化性樹脂によ
るトランスファモールドパッケージで封止されたパワー
半導体モジュールにおいて、 前記パワー半導体モジュール上面に、前記回路パターン
が露出した開口部を設け、前記主端子、及び、制御端子
を前記回路部へ接着することにより全端子を前記パワー
半導体モジュール上面に配置し、前記パワー半導体モジ
ュール底面には、前記回路パターンを取り囲む位置に金
属板が露出しており、該金属板を水冷装置へ取り付ける
ことにより、前記パワー半導体モジュール底面で冷却水
をシールしてパワー半導体を冷却することを特徴とする
パワー半導体モジュール。1. A power semiconductor chip comprising: a power semiconductor chip; a circuit pattern to which the power semiconductor chip is bonded; a main terminal for supplying a current of the power semiconductor chip to the outside; and a control terminal for controlling the power semiconductor chip. In a power semiconductor module sealed with a transfer mold package made of a thermosetting resin, an opening where the circuit pattern is exposed is provided on an upper surface of the power semiconductor module, and the main terminal and the control terminal are connected to the circuit portion. By bonding, all terminals are arranged on the upper surface of the power semiconductor module, and on the bottom surface of the power semiconductor module, a metal plate is exposed at a position surrounding the circuit pattern, and by attaching the metal plate to a water cooling device, Sealing the cooling water at the bottom of the power semiconductor module to cool the power semiconductor. Characteristic power semiconductor module. 【請求項２】請求項１において、前記回路パターン、及
び、前記パワー半導体モジュール底面の金属板が、リー
ドフレームで構成されていることを特徴とするパワー半
導体モジュール。2. The power semiconductor module according to claim 1, wherein the circuit pattern and the metal plate on the bottom surface of the power semiconductor module are formed of a lead frame. 【請求項３】請求項２において、前記リードフレーム
は、アルミニウム、又は、銅、又は、それらの合金であ
ることを特徴とするパワー半導体モジュール。3. The power semiconductor module according to claim 2, wherein said lead frame is made of aluminum, copper, or an alloy thereof. 【請求項４】請求項２において、前記冷却水シール用リ
ードフレームを除く前記回路パターンを、第１の熱硬化
性樹脂のトランスファモールドパッケージ（第１トラン
スファモールドパッケージ）に内蔵し、該第１トランス
ファモールドパッケージを、前記冷却水シール用リード
フレームとともに第２の熱硬化性樹脂のトランスファモ
ールドパッケージに内蔵したことを特徴とするパワー半
導体モジュール。4. The first transfer mold package according to claim 2, wherein the circuit pattern excluding the cooling water sealing lead frame is incorporated in a first thermosetting resin transfer mold package (first transfer mold package). A power semiconductor module, wherein a mold package is incorporated in a transfer mold package of a second thermosetting resin together with the cooling water sealing lead frame. 【請求項５】請求項４において、前記トランスファモー
ルドパッケージ上面開口部と、前記接着された端子のギ
ャップを、熱硬化性樹脂で接着することを特徴とするパ
ワー半導体モジュール。5. The power semiconductor module according to claim 4, wherein a gap between the upper surface of the transfer mold package and the bonded terminal is bonded with a thermosetting resin. 【請求項６】請求項２において、前記冷却水シール用リ
ードフレームを除く前記回路パターンを第１の熱硬化性
樹脂のトランスファモールドパッケージ（第１トランス
ファモールドパッケージ）に内蔵し、該第１トランスフ
ァモールドパッケージ上面の前記開口部に前記主端子、
及び、制御端子を配置し、該端子付き第１トランスファ
モールドパッケージを、前記冷却水シール用リードフレ
ームとともに第２の熱硬化性樹脂のポッティングパッケ
ージに内蔵したことを特徴とするパワー半導体モジュー
ル。6. The first transfer mold according to claim 2, wherein the circuit pattern excluding the cooling water sealing lead frame is incorporated in a first thermosetting resin transfer mold package (first transfer mold package). The main terminal in the opening on the top surface of the package,
A power semiconductor module, wherein control terminals are arranged, and the first transfer mold package with the terminals is incorporated in a second thermosetting resin potting package together with the cooling water sealing lead frame. 【請求項７】請求項２において、前記冷却水シール用リ
ードフレームが、前記回路パターン用リードフレームの
周囲を取り囲むタイバーであることを特徴とするパワー
半導体モジュール。7. The power semiconductor module according to claim 2, wherein the lead frame for cooling water sealing is a tie bar surrounding the periphery of the lead frame for circuit pattern. 【請求項８】請求項２において、前記冷却水シール用リ
ードフレームを除く前記回路パターンを第１の熱硬化性
樹脂のトランスファモールドパッケージ（第１トランス
ファモールドパッケージ）に内蔵し、該第１トランスフ
ァモールドパッケージ上面の前記開口部に前記主端子、
及び、制御端子を配置し、該端子付き第１トランスファ
モールドパッケージを、前記冷却水シール用リードフレ
ームとともに熱可塑性樹脂で一体パッケージとしたこと
を特徴とするパワー半導体モジュール。8. The first transfer mold according to claim 2, wherein the circuit pattern excluding the cooling water sealing lead frame is incorporated in a first thermosetting resin transfer mold package (first transfer mold package). The main terminal in the opening on the top surface of the package,
A power semiconductor module, wherein control terminals are arranged, and the first transfer mold package with the terminals is integrally formed of a thermoplastic resin together with the cooling water sealing lead frame. 【請求項９】請求項８において、前記熱可塑性樹脂が、
ポリフェニレンサリファイド樹脂であることを特徴とす
るパワー半導体モジュール。9. The method according to claim 8, wherein the thermoplastic resin is:
A power semiconductor module comprising a polyphenylene sulfide resin. 【請求項１０】パワー半導体チップと、該パワー半導体
チップが接着される回路パターンと、該パワー半導体チ
ップの電流を外部へ通電する主端子と、該パワー半導体
チップを制御する制御端子、とを備えたパワー半導体モ
ジュールにおいて、 前記回路パターンに前記主端子及び制御端子が接着さ
れ、前記全端子が前記パワー半導体モジュール上面に配
置されるように、全体を熱硬化性樹脂で一体のポッティ
ングモールドパッケージとし、該パッケージ底面には、
前記回路パターンを取り囲む位置に金属板を露出させ、
該金属板を水冷装置へ取り付けることにより、冷却水を
シールすることを特徴とするパワー半導体モジュール。10. A power semiconductor chip comprising: a power semiconductor chip; a circuit pattern to which the power semiconductor chip is adhered; a main terminal for supplying a current of the power semiconductor chip to the outside; and a control terminal for controlling the power semiconductor chip. In the power semiconductor module, the main terminal and the control terminal are adhered to the circuit pattern, and the entire terminal is made of a thermosetting resin as an integral potting mold package so that all the terminals are arranged on the upper surface of the power semiconductor module. On the bottom of the package,
Exposing a metal plate at a position surrounding the circuit pattern,
A power semiconductor module, wherein cooling water is sealed by attaching the metal plate to a water cooling device. 【請求項１１】請求項１において、前記回路パターン
は、リードフレーム、及び、金属回路パターン／セラミ
クス／金属パターンの積層構造からなる基板、又は、金
属回路パターン／セラミクス／金属パターンの積層構造
からなる基板で構成されていて、前記パワー半導体モジ
ュール底面の金属板が、リードフレームから構成され、
該リードフレーム底面と、前記金属製回路パターン／セ
ラミクス／金属パターンの積層構造からなる基板底面が
同一面であることを特徴とするパワー半導体モジュー
ル。11. The circuit pattern according to claim 1, wherein the circuit pattern comprises a lead frame, a substrate having a laminated structure of metal circuit pattern / ceramics / metal pattern, or a laminated structure of metal circuit pattern / ceramics / metal pattern. It is constituted by a substrate, the metal plate on the bottom surface of the power semiconductor module is constituted by a lead frame,
A power semiconductor module, wherein a bottom surface of the lead frame and a bottom surface of a substrate having a laminated structure of the metal circuit pattern / ceramics / metal pattern are the same surface. 【請求項１２】請求項１１において、前記セラミクス
が、窒化アルミニウムであることを特徴とするパワー半
導体モジュール。12. The power semiconductor module according to claim 11, wherein said ceramics is aluminum nitride. 【請求項１３】請求項２において、前記回路パターン
中、パワー半導体素子が接着されるパターン裏面に、絶
縁層がコーティングされていることを特徴とするパワー
半導体モジュール。13. The power semiconductor module according to claim 2, wherein an insulating layer is coated on a back surface of the circuit pattern to which a power semiconductor element is adhered. 【請求項１４】請求項１３において、前記絶縁層が、エ
ポキシ樹脂を主成分とする樹脂層、若しくは低融点ガラ
スの何れかであることを特徴とするパワー半導体モジュ
ール。14. The power semiconductor module according to claim 13, wherein said insulating layer is one of a resin layer mainly composed of epoxy resin and low melting point glass. 【請求項１５】請求項２において、前記主端子、及び、
制御端子が、熱可塑性樹脂で封止された端子部品である
ことを特徴とするパワー半導体モジュール。15. The main terminal according to claim 2, wherein:
A power semiconductor module, wherein the control terminal is a terminal component sealed with a thermoplastic resin. 【請求項１６】請求項１５において、前記主端子は、ネ
ジ締め手段を有する構造、制御端子は、スルーホールは
んだ接着手段を有することを特徴とするパワー半導体モ
ジュール。16. The power semiconductor module according to claim 15, wherein said main terminal has a structure having screw fastening means, and said control terminal has through-hole solder bonding means. 【請求項１７】パワー半導体チップと、該パワー半導体
チップが接着される回路パターンと、該パワー半導体チ
ップの電流を外部へ通電する主端子と、該パワー半導体
チップを制御する制御端子、とを備えていて、熱硬化性
樹脂によるトランスファモールドパッケージで封止され
たパワー半導体モジュールにおいて、 前記回路パターン底面と、該回路パターンを取り囲む位
置に配置された金属板底面とを同一面とし、前記回路パ
ターンと金属板とを樹脂で絶縁し、前記金属板を前記パ
ッケージ底面へ露出させて水冷装置へ取り付けることに
より、前記パワー半導体モジュール底面で冷却水をシー
ルしてパワー半導体を冷却することを特徴とするパワー
半導体モジュール。17. A power semiconductor chip comprising: a power semiconductor chip; a circuit pattern to which the power semiconductor chip is adhered; a main terminal for supplying a current of the power semiconductor chip to the outside; and a control terminal for controlling the power semiconductor chip. In a power semiconductor module sealed with a transfer mold package of a thermosetting resin, the circuit pattern bottom surface and a metal plate bottom surface disposed at a position surrounding the circuit pattern are flush with each other. Power is characterized by insulating a metal plate with a resin, exposing the metal plate to the package bottom surface, and attaching the metal plate to a water cooling device to seal cooling water at the power semiconductor module bottom surface and cool the power semiconductor. Semiconductor module. 【請求項１８】請求項１７において、前記回路パター
ン、及び、前記パッケージ底面の金属板はリードフレー
ムであって、前記パッケージ底面の金属板はリードフレ
ームのタイバーであることを特徴とするパワー半導体モ
ジュール。18. The power semiconductor module according to claim 17, wherein the circuit pattern and the metal plate on the bottom of the package are a lead frame, and the metal plate on the bottom of the package is a tie bar of the lead frame. . 【請求項１９】請求項１記載のパワー半導体モジュール
でスイッチング素子を構成した３相インバータ装置。19. A three-phase inverter device comprising a switching element using the power semiconductor module according to claim 1.
JP2001118999A 2001-04-18 2001-04-18 Power semiconductor module Expired - Fee Related JP4465906B2 (en)

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