JP2002313790A - Method for repairing dielectric layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for repairing a dielectric layer by which the surface of the dielectric layer is flattened, metallic layers are surely insulated with each other, and no short-circuiting occurs, by filling voids produced on the surface of the dielectric layer in a semiconductor substrate to repair them. SOLUTION: This method includes a step for polishing the surface of a first dielectric layer 13 in a semiconductor substrate 10 provided with at least the first dielectric layer 13 and a first dielectric layer 15, a step for forming a second dielectric layer 21 on the first dielectric layer 15 for cover at least one void produced in the first dielectric layer 15 in the said step, a step for forming an SOG layer 23 on the second dielectric layer 21, a step for flattening the SOG layer 23 by etching back, and a step for forming a third dielectric layer 24 on the SOG layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for repairing a dielectric layer.

[0002]

2. Description of the Related Art While the degree of integration of integrated circuits has been increasing, it has not been possible to obtain a sufficient wiring space from the wafer surface. In other words, as MOS transistors become smaller and smaller, metal wiring becomes more difficult. Therefore, in order to solve such a problem, the design of providing two or more metal layers is the mainstream of integrated circuit design. In particular, in the case of a product having a complicated function, for example, a microprocessor, four or more metal layers are required to connect each part inside the microprocessor.

Usually, after a main part of a MOS register is formed, a multi-metal wiring process is started. In other words, the process is an independently performed semiconductor manufacturing process. When forming multiple metal layers, it is necessary to place a dielectric material, that is, a so-called inner metal dielectric layer, between adjacent metal layers to provide insulation, in order to prevent metal wirings in different metal layers from contacting each other and causing a short circuit. is there. However, heretofore, there have been the following problems in the planarization processing for the dielectric layer.

FIGS. 1A to 1C are views showing that voids are formed on the surface of a dielectric layer in a planarization process by a CMP method.

Referring to FIGS. 1A to 1C, it is assumed that particles 11 are present in an inner metal dielectric layer 15 of a semiconductor substrate 10 before a planarization process (FIG. 1A). Then, when a planarization process is performed by a CMP (Chemical Mechanical Polishing) method, the particles 11 fall off by polishing, and voids 12 are generated on the surface of the dielectric layer 15 (FIG. 1B). If the void 12 is large, the first metal layer 13 below the dielectric layer 15 will be exposed. For this reason,
The second metal layer 14 formed later may be short-circuited to the metal layer 13 (FIG. 1c).

In order to solve the above-mentioned short-circuit problem, a method of forming a second metal layer 14 after coating a thin oxide layer on the dielectric layer 15 is used.

[0007]

However, in the above-described method, a short circuit between different metal layers can be prevented, but the following problems occur.

(1) In the subsequent process of forming a fine pattern in a dielectric layer or a metal layer, there is a step on the surface of the thin oxide layer (the flatness is reduced), so that an alignment error occurs and the accuracy is reduced. .

(2) In addition, alignment errors have an adverse effect on the deposition of the overlying metal layer and the flatness in subsequent processes.

(3) When performing defect detection (scan) after etching the second metal layer, the first metal layer is still seen. This means that the step problem still exists.

In order to solve the above problems, an object of the present invention is to fill a void formed on a surface of a semiconductor substrate having at least a conductive layer and a dielectric layer and repair the dielectric layer. Accordingly, it is an object of the present invention to provide a method of repairing a dielectric layer in which the surface of the dielectric layer becomes flat, the metal layers are reliably insulated from each other, and no short circuit occurs.

[0012]

According to the present invention, there is provided a method of repairing a dielectric layer, comprising the steps of: providing a semiconductor substrate having at least a first conductive layer and a first dielectric layer on a surface of the first dielectric layer; Polishing; and forming a second dielectric layer over the first dielectric layer to cover at least one void created in the first dielectric layer in the step. SOG (spin on glass) on the second dielectric layer
Forming a layer and extra SO with etch back
Removing the G layer (ie, planarizing the SOG layer) and forming a third dielectric layer on the SOG layer.

The method of repairing a dielectric layer according to the present invention includes the steps of: polishing a surface of the first dielectric layer on a semiconductor substrate having at least a first conductive layer and a first dielectric layer; Forming a second dielectric layer over the first dielectric layer to cover at least one void created in the first dielectric layer; and forming a thin SO layer over the second dielectric layer.
It may be configured to include a step of forming a G layer and a step of forming a third dielectric layer on the thin SOG layer.

When the method of repairing a dielectric layer according to the present invention is carried out, the voids on the surface of the dielectric layer are filled to repair the dielectric layer, and at the same time, the flatness of the dielectric layer is improved and the subsequent fine pattern forming process in each layer is smooth. Done in Therefore, the metal layers are reliably insulated by the dielectric layer, and the occurrence of short circuit is eliminated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of an embodiment of the present invention which achieves the above-mentioned objects and solves the problems of the related art will be described in detail with reference to the accompanying drawings.

FIGS. 2A to 2F show a first embodiment of the method for repairing a dielectric layer according to the present invention.

As shown in FIG. 2A, in a semiconductor substrate 15 having at least a first conductive layer 13 (for example, a metal layer) and a first dielectric layer 15 (for example, a SiO ₂ layer), the surface of the first dielectric layer 13 is formed. When polishing is performed, since at least one particle is present in the dielectric layer 15, the particles fall off due to polishing, and voids 12 are generated on the surface of the dielectric layer 15.

Then, as shown in FIG.
A second dielectric layer 21 is formed on the first dielectric layer 15 to cover. In the first embodiment, the second dielectric layer 21
Is a thin oxide layer.
It is formed by depositing O ₂ .

Next, as shown in FIG. 2C, an SOG (spin on glass) layer 22 is formed on the second dielectric layer 21. In this embodiment, the SOG layer is further solidified.

Next, as shown in FIG. 2D, the excess SOG layer is removed by etching back, that is, the SOG layer 23 is flattened. Here, as the etch back, for example, a plasma dry etching method is used.

Next, as shown in FIG.
A third dielectric layer 24 is formed on the first dielectric layer. In this embodiment, the third dielectric layer 24 is a thin oxide layer, for example, PECV
It is formed by depositing SiO ₂ by the method D.

Next, as shown in FIG. 2F, a second conductive layer 14 is formed on the third dielectric layer 24. In this embodiment, the second conductive layer is made of a metal, and is formed by, for example, a sputtering method.

FIGS. 3A to 3E show a second embodiment of the method for repairing a dielectric layer according to the present invention.

As shown in FIG. 3A, the surface of the first dielectric layer 13 is polished on a semiconductor substrate 15 having at least a first conductive layer 13 (eg, a metal layer) and a first dielectric layer 15 (eg, an SiO ₂ layer). At this time, since at least one particle is present in the dielectric layer 15, the particles are removed by polishing and the dielectric layer 15 is removed.
Voids 12 are formed on the surface of the substrate.

Then, as shown in FIG.
A second dielectric layer 21 is formed on the first dielectric layer 15 to cover. In the first embodiment, the second dielectric layer 21
Is a thin oxide layer.
O _{2 is} deposited.

Next, a thin SOG layer 31 is formed on the second dielectric layer 21 to completely fill the void 12 (FIG. 3c).

Next, as shown in FIG.
A third dielectric layer 24 is formed on layer 31. In this embodiment, the third dielectric layer 24 is a thin oxide layer, for example, P
It is formed by depositing SiO ₂ by the ECVD method.

Next, as shown in FIG. 3E, a second conductive layer 14 is formed on the third dielectric layer 24. In this embodiment, the second conductive layer is made of a metal, and is formed by, for example, a sputtering method.

In the above-described embodiment of the present invention, the definition and deposition of each layer, the etching, and the formation and solidification of the SOG layer are performed by conventional methods, respectively. It is used to repair the dielectric layer. That is, in the case where voids are generated due to falling off of particles in the dielectric layer when polishing the surface of the dielectric layer in a semiconductor substrate having at least a conductive layer and a dielectric layer, the dielectric layer is repaired using the method of the present invention. It can be planarized.

Although the present invention has been described in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications within the spirit and scope of the present invention. Therefore, the scope of the present invention is in accordance with the appended claims.

[0031]

As described above, according to the present invention, it is possible to improve the consistency of the intervals between the metal layers and prevent the occurrence of a short circuit between the metal layers. Further, the present invention is suitable for a manufacturing process of a multi-layer integrated circuit which requires a flattening process for each layer. Specifically, the present invention has the following effects.

(1) The insulation between the metal layers can be surely achieved, and the occurrence of short-circuit can be prevented.

(2) There is no step on the surface of the layer since the void is filled with the SOG layer and flattening is performed. Therefore, in the subsequent fine pattern forming process on the dielectric layer or the metal layer, the alignment accuracy is improved.

(3) Since the flatness is high and the accuracy of alignment is improved, the subsequent deposition process of the metal layer and the dielectric layer is performed smoothly.

(4) When a defect is detected (scanned) after etching the second metal layer, no image of the first metal layer is seen. This indicates that the problem of the conventional step has been solved.

[Brief description of the drawings]

FIG. 1A is a diagram showing that voids are formed on the surface of a dielectric layer in the case of a planarization process by a CMP method.

FIG. 1B is a diagram showing that voids are formed on the surface of a dielectric layer in the case of a planarization process by a CMP method.

FIG. 1c is a view showing that voids are formed on the surface of a dielectric layer in the case of a planarization process by a CMP method.

FIG. 2a illustrates a method (partial stages) of repairing a dielectric layer according to a first embodiment of the present invention.

FIG. 2b illustrates a method (partial steps) of repairing a dielectric layer according to a first embodiment of the present invention.

FIG. 2c illustrates a method (partial stages) of repairing a dielectric layer according to a first embodiment of the present invention.

FIG. 2d illustrates a step subsequent to the step according to the method of repairing the dielectric layer illustrated in FIGS. 2a to 2c.

FIG. 2e illustrates a step subsequent to the step according to the method of repairing the dielectric layer illustrated in FIGS. 2a to 2c.

FIG. 2f illustrates a step subsequent to the step of repairing the dielectric layer illustrated in FIGS. 2a to 2c.

FIG. 3a illustrates a method (partial stages) of repairing a dielectric layer according to a second embodiment of the present invention.

FIG. 3b illustrates a method (partial steps) of repairing a dielectric layer according to a second embodiment of the present invention.

FIG. 3c illustrates a method (partial steps) of repairing a dielectric layer according to a second embodiment of the present invention.

FIG. 3d illustrates a step subsequent to the step according to the method of repairing the dielectric layer illustrated in FIGS. 3a to 3c.

FIG. 3e illustrates a step subsequent to the step according to the method of repairing the dielectric layer shown in FIGS. 3a to 3c.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 11 particle 12 void 13 first metal layer 14 second metal layer 15 first dielectric layer 21 second dielectric layer 22 SOG layer 23 SOG layer after etch back 24 third dielectric layer 31 thin SOG layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Chu-Chun Fu Taiwan, Sinchu, Gwang-Hua Second Street, No. 143, 7F (72) Inventor Xiao-Cho Wu Taiwan, Taoyuan County, Chun-Li, She Yuan Road, No. 6-8, 14F F term (reference) 5F033 QQ09 QQ12 QQ31 QQ48 RR04 RR09 SS15 SS22 XX01 5F058 BD02 BD04 BD07 BE10 BF07 BH12 BJ02

Claims (10)

[Claims] (A) polishing a surface of a first dielectric layer on a semiconductor substrate having at least a first conductive layer and a first dielectric layer; and (B) polishing the surface of the first dielectric layer in the step (A). Forming a second dielectric layer over the first dielectric layer to cover at least one void created in the first dielectric layer; and (C) overlying the second dielectric layer. Forming a SOG layer; (D) planarizing the SOG layer with etchback; and (E) forming a third dielectric layer on the SOG layer. How to repair. 2. Immediately after said step (C), furthermore said SO
2. A step of solidifying the G layer.
3. The method for repairing a dielectric layer according to claim 1. 3. Immediately after the step (E), the third step
2. The method according to claim 1, wherein the step of forming a second conductive layer on the dielectric layer is performed. 4. The method according to claim 1, wherein the first conductive layer and the second conductive layer are each made of a metal. 5. The method according to claim 1, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are each made of SiO ₂ . 6. A step of: (a) polishing a surface of a first dielectric layer in a semiconductor substrate having at least a first conductive layer and a first dielectric layer; and (b) the step of polishing the surface of the first dielectric layer in the step (a). Forming a second dielectric layer over the first dielectric layer to cover at least one void created in the one dielectric layer; and (c) overlying the second dielectric layer. A method for repairing a dielectric layer, comprising: forming a thin SOG layer; and (d) forming a third dielectric layer on the thin SOG layer. 7. The method of claim 6, further comprising the step of solidifying the thin SOG layer immediately after the step (c). 8. Immediately after said step (d), the third
7. The method of claim 6, further comprising the step of forming a second conductive layer on the dielectric layer. 9. The method according to claim 6, wherein the first conductive layer and the second conductive layer are each made of a metal. 10. The method according to claim 6, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are each made of SiO ₂ .