JP3405006B2 - Insulating film flattening method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of flattening an insulating film used in, for example, a semiconductor device, and more particularly to a technique of simultaneously achieving local planarization and global planarization through physical deformation of a coating type insulating film.

[0002]

2. Description of the Related Art In recent highly integrated semiconductor devices such as VLSI and ULSI, three-dimensional circuit patterns are being promoted in order to suppress the increase in chip area. However, as the three-dimensionalization progresses, the surface steps of the substrate increase, and various problems such as halation in photolithography and the effect of standing waves, disconnection of wiring at the step, and generation of stringer residues in dry etching are likely to occur. . Therefore, in the process of manufacturing a semiconductor device, as work for eliminating or reducing this surface step,
The importance of flattening is increasing.

Above all, planarization of an interlayer insulating film filling a complicated inter-wiring space is an important technique, and several methods have been proposed conventionally. Typical methods include an etch back method and a chemical mechanical polishing (CMP) method.

In the etch back method, the surface of a substrate having a step is once flattened by using a flattening film such as an SOG (spin-on-glass) film, and the flattening film and the film immediately below it (mostly In the case of, the anisotropic dry etching is performed under the condition that the etching selection ratio to the interlayer insulating film) is 1, that is, the condition that the etching rates of both films are equal to reduce the total film thickness of the insulating film. Is.

On the other hand, the CMP method is a method in which a substrate mounted on a substrate holder is pressed against the surface of a surface plate on which a polishing pad is adhered, and a slurry containing polishing fine particles is supplied onto the polishing pad while the surface plate and the substrate holder are being supplied. This is a method of rotating both of them and polishing the surface of the substrate.

[0006]

By the way, planarization to be achieved in a semiconductor process includes local planarization and global planarization. The local flattening is a local flattening such as filling a fine inter-wiring space in a region where wiring patterns are densely formed. On the other hand, the global flattening is flattening for eliminating an absolute difference in elevation that occurs between a wide space between wirings or a relatively wide area such as a memory cell portion of a DRAM and a peripheral circuit portion. Both of these planarizations
Originally, it is desirable to achieve them at the same time, but it is extremely difficult to achieve them simultaneously by the conventionally known etchback method or CMP method.

First, regarding the problems of the etch back method,
This will be described with reference to FIGS. 16 and 17. FIG.
On the insulating substrate 11 made of an insulating material such as SiOx.
l-system wiring patterns 12 are formed at various intervals,
This Al-based wiring pattern 12 is made of SiOx by the CVD method.
Interlayer insulating film 1 formed by conformally depositing
3 and SOG film 14b applied by spin coating
(The subscript b indicates that the film has been subjected to baking.) And the state of being sequentially coated.

Here, the SOG film 14b is formed for the purpose of flattening the surface of the base body, but as shown in FIG. 16, it has succeeded in flattening in a region where the space between wirings is narrow. , Has not been successful in a large area.
This is based on the IEICE Transactions Vol. J78-C-
II No. 5, p200 to 206, the "constant law of constant deposition" in which the deposition of the SOG film applied per fixed horizontal projection length in the wafer surface is constant regardless of the density of the wiring. Because it is controlled by.
Therefore, even if the SOG film 14b and the CVD interlayer insulating film 13 are etched back at a constant speed from this state, as shown in FIG.
As shown in FIG. 7, the global step remains unresolved in a wide area between the wirings. That is, the SOG film 14be after etching back (the subscript e represents a film that has been etched back) is not flat.

In order to supplement the limit of the flattening ability of the SOG film, a dummy pattern is formed in a wide area between wirings to reduce the apparent space between wirings. A method of forming this dummy pattern by patterning the CVD interlayer insulating film will be described with reference to FIGS. Note that the reference numerals in these figures are partially common to those in FIG.

First, as shown in FIG. 18, the steps up to the formation of the CVD interlayer insulating film 13 are performed in the same manner as described above, and a resist mask 15 (PR) is formed in a region having a wide space between wirings through ordinary photolithography. To do. Next, the CVD interlayer insulating film 13 is etched through the resist mask 15 to form a dummy wiring pattern 13d. Next, as shown in FIG. 20, CVD is performed again on the entire surface of the substrate.
A CVD interlayer insulating film 16 is formed by conformally depositing a SiOx film by the method, and an SOG film 17b is formed thereon by a spin coating method. According to this method, even if etching back is performed, it is possible to prevent the occurrence of a global step in a region having a wide inter-wiring space, as shown in FIG.

However, in the above-described method, a lithography process for forming the dummy wiring pattern is newly generated, and the throughput and the yield are reduced due to the increase in the number of processes.
Or cost increase is inevitable. If the dummy wiring pattern is formed of an Al-based wiring film that is common to the Al-based wiring pattern 12, the number of times of photolithography will not increase, but it is necessary to generate the dummy pattern on the photomask, which makes the photomask laborious. Increase.

Further, no matter which material film is used to form the dummy wiring pattern, this method is effective for a DRAM or a logic LSI whose wiring layout has been determined from the beginning, but the wiring layout is required according to the customer's request. Not suitable for custom logic LSIs that determine

While the CMP method is a promising flattening method, complete global flattening achieved by polishing only the highest elevation is still difficult. This is because the hardness of the polishing pad is set to a value that can follow the warp of the wafer to some extent, so that the polishing pad also enters the low step portion due to the pressing pressure, and the low step portion is also scraped to some extent.

Further, the CMP method is not suitable for a system in which different kinds of insulating films coexist as shown in FIG. That is, S
Since the hardness of the OG film 14b and that of the CVD interlayer insulating film 13 are largely different, when the CVD interlayer insulating film 13 is exposed, the polishing rate of the SOG film 14b having low hardness is increased, and as a result, the global step difference is eliminated. I can't. Further, it is considered that CMP involves a chemical etching process depending on the composition of the slurry, and in a system in which different kinds of insulating films coexist, different polishing rates are likely to occur simultaneously. This also hinders the elimination of the global step. Therefore, global planarization by the CMP method is premised on that the CVD interlayer insulating film is used alone as an interlayer insulating film. However, there is a limit to the filling with the CVD interlayer insulating film,
For example, it is extremely difficult to embed a high step region such as a DRAM capacitor with this film alone. Therefore, there is a limit to the application of the CMP method.

Therefore, in view of the above-mentioned conventional problems, it is an object of the present invention to provide an insulating film flattening method capable of simultaneously achieving local flattening and global flattening at low cost. .

[0016]

DISCLOSURE OF THE INVENTION The present invention is proposed in order to achieve the above-mentioned object, does not cause a global step even in a wide area between wirings, and has different hardness and chemical properties. In order to prevent the difference in the flattening characteristics due to (a), S is first formed on the surface of the substrate having a step.
Forming a coating type insulating film typified by an OG film to a certain thickness, and (b) planarizing the coating type insulating film by a pure physical mechanism not involving a chemical mechanism,
The two points are.

Here, the certain thickness of the coating type insulating film is a thickness at which the lowest altitude portion of the coating type insulating film has at least the same altitude as the highest altitude portion of the substrate. This thickness is
Since the thickness is larger than the thickness of the planarization film formed by the conventional etch-back method, the conditions for local planarization are satisfied at this point.

Therefore, the process thereafter is to achieve global flattening. As the operation for giving the physical deformation, cutting by a cutting means, wiping by a wiping means, or both of them can be combined. Cutting is performed after baking the coating type insulating film, and wiping is performed before baking. Therefore, when cutting and wiping are combined, the process flow is wiping → baking →
The order is cutting.

The cutting or wiping may be completed once, but if it is divided into a plurality of times and the coating type insulating film is partially removed in the film thickness direction each time, the controllability can be improved. It is possible to improve and reduce damage.

In the case of cutting, the coating type insulating film can be formed on the vapor-phase growth insulating film having a hardness higher than that of the coating type insulating film, and the cutting can substantially cut only the coating type insulating film. It can be performed under various conditions. By doing so, the cutting stops at the surface of the vapor-phase growth insulating film, so that the global step difference that has occurred after the formation of the coating type insulating film is virtually eliminated. However, if the vapor growth insulating film is then switched to a condition in which it can be cut, a part of the vapor growth insulating film can also be cut, and the residual film thickness can be controlled as necessary.

Further, in the case of applying, as the wiping means, one in which the base body sliding contact surface is made of an elastic member is used, and the intrusion of the elastic member to the altitude portion lower than the highest altitude portion of the base body is predetermined. Keep within the range. Here, the predetermined range refers to a range that is allowed as a deterioration amount of flatness.
In this way, the range to be removed by wiping is determined almost according to the highest altitude portion of the substrate, so that good global flattening can be achieved.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

First Embodiment Here, a process of flattening an SOG film formed on a CVD interlayer insulating film by cutting will be described with reference to FIGS. 1 to 5.

First, as shown in FIG. 1, an Al type wiring pattern 2 is formed on an insulating substrate 1 made of an insulating material such as SiOx, and a CVD interlayer insulating film 3 and an SOG film 4 are formed so as to cover the Al type wiring pattern 2. Were sequentially formed. The Al-based wiring pattern 2 is formed by patterning a multilayer film in which a barrier metal made of a Ti / TiN laminated film, an Al-1% Si film, and a SiON antireflection film are laminated in this order. The film thickness and the film thickness can be appropriately selected from conventionally known configurations and film thicknesses. For example, the Al-based wiring pattern 2 has a line width of 0.4 μm and a height of 0.8 μm,
The space between wirings was set to a minimum of 0.25 μm and a maximum of 2 μm.

The CVD interlayer insulating film 3 is formed of O ₂ -TEOS.
(Tetraethoxysilane) Plasma C with mixed gas system
It is formed substantially conformally by VD to a thickness of, for example, about 0.5 μm. However, this film forming method may also be a conventionally known method such as atmospheric pressure CVD using an O ₃ -TEOS mixed gas system or LPCVD using a SiH ₄ -H ₂ mixed gas system. Above SO
The G film 4 is a conventionally known inorganic SOG material or organic SO.
The G material is applied by spin coating, and the film thickness is, for example, 1.0 μm at maximum and 0.2 μm at minimum.
m. Although the SOG film 4 at this stage achieves local planarization, it does not achieve global planarization because it is governed by the above-mentioned “law of constant deposition”. However, here, the altitude h of the lowest altitude part of the SOG film 4
Since 1 is higher than the altitude h2 of the highest altitude portion of the CVD interlayer insulating film 3 (h1> h2), global flattening can be achieved without exposing the CVD interlayer insulating film 3 in the cutting step described later. ing. The above altitude h
1 and h2 may be the same (h1 = h2), and in this case, global flattening is achieved when the highest elevation of the CVD interlayer insulating film 3 is just exposed.

Next, as shown in FIG.
The film 4 was baked at, for example, 380 ° C. for 10 minutes to form an SOG film 4b.

Next, using the cutting blade 100, the above S
The OG film 4b was cut. This cutting is done in two steps,
In the first cutting, about half of the minimum film thickness portion is cut as shown in FIG. 3, and in the second cutting, the remaining half is cut as shown in FIG. 4, so that the SOG film 4bc (subscript bc) is cut.
Indicates that the film was baked and flattened by cutting. ) Got. Note that, of course, the above cutting may be performed once.

Although the constituent material of the cutting blade 100 is SUS steel, other alloys or ceramics may be used. In addition, the hardness and pressing pressure of the cutting blade 100 are set so that the cutting blade 100 is substantially the same as the SOG film 4.
It was selected such that only b was cut and the underlying CVD interlayer insulating film 3 was not cut. With this selection, the CVD
By moving the cutting blade 100 so as to slide on the highest elevation surface of the interlayer insulating film 3, global flattening of the substrate surface according to the elevation h2 was realized.

If it is desired to further reduce the residual film thickness, the conditions for cutting the CVD interlayer insulating film 3 are set by changing the hardness of the cutting blade 100 and the pressing pressure, and as shown in FIG. The CVD interlayer insulating film 3 may be cut and removed together with the SOG film 4bc by a desired film thickness.

According to the present invention, the finally obtained insulating film partially has a two-layer structure of a CVD interlayer insulating film and an SOG film. The SOG film has a lower dielectric constant than the CVD interlayer insulating film. Therefore, assuming the application to a miniaturized semiconductor device in the future, such a two-layer structure has a CV as an insulating film.
Compared with the case where the D interlayer insulating film is used alone, there is an advantage that the parasitic capacitance between adjacent wirings or between upper and lower wirings can be reduced without increasing the thickness of the insulating film.

By the way, the cutting in the present invention is performed by scanning the cutting blade 100 on the substrate (here, the wafer W), but some methods can be applied to the scanning at this time. A typical scanning method is shown in FIG. (A) is a translational scanning method in which a cutting blade 100 having a length capable of covering the diameter of the wafer W is used and the cutting blade 100 is translated in the direction of arrow A on the fixed wafer W, and (b) is a wafer. A cutting blade 101 having a length capable of covering the radius of W is used.
01 is fixed, the wafer W is rotated in the direction of the arrow B in the rotation scanning method, (c) shows a cutting blade 102 shorter than the radius of the wafer W in the direction of the arrow C.
This is a spiral scan method in which a spiral movement locus is given by moving the wafer W in the direction of arrow B and rotating the wafer W in the direction of arrow B.

However, these are examples of possible methods and are not limited to the above methods as long as the relative positions of the cutting blade 100 and the wafer W can be changed. For example, in the above translational scanning method, the traveling direction of the cutting blade 100 does not have to be perpendicular to the longitudinal direction of the blade. Further, in the above rotary scan method, the wafer W may be fixed and the cutting blade 101 may be rotated. Further, in the spiral scan method, the wafer W may be fixed and the cutting blade 102 may be moved in a spiral shape.

The shape of the cutting blade is not limited to the linear shape as described above, but may be V-shaped, for example. When using a V-shaped blade, cutting waste can be efficiently removed from the cutting area by cutting with the apex of the V-shape directed in the advancing direction of the blade. Since they can be collected inside, it is possible to use a dust collector suitable for each case together to realize a clean process. Second Embodiment Here, a process of flattening the surface layer portion of the SOG film formed on the CVD interlayer insulating film by wiping is shown in FIG.
This will be described with reference to FIGS. 7 to 11 and FIG.

First, a substrate coated with the SOG film 4 as shown in FIG.
0 was used to wipe off the SOG film 4. This wiping is divided into two steps, and in the first wiping, about half of the minimum film thickness portion is wiped off as shown in FIG. 7, and the flattened SOG film 4w ( The subscript w represents that the film was flattened by wiping.).
In the second wiping, the other half was wiped off as shown in FIG. The wiping may be performed once, as a matter of course.

Here, rubber was used as the constituent material of the substrate sliding contact surface of the wiping blade 200, but other polymeric materials such as urethane may be used. Further, the deformation degree and the sliding contact pressure of the wiping blade 200 are, as shown in an enlarged scale in FIG. 11, the penetration depth d of the wiping blade 200 downward from the highest elevation surface of the CVD interlayer insulating film 3. Is 100
It was set to be within nm. After making such settings, the wiping blade 200 is moved so as to slide on the highest elevation surface of the CVD interlayer insulating film 3 to obtain an elevation h.
It was possible to achieve global flattening in line with item 2. The scan of the wiping blade 200 is
The cutting blade 100 can be used in the same manner as the method described with reference to FIG.

After that, baking was performed. As a result,
As shown in FIG. 4, the concave portion of the CVD interlayer insulating film 3 is S
The OG film 4wb (subscript wb represents a film that has been flattened by wiping and then baked) is in a state of being flatly embedded. The insulating film thus flattened can reduce the inter-wiring capacitance.

Third Embodiment Here, a process of reducing the film thickness of the insulating film by flattening the surface layer portion of the SOG film formed on the CVD interlayer insulating film by wiping and then cutting , FIG. 8, FIG. 12, FIG. 4 and FIG.

First, as shown in FIG. 8 described above, a substrate on which the SOG film 4w has been wiped off for the first time is prepared. The SOG film 4w at this stage is formed by the spin-coated SO film.
The in-plane uniformity of the film thickness is improved as compared with the G film 4. Subsequently, this substrate was baked as shown in FIG. 12 to obtain an SOG film 4wb. Further, as shown in FIG. 4, the concave portion of the CVD interlayer insulating film 3 is subjected to the above-described cutting, and the SOG film 4wbc (the subscript wbc is a film which has been sequentially subjected to flattening by wiping, baking, and cutting). Represents the state of being embedded evenly. In addition,
It is optional to continue this cutting under different conditions and also to cut a part of the CVD interlayer insulating film 3 as shown in FIG.

Fourth Embodiment Here, a process in which an insulating film for filling a space between wirings is composed of an SOG film alone and the surface layer portion thereof is flattened by wiping will be described with reference to FIGS. 13 to 15. To do.

First, as shown in FIG. 13, the SOG film 5 having a sufficient thickness is formed on the surface of the substrate on which the Al-based wiring pattern 2 is formed with various inter-wiring spaces by spin coating. . Here, the film thickness of the SOG film 5 is, for example, 1.0 μm at maximum and 0.2 μm at minimum, and the altitude h3 at the lowest altitude thereof is higher than the altitude h4 at the highest altitude of the Al-based wiring pattern 2 ( h3> h
4). At this stage, a global step has occurred.

Next, as shown in FIG.
The surface layer of the G film 5 was wiped off with a wiping blade 200 to obtain a globally flattened SOG film 5w.
Subsequently, as shown in FIG. 15, baking was performed to obtain a dense and excellent SOG film 5wb having excellent moisture resistance. Since the insulating film thus obtained is composed of the SOG film alone,
The capacity can be further reduced as compared with the case described in the other embodiments. If the above-mentioned altitudes h3 and h4 are equal (h3 = h4), the Al-based wiring pattern 2 will be exposed at the time when global flattening is achieved by wiping. It is necessary to re-cover the entire surface of the substrate with the SOG film or the CVD interlayer insulating film.

[0042]

As is apparent from the above description, when the present invention is applied, the material of the planarizing film and the underlying structure such as CMP can be obtained without complicated steps such as dummy pattern formation. The local planarization and the global planarization of the insulating film can be achieved at the same time without any restriction. As a result, it becomes possible to improve the processing accuracy and reliability of the circuit pattern formed on the upper layer side of the insulating film. The present invention greatly contributes to high integration and high reliability of, for example, a semiconductor device through highly accurate flattening of an insulating film.

[Brief description of drawings]

FIG. 1 shows a CVD interlayer insulating film and a sufficiently thick SO on an Al-based wiring pattern according to the first embodiment of the present invention.
It is a typical sectional view showing a state where a G film was formed one by one.

FIG. 2 is a schematic cross-sectional view showing a state where the SOG film of FIG. 1 is baked.

FIG. 3 is a schematic cross-sectional view showing a state in which about half of the film thickness of the SOG film of FIG. 2 is removed by the first cutting.

FIG. 4 is a schematic cross-sectional view showing a state in which the remaining portion of the SOG film of FIG. 3 is removed by the second cutting.

5 is a schematic cross-sectional view showing a state in which a part of the CVD interlayer insulating film of FIG. 4 is further cut.

6A and 6B are schematic plan views showing a scanning system of a cutting blade, wherein FIG. 6A is a translational scan, FIG. 6B is a rotational scan, and FIG. 6C is a spiral scan.

FIG. 7 is a schematic cross-sectional view showing a state in which the surface layer portion of the SOG film before baking is wiped off in the second embodiment of the invention.

8 is a schematic cross-sectional view showing a state in which the SOG film of FIG. 7 is flattened.

9 is a schematic cross-sectional view showing a state where the SOG film of FIG. 8 is removed by wiping a second time.

10 is a schematic cross-sectional view showing a state in which the SOG film of FIG. 9 is flattened.

FIG. 11 is a schematic enlarged cross-sectional view showing a locally deformed state of the wiping blade during wiping.

FIG. 12 is a schematic cross-sectional view showing a state where the SOG film of FIG. 8 is being baked in the third embodiment of the invention.

FIG. 13 is a schematic cross-sectional view showing a state where an inter-wiring space of an Al-based wiring film is filled with only an SOG film in the fourth embodiment of the present invention.

14 is a schematic cross-sectional view showing a state in which the surface layer portion of the SOG film of FIG. 13 is wiped off.

15 is a schematic cross-sectional view showing a state where the SOG film of FIG. 14 is being baked.

FIG. 16 is a schematic cross-sectional view showing a state in which a CVD interlayer insulating film and a thin SOG film are sequentially formed on an Al-based wiring pattern in a conventional insulating film flattening method.

FIG. 17 is a schematic cross-sectional view showing a state where the SOG film and the CVD interlayer insulating film of FIG. 16 are etched back.

FIG. 18 is a schematic cross-sectional view showing a state in which a resist mask for forming a dummy wiring pattern is formed in a region having a large inter-wiring space of an Al-based wiring pattern in another example of the conventional insulating film flattening method. is there.

19 is a schematic cross-sectional view showing a state where a dummy wiring pattern is formed by etching the CVD interlayer insulating film through the resist mask of FIG.

20 shows a CVD interlayer insulating film and S on the entire surface of the substrate of FIG.
It is a typical sectional view showing the state where an OG film was formed.

21 is a schematic cross-sectional view showing a state where the SOG film and the CVD interlayer insulating film of FIG. 20 are etched back.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Al-based wiring pattern 3 CVD interlayer insulating film 4,5 SOG film 4b (after baking) SOG films 4w and 5w (after wiping) SOG film 4bc (after baking and after cutting) SOG film 4wb, 5wb (after wiping, baking) SO
G film 4wbc (Wipe, baking, cutting in sequence) S
OG film 100, 101, 102 Cutting blade 200 Wiping blade W Wafer

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 H01L 21/31 H01L 21/316 H01L 21/3205

Claims (9)

(57) [Claims] 1. A step of applying a coating type insulating film on the surface of a machine body having a step to a thickness such that the lowest altitude part thereof is at least the same altitude as the highest altitude part of the substrate, and the coating type insulating film A method of flattening an insulating film, comprising: a step of baking the surface of the coating type insulating film having been baked, and a step of cutting the surface layer part of the coating type insulating film into a plurality of times by a cutting means to flatten the surface. 2. The coating type insulating film is formed on a vapor phase growth insulating film having a hardness higher than that of the coating type insulating film, and the cutting is performed under the condition that only the coating type insulating film can be cut. 1. The method for planarizing an insulating film according to 1. 3. The insulating film according to claim 1, wherein after the coating type insulating film is cut, a part of the vapor growth insulating film is cut by switching to a condition in which the vapor growth insulating film can also be cut. Flattening method. 4. The method of planarizing an insulating film according to claim 1, wherein the coating type insulating film is spin-on-glass. 5. A step of applying a coating type insulating film on the surface of a machine body having a step to a thickness such that the lowest elevation part thereof has at least the same elevation as the highest elevation part of the substrate, and the coating type insulation before baking. the surface portion of the film, wiping
A method of flattening the insulating film in a plurality of times by a means . 6. The base sliding contact surface of the wiping means is composed of an elastic member, and the wiping is performed while suppressing the invasion of the elastic member to an altitude portion lower than the highest altitude portion of the base member within a predetermined range. The method for planarizing an insulating film according to claim 5. 7. The method of planarizing an insulating film according to claim 5, wherein the coating type insulating film is spin-on-glass. 8. A step of applying a coating type insulating film on a surface of a machine body having a step to a thickness such that the lowest altitude part thereof is at least the same altitude as the highest altitude part of the substrate, and the surface layer of the coating type insulating film. Part with a wiping means
And flattening, and the coating mold wiped by the wiping means
Baking the insulating film and the surface layer of the coating type insulating film having been baked.
And a step of flattening by cutting with a cutting means . 9. The method of planarizing an insulating film according to claim 8, wherein the coating type insulating film is spin-on-glass.