JP2002312297A - Pci host bus bridge system initializing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the initialization of various kinds of PCI host bus bridge without rewriting BIOS. SOLUTION: An EEPROM reading function 310/410 read out the information related to the characteristic of PCI host bus bridges 31/41 inside the EEPROM 33/43 and the information related to a PCI slot and a PCI device engaged with the PCI host bus bridge 31/41 on the basis of a command from BIOS 11. The BIOS 11 is provided with an information reading function for reading (obtaining) the information by using the EEPROM reading functions 310/410 and an initializing function for initializing the PCI host bus bridges 31/41 (initialization of a PCI device and interrupt controllers 34/44 engaged with the PCI host bus bridges 31/41) on the basis of the information read by the information reading function.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a plurality of types of PCIs.
(Peripheral Component Int
A PCI host bus bridge system capable of implementing a host bus bridge ("PCI multi-host bus bridge system" in the case of having multiple PCI host bus bridges) The present invention relates to a PCI host bus bridge system initialization method for performing initialization processing relating to a PCI host bus bridge.

[0002]

2. Description of the Related Art A conventional PCI host bus bridge
The system initialization method includes information on the characteristics of the PCI host bus bridge system (for example, information on the number of PCI slots, information on PCI device numbers,
And information about the interrupt connection (for example, information indicating the interrupt input pin number of the interrupt controller to which the interrupt output pin of the PCI slot is input)
OS (Basic Input Output Sys)
tem. Firmware for initial settings etc.
Table (PCI host bus bridge table)
And initialization related to the PCI host bus bridge is realized according to the table.

FIG. 8 shows such a conventional technique.
FIG. 3 is a diagram illustrating a specific example of a PCI host bus bridge table held inside the BIOS.

An example shown in FIG. 8 is a PCI bus shown in FIG.
"PCI" corresponding to the host bus bridge system (PCI multi-host bus bridge system)
9 shows a PCI host bus bridge table having "information on characteristics of host bus bridge".

As can be seen from FIG. 8, in the conventional PCI host bus bridge system initialization method, all the PCI host bus bridges that can be mounted on the target PCI host bus bridge system are applied. Bridge (a PCI host bus bridge on a PCI built-in board, a PCI host bus bridge on a PCI expansion board, or a PC with a hot plug insert possibility)
Information about the respective features of the PCI host bus bridge on the I expansion board
It had to be kept in an internal PCI host bus bridge table.

Incidentally, such a “PCI host bus
The reason for the need for information on the characteristics of bridges is the BIO
In order for S to initialize a PCI board with a PCI host bus bridge and incorporate it into a PCI host bus bridge system, such a "PCI host bus bridge"
It is necessary to know "information on the characteristics of bus bridges".

[0007]

SUMMARY OF THE INVENTION The aforementioned conventional PCI
In the host bus bridge system initialization method, as described above, the PCI host bus bridge system (PCI multi-host bus bridge system)
For all the PCI host bus bridges that can be installed in the BIOS, information on the respective features is stored in the BIOS in advance.
I had to keep it as a table.

Here, such a conventional PCI host
Also in the bus bridge system initialization method, if a limited type of PCI host bus bridge is added or extended, the table is added to the PCI host bus bridge table group held inside the BIOS. It was able to cope by adding.

However, in the conventional PCI host bus bridge system initialization method, a "PCI multi-host bus bridge system capable of mounting various PCI host bus bridges" as in today is used.
In order to deal with
There is a problem that the rewriting of S involves a limitation in dealing with it.

In view of the above, an object of the present invention is to provide a PCI
A function that depends on the host bus bridge is separated from the inside of the BIOS, enabling initialization processing for various types of PCI host bus bridges without rewriting the BIOS.
It is an object of the present invention to provide a PCI host bus bridge system initialization method which can be incorporated into a CI host bus bridge system.

A patent publication relating to the prior art for the PCI host bus bridge system initialization method of the present invention is similar to the present invention in that hardware initialization by firmware is considered. Japanese Patent Application Laid-Open No. 2000-187533.

However, the above-mentioned Japanese Patent Application Laid-Open No. 2000-18753
The technique described in Japanese Patent Publication No. 3 (“Hardware initialization method by firmware”) has a configuration for realizing initialization of various types of PCI host bus bridges without rewriting the BIOS. However, the present invention is essentially different from the present invention.

[0013]

According to the present invention, a PCI host is provided.
The bus bridge system initialization method has several types of P
P capable of mounting CI host bus bridge
PC in CI host bus bridge system
P required to initialize I host bus bridge
The P on which the PCI host bus bridge holding information on the characteristics of the CI host bus bridge is mounted.
A feature information holding unit on a CI board (a board with built-in PCI or a PCI expansion board) is provided in a PCI host bus bridge, and information in the feature information holding unit and the PCI host bus are provided based on a command from a BIOS.・
A feature information holding unit reading function for reading information about a PCI slot or a PCI device related to the bridge (whether or not a PCI device is mounted in the PCI slot, an interrupt output pin number, and the like);・ Information on the characteristics of the bus bridge and the PC related to the PCI host bus bridge
An information reading function for reading (acquiring) information about the I slot and the PCI device, and an initialization process for the PCI host bus bridge based on the information read by the information reading function (the PCI host bus bridge) And an initialization function for performing initialization of a PCI device and an interrupt controller according to the above-mentioned BIOS.

The PCI host bus bridge system initialization method of the present invention is the same as the PCI host bus bridge system initialization method described above, except that the PCI host bus bridge system has a PCI host bus bridge system in addition to the information reading function and the initialization function. It is also possible to have a BIOS with a hot plug insert handling function that operates the above information reading function and initialization function in response to a hot plug interrupt based on the hot plug insert of the bus bridge. It is.

It should be noted that the PCI host bus bridge system initialization method of the present invention is used in a PCI host bus bridge system capable of mounting a plurality of types of PCI host bus bridges.
The P which holds information on the characteristics of the PCI host bus bridge required to initialize the bus bridge.
A feature information holding unit on a PCI board on which a CI host bus bridge is mounted, and information provided in the feature information holding unit and the PCI host / bus based on a command from a BIOS provided in the PCI host bus bridge. Assuming that a feature information holding unit reading function for reading information on a PCI slot and a PCI device related to a bus bridge exists, a CPU (Central P
processing unit), by using the feature information holding unit reading function, an information reading function of reading information on the feature of the PCI host bus bridge and information on a PCI slot and a PCI device related to the PCI host bus bridge; A program for functioning as the BIOS having an initialization function for performing an initialization process for the PCI host bus bridge based on the information read by the information reading function (“the information reading function and the initialization function described above”). And a BIOS having a hot plug insert handling function for operating the information reading function and the initialization function in response to a hot plug interrupt based on the hot plug insert of the PCI host bus bridge. Or a program for functioning).

[0016]

Next, the present invention will be described in detail with reference to the drawings.

(1) First embodiment

FIG. 1 is a block diagram showing a configuration of a PCI host bus bridge system to which a PCI host bus bridge system initialization method according to a first embodiment of the present invention is applied.

Referring to FIG. 1, P according to the present embodiment
The PCI host bus bridge system to which the CI host bus bridge system initialization method is applied,
CPU 1, memory 2, PCI built-in board 3, PC
And a PCI host bus bridge system that includes a CPU 1, a memory 2, and a PCI built-in board 3 connected on the same bus. 4 is additionally implemented).

On the CPU 1, a BIOS 11 operates.

The BIOS 11 includes a PCI host bus
Bridge 31/41 (PCI host bus bridge 3
1 or EE in PCI host bus bridge 41)
PROM (Electrically Erasable)
e Programmable Read Only M
memory) An information read function for reading information using the read function 310/410, and an initialization function for initializing each PCI host bus bridge 31/41 based on the information.

The PCI built-in board 3 has a PCI host
Bus bridge 31, PCI bus 32, EEPROM
M33, an interrupt controller 34, a PCI device A 35, a PCI device B 36, and a PCI device C 37 are mounted. The PCI device A3
5, PCI device B36 and PCI device C3
Although not shown, 7 is mounted on PCI slot A, PCI slot B, and PCI slot C, respectively.

The interrupt output pin INTA # of the PCI device A35 (the interrupt output pin of the PCI slot used by the PCI device A35) is input to the interrupt input pin INTIN0 # of the interrupt controller 34. Similarly, the interrupt output pin INTA # of the PCI device B36 is input to the interrupt input pin INTIN10 # of the interrupt controller 34, and the interrupt output pin INTA # of the PCI device C37 is connected to the interrupt input pin INTIN30 # of the interrupt controller 34.
Has been entered.

The PCI slot A in which the PCI device A 35 is mounted is assigned a PCI device number "0". Similarly, PCI device B3
PCI device number “1” is assigned to the PCI slot B in which the PCI device C3 is mounted, and the PCI device C3
The PCI device number “2” is assigned to the PCI slot C in which the device 7 is mounted.

The EEPROM 33 holds information on the features of the PCI host bus bridge 31 as shown in the following a to c. It should be noted that "information on the characteristics of the PCI host bus bridge"
Needless to say, it is possible to hold other information such as information indicating the version of the PCI board on which the host bus bridge is mounted (the PCI host bus bridge 41 and the PCI bus described later). The same applies to the host bus bridge 51).

A. Information on interrupt connection indicating "connection state between each interrupt output pin of each PCI slot and each interrupt input pin of interrupt controller 34"

B. Information on a PCI device number indicating “PCI device number assigned to each PCI slot”

C. "PCI Host Bus Bridge 31
Is located below the PCI bus 32 in a PCI slot A (PCI
PCI slot in which device A35 is mounted), P
CI slot B (PCI slot in which PCI device B36 is mounted) and PCI slot C (PCI slot
(PCI slot in which device C37 is mounted) 3
Information about the number of PCI slots, which means that "one PCI slot is provided"

The PCI host bus bridge 31 has an EEPROM read function 310 for reading information (information relating to the characteristics of the PCI host bus bridge 31) held in the EEPROM 33.

The PCI expansion board 4 includes a PCI host
Bus bridge 41, PCI bus 42, EEPRO
M43, an interrupt controller 44, a PCI slot A45, and a PCI slot B46 are mounted. PCI slot A45 and PCI slot B46
Can be equipped with a PCI device.

The interrupt output pin INTA # of the PCI slot A45 is input to the interrupt input pin INTIN0 # of the interrupt controller 44. Similarly, the interrupt output pin INTB # is connected to the interrupt input pin INTIN
1 #, the interrupt output pin INTC # is input to the interrupt input pin INTIN2 #, and the interrupt output pin INTD # is the interrupt input pin INTI
N3 #.

Similarly, the interrupt output pin INTA # of the PCI slot B46 is input to the interrupt input pin INTIN10 # of the interrupt controller 44, and the interrupt output pin INTB # is set to the interrupt input pin INTIN.
11 #, and the interrupt output pin INTC #
Is input to an interrupt input pin INTIN12 #, and the interrupt output pin INTD # is an interrupt input pin I
It has been input to NTIN13 #.

The PCI slot A45 contains a PCI
The device number “0” is given. Similarly, PC
The PCI device number “1” is given to the I slot B46.

The EEPROM 43 holds information on the features of the PCI host bus bridge 41 as shown in the following a to c.

A. Information on interrupt connection indicating "connection state between each interrupt output pin of each PCI slot and each interrupt input pin of interrupt controller 44"

B. Information on a PCI device number indicating “PCI device number assigned to each PCI slot”

C. "PCI Host Bus Bridge 41
Has two PCI slots under the PCI bus 42, a PCI slot A45 and a PCI slot B46. "

The PCI host bus bridge 41 has an EEPROM reading function 410 for reading information (information relating to the characteristics of the PCI host bus bridge 41) held in the EEPROM 43.

It should be noted that EEPR is used as a holding unit for holding “information on the characteristics of the PCI host bus bridge”.
It is also possible to adopt a “feature information holding unit” other than the OM. In this case, the "EEPROM read function"
Means “feature information holding unit reading function”.

FIG. 2 shows an EEPROM read function 310.
FIG. 3 is a block diagram showing a configuration of a register at / 410.

Referring to FIG. 2, the EEPROM read function 310/410 includes a command register 200,
A sub-command register 201 (a register for a first sub-command) and a sub-command register 202
(A register for the second sub-command) and a data register 203.

FIG. 3 shows the command register 200, the sub command register 201, the sub command register 202, and the data register 203 in FIG.
It is a figure which shows the specific example of the content of.

The BIOS 11 has a command register 20
0 after writing command 0 # to data register 2
03, the PCI slot (PCI bus 3) provided in the PCI host bus bridge 31/41 is read.
The number of PCI slots connected to 2/42) can be known.

For example, if the BIOS 11 is a PCI host
EEPROM reading function 410 of bus bridge 41
When the data register 203 is read after the command 0 # is written in the command register 200, the value "the number of PCI slots = 2" can be obtained. this is,
"The PCI host bus bridge 41 has two PCI slots."

If the result of reading the data register 203 is "the number of PCI slots = 0", it indicates that "the PCI host bus bridge does not have a PCI slot".

The BIOS 11 writes the command 1 # in the command register 200, writes the slot number in the sub-command register 201, and then reads the data register 203 to read the PCI slot of the slot number. Can be found.

For example, if the BIOS 11 is a PCI host
EEPROM reading function 410 of bus bridge 41
After the command 1 # is written in the command register 200 and the slot number "0" of the PCI slot A45 is written in the sub-command register 201, the data register 203 is read.
0 "can be obtained. This indicates that "PCI device number" 0 "is given to PCI slot A45 of PCI host bus bridge 41". The BIOS 11 can use this PCI device number to initialize the PCI device mounted in the PCI slot A45.

When the result of reading data register 203 is a value "FF" indicating an error,
"There is no PCI slot for which a slot number is specified in the sub-command register 201."

The BIOS 11 writes the command 2 # into the command register 200, and
The slot number is written in the register 201, the interrupt output pin number is written in the sub-command register 202, and then the data register 203 is read.
It is possible to know which interrupt input pin of the interrupt controller 34/44 (interrupt input pin number of the interrupt input pin) the interrupt output pin (interrupt output pin of the interrupt output pin number) of the corresponding interrupt output pin of the I slot). it can.

For example, when the BIOS 11 is a PCI host
EEPROM reading function 410 of bus bridge 41
The command 2 # is written in the command register 200, the slot number "0" of the PCI slot A45 is written in the sub-command register 201, and the interrupt output pin number "1" ( After writing INTA #)
By reading the data register 203, a value "interrupt input pin number = 0" can be obtained. This is "P
PCI slot A4 of CI host bus bridge 41
No. 5 interrupt output pin INTA # is input to the interrupt input pin INTIN0 # (interrupt input pin number is “0” interrupt input pin) of the interrupt controller 44 ”.

If the result of reading the data register 203 is "FF" indicating an error,
This indicates that the interrupt output pin whose interrupt output pin number is specified in the sub-command register 202 is not input to the interrupt input pin of the interrupt controller 34/44.

Here, in the above process (the process of reading the contents of the data register 203 of the EEPROM reading function 310/410 by the BIOS 11),
The OM read function 310/410 executes the data register 203 based on the command written by the BIOS 11 to the command register 200, the sub-command register 201, and the sub-command register 202.
Set the data to.

FIG. 4 is a flowchart showing processing of the PCI host bus bridge system initialization method according to the present embodiment. This processing includes a PCI host bus bridge detection step S1, a PCI slot number acquisition step S2, a PCI slot related initialization processing start step S3, and an all PCI slot initialization end determination step S4.
A PCI device number obtaining step S5, a PCI device mounting presence / absence determining step S6, an interrupt output pin number obtaining step S7, an interrupt input pin number obtaining step S8, a PCI device initialization step S9,
It comprises an interrupt controller initialization step S10.

Next, referring to FIG. 1 to FIG. 4, the PCI host bus
The overall operation of the bridge system initialization method will be described in detail.

When the BIOS 11 detects the PCI host bus bridge 31/41 (step S in FIG. 4).
1), using the EEPROM read function 310/410 in the PCI host bus bridge 31/41,
The number of PCI slots provided in the PCI host bus bridge 31/41 is obtained (step S2).

The BIOS 11 is provided with all the PCI slots related to the PCI host bus bridge 31/41 (the PCI built-in board 3 / PCI expansion board 4 in which the PCI host bus bridge 31/41 is mounted).
A process of repeating the initialization of each PCI slot (a series of initialization processes in steps S4 to S10 described below) is started for all the above PCI slots (step S).
3).

First, the BIOS 11 determines whether initialization has been completed for all PCI slots (Step S).
4).

If it is determined in step S4 that "the initialization for all PCI slots has been completed", the BIOS 11
Ends the processing shown in FIG. If the number of PCI slots acquired in step S2 is “0”, the PCI
Since the host bus bridge 31/41 does not have a PCI slot, the BIOS 11 ends the processing shown in FIG. 4 (steps S3 and S4).

In step S4, the BIOS 11 reads “all PCs”.
If it is determined that the initialization for the I slot has not been completed yet, the initialization for one of the unprocessed PCI slots is started.

First, the BIOS 11 executes the EEPRO
Using the M read function 310/410, the PCI device number assigned to the PCI slot is obtained (step S5).

Next, the BIOS 11 uses the PCI device number acquired in step S5 to set the vendor ID (ID).
By reading the device ID and the device ID, it is checked whether a PCI device is mounted in the PCI slot (step S6).

If the BIOS 11 determines in step S6 that "all F values have been read (master aborted) as the values of the vendor ID and device ID",
It is determined that no PCI device is mounted in the PCI slot, and the process proceeds to the next PCI slot (see step S3).

On the other hand, if the BIOS 11 determines in step S6 that "a value other than All-F has been read as the value of the vendor ID and the device ID", "the PCI slot is mounted with a PCI device" Then, initialization processing as shown in the following a to d is performed (when these processings are completed, the processing moves to the next PCI slot).

A. First, the PCI acquired in step S5
Using the device number, the interrupt pin register of the PCI device mounted on the PCI slot is read, and the interrupt output pin number of the interrupt output pin used by the PCI device is obtained (Step S).
7). For example, if the value of “interrupt output pin number = 1” can be read as the content of the interrupt pin register, “the PCI device is interrupt output pin INTA
# (Interrupt output pin number “1” interrupt output pin) is being used ”.

B. Next, the EEPROM read function 31
Using 0/410, the interrupt output pin of the interrupt output pin number acquired in step S7 is input to which interrupt input pin of the interrupt controller 34/44 (interrupt input pin number of the interrupt input pin)
Is obtained (step S8). For example, when the value “interrupt input pin number = 0” can be read as the content of the data register 203 of the EEPROM read function 310/410, “the interrupt output pin is the interrupt input pin INTIN0 # of the interrupt controller 34/44.
(Interrupt input pin with interrupt input pin number "0")
(Acquired).

C. Next, the PCI acquired in step S5
A PCI device mounted in the PCI slot is initialized using the device number (step S9).
Specifically, an interrupt vector is set in an interrupt line register of the PCI device, and an interrupt output from the PCI device is permitted.

D. Finally, the interrupt controller 34 /
44 (initialization relating to the PCI slot) is performed (step S10). Specifically, the same interrupt vector as the interrupt vector set in step S9 is set to the interrupt input pin of the interrupt controller 34/44 specified by the interrupt input pin number acquired in step S8, and the The input of the interrupt output signal to the interrupt controller 34/44 is permitted.

As described above, the initialization of the PCI device and the interrupt controller 34/44 is performed, whereby “the PCI device is transmitted to the BIOS 11 operating on the CPU 1 through the interrupt controller 34/44. Notification of interruption "is possible.

Next, a specific operation of the PCI host bus bridge system initialization method according to the present embodiment in the PCI host bus bridge system configured as shown in FIG. 1 will be described.

First, the operation for initializing the PCI device A 35 (the PCI device mounted in the PCI slot A) of the PCI host bus bridge 31 mounted on the PCI built-in board 3 will be described in one concrete manner. This will be described as an example. The operation in this case can be considered as an operation in a PCI single host bus bridge system (a system in which the PCI expansion board 4 is not mounted) including the CPU 1, the memory 2, and the PCI built-in board 3.

When the BIOS 11 detects the PCI host bus bridge 31 (Step S1 in FIG. 4), the EE
Command register 20 of PROM read function 310
After writing the command 0 # to the data register 203, the PCI host bus bridge 3
The number of PCI slots provided in 1 is acquired (step S2). PCI host bus bridge 31 is PCI
Since three slots are provided, a value of “the number of PCI slots = 3” can be obtained here.

The BIOS 11 processes the PCI slot A, which is one of the PCI slot numbers acquired as described above, as shown in the following a to f (the PCI slot A in which the PCI device A 35 is mounted). Initialization processing).

A. After writing the command 1 # in the command register 200 of the EEPROM read function 310 and writing the slot number “0” of the PCI slot A in which the PCI device A 35 is mounted in the sub-command register 201, the data Register 20
3, the P assigned to the PCI slot A is read.
A CI device number is obtained (step S5). PCI
Since the PCI slot A in which the device A35 is mounted is given the PCI device number “0”, the value “PCI device number = 0” can be acquired here.

B. Using the PCI device number “0” obtained in step S5, the vendor I of the PCI slot A is used.
D and the device ID are read, and the PC is
It is checked whether or not the I device is mounted (Step S6). The PCI slot A contains a PCI device A35.
Are incorporated as internal devices on the PCI internal board 3. Therefore, here, a value (unique value) other than All F can be read, and it is determined that "PCI device A (PCI device A35) is mounted in PCI slot A", and this PCI device A35 is read.
The initialization for (PCI slot A) is started.

C. That is, the P acquired in step S5
Using the CI device number “0”, the PCI device A
The CPU reads the interrupt pin register No. 35 and acquires the interrupt output pin number of the interrupt output pin used by the PCI device A35 (step S7). Since the PCI device A35 uses the interrupt output pin INTA #, the value "interrupt output pin number = 1" can be read here.

D. Next, the EEPROM read function 31
0 is written to the command register 200 of 0, the slot number “0” of the PCI slot A is written to the sub-command register 201, and
After writing the interrupt output pin number “1” obtained in step S7 to the command register 202, the data register 203 is read to read the PCI device A35.
Then, the interrupt input pin number of the interrupt input pin of the interrupt controller 34 to which the interrupt output pin INTA # being used is input is obtained (step S8). P
Interrupt output pin I used by CI device A35
Since NTA # is input to the interrupt input pin INTIN0 # of the interrupt controller 34, here,
The value “interrupt output pin number = 0” can be read.

E. The PCI device A 35 is initialized using the PCI device number acquired in step S5 (step S9). Specifically, the PCI device A35
The interrupt vector is set in the interrupt line register of the PCI device A35, and the interrupt output pin INTA of the PCI device A35 is set.
Enable interrupt output from #.

F. Initialization of the interrupt controller 34 (interrupt input pin IN for PCI device A35)
(TIN0 # initialization) (Step S1)
0). Specifically, the same interrupt vector as the interrupt vector set in step S9 is set to the interrupt input pin INTIN0 # having the interrupt input pin number acquired in step S8, and the interrupt output pin INTA # (PCI
The input of the interrupt output signal from the interrupt output pin used by the device A35 to the interrupt controller 34 (interrupt input pin INTIN0 #) is permitted.

By performing the initialization as described above, the interrupt from the PCI device A 35 is transmitted to the interrupt controller 3.
4, it becomes possible to notify the BIOS 11 operating on the CPU 1.

Secondly, the operation when the initialization process for the PCI host bus bridge 41 mounted on the PCI expansion board 4 is performed will be described. The operation in this case is performed by a PCI single host host configured by the CPU 1, the memory 2, and the PCI built-in board 3.
It is also considered that the operation may be performed when a PCI expansion board 4 is additionally mounted on the bus bridge system for system configuration expansion. Here, the PCI slot A45
No PCI device is mounted on the PCI slot B46, and a PCI device is mounted on the PCI slot B46.

When the BIOS 11 detects the PCI host bus bridge 41 (Step S1 in FIG. 4), the EE
Command register 20 of PROM read function 410
After the command 0 # is written in the PCI host bus bridge 4
The number of PCI slots provided in 1 is acquired (step S2). PCI host bus bridge 41 is PCI
Since two slots are provided, a value of “the number of PCI slots = 2” can be obtained here.

The BIOS 11 performs the following processes a to h for each PCI slot corresponding to the number of PCI slots acquired as described above.

A. The command 1 # is written in the command register 200 of the EEPROM read function 410, and the slot number “0” of the PCI slot A45 is written in the sub-command register 201, and then the data register 203 is read. Slot A
The PCI device number assigned to the device 45 is obtained (step S5). Since the PCI slot A45 is assigned the PCI device number “0”,
The value “PCI device number = 0” can be obtained.

B. Using the PCI device number “0” obtained in step S5, the vendor ID and device ID of the PCI slot A45 are read, and the PCI slot A4 is read.
It is checked whether or not a PCI device is mounted in Step 5 (Step S6). Since no PCI device is mounted in the PCI slot A45, here, the value of all F (master abort) is read and “PCI slot A4
No PCI device is mounted in 5 ", and the process proceeds to the next PCI slot B46.

C. The command 1 # is written in the command register 200 of the EEPROM read function 410, and the slot number "1" of the PCI slot B46 is written in the sub-command register 201, and then the data register 203 is read. Slot B
The PCI device number given to 46 is obtained (step S5). Since the PCI device number “1” is given to the PCI slot B46, here,
The value “PCI device number = 1” can be obtained.

D. Using the PCI device number “1” obtained in step S5, the vendor ID and device ID of the PCI slot B46 are read, and the PCI slot B4 is read.
It is checked whether or not a PCI device is mounted on the device 6 (step S6). Since a PCI device is mounted in the PCI slot B46, a value (unique value) other than All-F can be read. Here, it is determined that "the PCI device is mounted in the PCI slot B46". Then, initialization for the PCI slot B46 is started.

E. That is, the P acquired in step S5
Using the CI device number “1”, the PCI slot B
The interrupt pin of the PCI device mounted on 46
The register is read, and the interrupt output pin number of the interrupt output pin used by the PCI device is obtained (step S7). Since the PCI device mounted in the PCI slot B46 uses the interrupt output pin INTB #, here, “interrupt output pin number = 2”
You can read the value.

F. Next, the EEPROM read function 41
0 is written to the command register 200, the slot number “1” of the PCI slot B 46 is written to the sub-command register 201, and the interrupt output pin acquired at step S7 is written to the sub-command register 202. By reading the data register 203 after writing the number “2”, the PCI slot B
The interrupt input pin number of the interrupt input pin of the interrupt controller 44 to which the interrupt output pin INTB # used by the PCI device mounted on 46 is input (step S8). PCI slot B4
The interrupt output pin INTB # used by the PCI device mounted on the
In this case, the value "interrupt output pin number = 11" can be read here.

G. Using the PCI device number acquired in step S5, the PCI device mounted in the PCI slot B46 is initialized (step S9). Specifically, the PCI mounted in the PCI slot B46
The interrupt vector is set in the interrupt line register of the device, and the interrupt output pin I of the PCI device is set.
Enables interrupt output from NTB #.

H. Initialization of the interrupt controller 44 (interrupt input pin IN for PCI slot B46)
(TIN11 # initialization) (Step S1)
0). Specifically, the same interrupt vector as the interrupt vector set in step S9 is set to the interrupt input pin INTIN11 # having the interrupt input pin number acquired in step S8, and the interrupt output pin INTB # (PC
The interrupt controller 44 (interrupt input pin INT) of the interrupt output signal from the interrupt output pin used by the PCI device mounted in the I slot B46
IN11 #) is permitted.

By performing the initialization as described above, an interrupt from the PCI device mounted in the PCI slot B 46 is transmitted to the CPU 1 via the interrupt controller 44.
It becomes possible to notify the BIOS 11 operating above.

(2) Second Embodiment

FIG. 5 is a block diagram showing a configuration of a PCI host bus bridge system to which a PCI host bus bridge system initialization method according to a second embodiment of the present invention is applied.

Referring to FIG. 5, P according to the present embodiment is
The PCI host bus bridge system to which the CI host bus bridge system initialization method is applied,
CPU 1, memory 2, PCI built-in board 3, PC
It is configured to include an I extension board 4 and a PCI extension board 5 (CPU 1, memory 2, PCI built-in board 3, and PCI extension board 4 in the first embodiment).
A PCI host bus bridge system configured to include a PC in the form of a hot plug insert
I extension board 5 is additionally mounted).

On the CPU 1, the BIOS 11 and the OS
(Operating System) 12 is operating.

The BIOS 11 is connected to each PCI host bus
EEPROM in bridge 31/41/51 (PCI host bus bridge 31, PCI host bus bridge 41, or PCI host bus bridge 51)
An information read function for reading information using the read functions 310/410/510, an initialization function for initializing each PCI host bus bridge 31/41/51 based on the information, and a hot read function. A hot plug insert handling function for operating the information reading function and the initialization function in response to the hot plug interrupt 6 based on the plug insert is included.

The PCI expansion board 5 includes a PCI host
Bus bridge 51, PCI bus 52, EEPROM
M53, an interrupt controller 54, and a PCI slot A55 are mounted. A PCI device can be mounted in the PCI slot A55.

[0098] The interrupt output pin INTA # of the PCI slot A55 is input to the interrupt input pin INTIN0 # of the interrupt controller 54. Similarly, the interrupt output pin INTB # is connected to the interrupt input pin INTIN
1 #, the interrupt output pin INTC # is input to the interrupt input pin INTIN2 #, and the interrupt output pin INTD # is the interrupt input pin INTI
N3 #.

The PCI slot A55 contains a PCI
The device number “0” is given.

The EEPROM 53 holds information on the features of the PCI host bus bridge 51 as shown in the following a to c.

A. Information on interrupt connection indicating "connection state between each interrupt output pin of PCI slot A55 and each interrupt input pin of interrupt controller 54"

B. Information on a PCI device number indicating “PCI device number assigned to PCI slot A55”

C. "PCI Host Bus Bridge 51
Has one PCI slot, PCI slot A55, under the PCI bus 52.
Information on the number of I slots

The PCI host bus bridge 51 has an EEPROM reading function 510 for reading information (information relating to the characteristics of the PCI host bus bridge 51) held in the EEPROM 53.

As described above, the PCI host shown in FIG.
The bus bridge system is different from the PCI host bus bridge system in the first embodiment in that the PCI expansion board 5 (PCI host bus bridge 51) is operated while the BIOS 11 and the OS 12 are operating on the CPU 1. Indicates a system configuration when hot plug insertion is performed.

FIGS. 2, 3, and 4 also apply to the PCI host bus bridge system initialization method according to the present embodiment. For example, referring to FIG. 2, the EEPROM read function 510 includes an EEPROM
Similarly to the M read function 310/410, the command register 200, the sub-command register 201 (register for the first sub-command), and the sub-command register 202 (the second sub-command Register) and a data register 203.

Next, with reference to FIG. 2 to FIG. 5, the PCI host bus
The overall operation of the bridge system initialization method will be described. The PCI host on the PCI built-in board 3
PC on bus bridge 31 and PCI expansion board 4
The operation of the initialization process for the I host bus bridge 41 is the same as the operation in the first embodiment.

If the PCI expansion board 5 (PCI host bus bridge 51) is hot plug inserted while the BIOS 11 and the OS 12 are operating on the CPU 1, a hot plug interrupt 6 is reported to the BIOS 11.

When the BIOS 11 receives the hot plug interrupt 6, the BIOS 11 searches whether or not a PCI host bus bridge has been added, and attempts to detect it.

When the BIOS 11 detects the PCI host bus bridge 51 mounted on the PCI expansion board 5 (step S1 in FIG. 4), the BIOS 11 initializes the PCI host bus bridge 51, and resets the PCI host bus bridge 51.
Integrate into the system.

The basic operation in the initialization of the PCI host bus bridge 51 is the same as the initialization of the PCI host bus bridge 31 and the initialization of the PCI host bus bridge 41 in FIG.

That is, the BIOS 11 having received the hot plug interrupt 6 uses the EEPROM read function 510 of the PCI host bus bridge 51 to
The number of PCI slots provided in the CI host bus bridge 51 is obtained (step S2). Since the PCI expansion board 5 has one PCI slot, “1” is acquired here as the number of PCI slots.

The BIOS 11 acquires the PCI device number assigned to the PCI slot A55, which is one PCI slot on the PCI expansion board 5, by using the EEPROM read function 510 (Step S).
5).

Next, the BIOS 11 uses the PCI device number acquired in step S5 to
It is checked whether or not a PCI device is mounted on 55 (step S6).

If a PCI device is mounted in the PCI slot A55, the BIOS 11 uses the PCI device number obtained in step S5 to output the interrupt output of the interrupt output pin used by the PCI device. A pin number is obtained (step S7).

The P mounted on the PCI slot A55
If the CI device uses the interrupt output pin INTA #, the BIOS 11 uses the EEPROM read function 510 to output the interrupt input pin INTIN0 # of the interrupt controller 54 to which the interrupt output pin INTA # has been input. The number "0" is acquired (step S8).

Next, the BIOS 11 uses the PCI device number acquired in step S5 to
The PCI device mounted on the device 55 is initialized (step S9). Specifically, an interrupt vector is set in an interrupt line register of the PCI device, and an interrupt output from the PCI device is permitted.

Further, the BIOS 11 initializes the interrupt controller 54 (initialization relating to the PCI slot A55) (step S10). Specifically, the interrupt input pin (PC) of the interrupt controller 54 specified by the interrupt input pin number acquired in step S8
(Interrupt input pin INTIN0 # of interrupt controller 54 to which interrupt output pin INTA # of the PCI device mounted in I slot A55 is input.)
In step S9, the same interrupt vector as the interrupt vector set in step S9 is set, and the interrupt controller 54 (interrupt input pin INTIN0) of the interrupt output signal from the PCI device (interrupt output pin INTA #) is set.
#) Input is allowed.

As described above, the BIOS 11 initializes the PCI host bus bridge 51 on the PCI plug-in board 5 into which the hot plug has been inserted, and resets the PCI host bus of the PCI host bus bridge 51. -Enables integration into bridge systems.

(3) Third Embodiment

FIG. 6 is a block diagram showing a configuration of a PCI host bus bridge system initialization system according to the third embodiment of the present invention.

Referring to FIG. 6, the PCI host bus bridge system initialization method according to the third embodiment of the present invention is the same as that of the PC host bus bridge system according to the first embodiment shown in FIG.
The difference is that a bridge-related initialization processing program 600 is provided for the I host bus bridge system initialization method.

Bridge-related initialization processing program 600
Is read by the CPU 1 and the operation of the CPU 1 is
Bridge-related initialization function on IOS 11 (information reading function and initialization function in PCI host bus bridge system initialization method according to the first embodiment)
To control. Bridge-related initialization processing program 6
The operation of the BIOS 11 under the control of 00 is exactly the same as the operation of the BIOS 11 in the first embodiment, and a detailed description thereof will be omitted.

(4) Fourth Embodiment

FIG. 7 is a block diagram showing a configuration of a PCI host bus bridge system initialization system according to the fourth embodiment of the present invention.

Referring to FIG. 7, the PCI host bus bridge system initialization method according to the fourth embodiment of the present invention is similar to the PC host bus bridge system according to the second embodiment shown in FIG.
The difference is that a bridge-related initialization processing program 700 is provided for the I host bus bridge system initialization method.

Bridge-related initialization processing program 700
Is read by the CPU 1, and the operation of the CPU 1 is
Control is performed as a bridge-related initialization function on the IOS 11 (information reading function, initialization function, and hot plug insertion handling function in the PCI host bus bridge system initialization method according to the second embodiment). The operation of the BIOS 11 under the control of the bridge-related initialization processing program 700 is exactly the same as the operation of the BIOS 11 in the second embodiment, and a detailed description thereof will be omitted.

[0128]

As described above, according to the present invention,
The following effects are produced.

The first effect is that one BIOS can use a plurality of (various) types of P without rewriting the BIOS.
An initialization process for the CI host bus bridge can be realized, and the PCI host bus bridge can be incorporated in a PCI host bus bridge system.

The reason why such an effect occurs is that the function that depends on the PCI host bus bridge is separated from the inside of the BIOS, and instead information about the characteristics of the PCI host bus bridge (for example, information about the number of PCI slots, PCI device number information and interrupt connection information) are stored in a characteristic information storage unit (for example, EEPROM) on a PCI board on which a PCI host bus bridge is mounted.
Functions on the I-host bus bridge (eg, EEPR
OM read function) and read the information,
This is for performing initialization processing relating to the I host bus bridge.

A second effect is that, in addition to the above, by providing the BIOS with a hot plug / insert handling function, the initialization relating to the PCI host bus bridge on the hot plug / inserted PCI expansion board can be achieved. On the other hand, the first effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a P to which a PCI host bus bridge system initialization method according to a first embodiment of the present invention is applied;
FIG. 2 is a block diagram illustrating a configuration of a CI host bus bridge system.

FIG. 2 is a block diagram showing a configuration of a register in an EEPROM reading function in FIGS. 1 and 5;

3 is a diagram showing a specific example of the contents of a command register, a sub-command register group, and a data register in FIG. 2;

FIG. 4 is a flowchart showing processing of a PCI host bus bridge system initialization method according to the first embodiment and the second embodiment of the present invention.

FIG. 5 illustrates a P to which a PCI host bus bridge system initialization method according to a second embodiment of the present invention is applied;
FIG. 2 is a block diagram illustrating a configuration of a CI host bus bridge system.

FIG. 6 is a block diagram showing a configuration of a PCI host bus bridge system initialization method according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a PCI host bus bridge system initialization method according to a fourth embodiment of the present invention.

FIG. 8 is a diagram for explaining a conventional PCI host bus bridge system initialization method (a diagram showing a specific example of a PCI host bus bridge table).

[Explanation of symbols]

 1 CPU 2 Memory 3 PCI Built-in Board 4, 5 PCI Expansion Board 6 Hot Plug Interrupt 11 BIOS 12 OS 31, 41, 51 PCI Host Bus Bridge 32, 42, 52 PCI Bus 33, 43, 53 EEPROM 34, 44 , 54 Interrupt controller 35 PCI device A 36 PCI device B 37 PCI device C 45, 55 PCI slot A 46 PCI slot B 200 Command register 201, 202 Sub command register 203 Data register 310, 410, 510 EEPROM read function 600, 700 Bridge-related initialization processing program

Claims (8)

[Claims] In a PCI host bus bridge system capable of mounting a plurality of types of PCI host bus bridges, a PCI host bus bridge required for initializing the PCI host bus bridge is provided. A feature information holding unit on a PCI board on which the PCI host bus bridge holding information related to the feature is mounted, and a PCI bus bus bridge;
Using a feature information holding unit reading function for reading information in the feature information holding unit and information about a PCI slot and a PCI device related to the PCI host bus bridge based on a command from the BIOS, and using the feature information holding unit reading function An information reading function for reading out information on the characteristics of the PCI host bus bridge and information on a PCI slot and a PCI device related to the PCI host bus bridge, and And a BIOS having an initialization function for performing an initialization process for the host bus bridge. 2. In addition to the information reading function and the initialization function, the information reading function and the initialization function are operated in response to a hot plug interrupt based on a hot plug insertion of the PCI host bus bridge. BIO with hot plug insert handling function
2. The PCI host bus bridge system initialization method according to claim 1, further comprising: S. 3. “Information on PCI host bus bridge characteristics” is “information on the number of PCI slots, P
3. The PCI host bus bridge system initialization method according to claim 1, wherein "information related to a CI device number and information related to an interrupt connection". 4. The "characteristic information holding unit" is "EEPROM"
4. The PCI host bus bridge system initialization system according to claim 1, wherein: 5. In a PCI host bus bridge system capable of mounting a plurality of types of PCI host bus bridges, a PCI host bus bridge required for initializing the PCI host bus bridge A feature information holding unit on a PCI board on which the PCI host bus bridge holding information related to the feature is mounted, and a PCI bus bus bridge;
Based on a command from the BIOS, the CPU is assumed to have a feature information holding unit reading function for reading information in the feature information holding unit and information on a PCI slot and a PCI device related to the PCI host bus bridge. The information on the characteristics of the PCI host bus bridge and the P related to the PCI host bus bridge by using the characteristic information holding unit read function.
A function as the BIOS having an information reading function of reading information on the CI slot and the PCI device, and an initialization function of performing an initialization process on the PCI host bus bridge based on the information read by the information reading function. Program to let you. 6. The CPU has an information reading function and an initialization function, and copes with a hot plug interrupt based on a hot plug insertion of a PCI host bus bridge. 6. A function for functioning as a BIOS having a hot plug / insert handling function for operating a computer.
The program described. 7. “Information on PCI host bus bridge characteristics” includes “information on the number of PCI slots, P
7. The program according to claim 5, wherein the information is information relating to a CI device number and information relating to an interrupt connection. 8. The "characteristic information holding unit" is "EEPROM"
8. The program according to claim 5, wherein the program is: