JP2002312191A - Memory emulation device and data providing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change operation characteristics in matching with the data read operation in a target board. SOLUTION: A synchronous timing generating circuit 30 becomes active, when a read mode set by a mode set switch 14 is a synchronous burst read mode, and outputs a signal on the basis of an address signal and a control signal transmitted from the target board. Here, an asynchronous timing generating circuit 31 becomes non-active, and a logical level of the address signal and the control signal is set 'Hi'. The synchronous timing generating circuit 30 becomes non-active, when the read mode set by the mode set switch 14 is an asynchronous page read mode, and the logical level of the address signal and the control signal is set to 'Hi'. Here, the asynchronous timing generating circuit 31 becomes active and outputs a signal, on the basis of the address signal and the control signal transmitted from the target board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory emulation device and a data supply method.

[0002]

2. Description of the Related Art A ROM emulator is used to verify the operation of an electronic circuit having a microprocessor such as a CPU (Central Processing Unit) or MPU (Micro Processing Unit) and to debug an operation program such as firmware. A known memory emulation device is known. The memory emulation device uses an electronic circuit (target board) to be verified
By connecting a connector to a socket for mounting a nonvolatile memory such as an OM or a flash memory, the connector is connected to a target board. The memory emulation device is also connected to an external computer system to supply instruction codes and data for verification to the target board.

FIG. 7 is a diagram illustrating a configuration in which a conventional memory emulation device 200 is connected to a target board 201 and an external computer system 202. In this configuration, the memory emulation device 200 sets the operation states of the first and second buffers 51 and 52 to an enabled (operating) state and a disabled (stopped) state.
Exclusively switch between states.

That is, the memory emulation device 2
00, when the download microcomputer 50 writes an instruction code or data sent from the external computer system 202 to an SRAM (Static Random Access Memory) 53, the first buffer 51 is disabled, and the second The buffer 52 is enabled. At this time, the download microcomputer 50 communicates with the external computer system 20 via a predetermined input / output interface.
2 to be stored in the SRAM 53 in order to enable reading by the target board 201.

Further, a memory emulation device 200
Sets the first buffer 51 to an enabled state and the second buffer 52 to a disabled state so that the instruction code and data stored in the SRAM 53 can be read from the target board 201. Target board 2
01 is connected to the connector 55 and the flat cable 54 fitted in the socket 61, the first buffer 51, and R
By supplying an address signal and a control signal similar to those for reading data from a nonvolatile memory such as an OM or a flash memory to the memory emulation device 200, the SRAM
The instruction code and data stored in 53 can be read. The instruction code and data read from the SRAM 53 are sent to the microcomputer 60 included in the target board 201 and subjected to various processes.

[0006]

In the above prior art, an instruction code or data stored in an SRAM included in a memory emulation device is read out by random access from a target board. On the other hand, the R mounted on the socket of the target board
Some non-volatile memories, such as OMs and flash memories, are capable of reading stored data in a read mode other than random access, such as a synchronous burst read mode or an asynchronous page read mode, in order to enable high-speed read of stored data. is there.

For this reason, the read operation of the instruction code or data stored in the SRAM included in the memory emulation device may be significantly different from the read operation of the nonvolatile memory actually mounted on the socket of the target board. Was. Here, in order to more strictly verify the operation of the target board, the operation of supplying an instruction code and data from the memory emulation device to the target board should also be close to the operation of reading data from the actually used nonvolatile memory. desirable.

The present invention has been made in view of the above situation, and has as its object to provide a memory emulation device capable of changing its operation characteristics in accordance with a data read operation on a target board.

[0009]

In order to achieve the above object, a memory emulation device according to a first aspect of the present invention supplies data for verifying the operation of a target board to the target board. A random access means; a first signal output means for outputting a signal corresponding to a synchronous burst read mode for burst reading data stored in the storage means in synchronization with a clock signal; A second signal output means for outputting a signal corresponding to an asynchronous page read mode for asynchronously reading data stored in the storage means in a page, and an output from one of the first and second signal output means. By selecting the selected signal and supplying the selected signal to the storage means, the data stored in the storage means is read out and the target is read out. And a selection supply means for supplying Tobodo, characterized in that.

[0010] Mode setting means for switching and setting between a synchronous burst read mode and an asynchronous page read mode is provided, and the first signal output means is a synchronous burst read mode in which the read mode set by the mode setting means is set. In this case, a signal based on the address signal and the control signal sent from the target board is output, and the second signal output means outputs the signal when the read mode set by the mode setting means is the asynchronous page read mode. Outputting a signal based on an address signal and a control signal sent from the target board, wherein the selection and supply unit outputs the first signal when the read mode set by the mode setting unit is a synchronous burst read mode. A signal output from the signal output means is selected and supplied to the storage means, and the signal is output by the mode setting means. When the set read mode is asynchronous page read mode, it is desirable to select a signal output from the second signal output means for supplying to said memory means.

[0011] A burst size setting means for setting a size of a transfer data unit when the read mode set by the mode setting means is a synchronous burst read mode, wherein the first signal output means is provided with the mode setting means. When the read mode set by (1) is the synchronous burst read mode, it is desirable to generate and output an address signal corresponding to the size of the transfer data unit set by the burst size setting means.

[0012] The first signal output means includes a clock generation means for generating a clock signal having a size of a transfer data unit set by the burst size setting means, and counts the clock signal generated by the clock generation means. The address signal supplied from the target board as an upper address, and an address signal output unit that outputs an address signal with the count value of the clock signal in the counting unit as a lower address and sends the address signal to the selection supply unit. It is desirable to have.

[0013] A data supply method according to a second aspect of the present invention is a data supply method, comprising: a randomly accessible storage means;
And a second signal output means, a signal selection means, and a mode setting means, wherein the memory emulation device supplies data to the target board, wherein the mode setting means is synchronized with a clock signal. A mode setting step of switching between a synchronous burst read mode for performing burst read and an asynchronous page read mode for performing page read asynchronously with a clock signal to set a read mode of data stored in the storage means; A signal output unit that outputs a signal based on the address signal and the control signal sent from the target board when the read mode set by the mode setting unit in the mode setting step is a synchronous burst read mode. 1
And the second signal output means, when the read mode set by the mode setting means in the mode setting step is an asynchronous page read mode, the address signal sent from the target board and A second signal output step of outputting a signal based on a control signal; and wherein the signal selecting means is configured to output the signal when the read mode set by the mode setting means in the mode setting step is a synchronous burst read mode. In the first signal output step, the signal output by the first signal output means is selected and supplied to the storage means, and the read mode set by the mode setting means in the mode setting step is the asynchronous page In the read mode, the signal is output by the second signal output means in the second signal output step. By supplying to the storage means to select the item, and a selection supply step of supplying to the target board reads the data stored in the storage means, characterized in that.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory emulation device according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a memory emulation device 100 according to an embodiment of the present invention.
The memory emulation device 100 has a CPU (Ce
a target board 101 having a microcomputer 20 including a microprocessor such as a ntral processing unit, and an instruction code or data transmitted from the external computer system 102 connected to the external computer system 102. Supply.

As shown in FIG. 1, the memory emulation device 100 includes a download microcomputer 10 and a first microcomputer.
And second buffers 11 and 12 and an SRAM (Static R)
andom Access Memory) 13 and mode setting switch 1
4, a burst size setting switch 15, a timing generation circuit 16, a flat cable 17, and a connector 1.
8 is provided.

The download microcomputer 10 is, for example, a parallel interface or a USB (Universal Serial B
external computer system 10 such as a PC (Personal Computer) or a workstation via a predetermined input / output interface such as a us) interface.
2 are connected. The microcomputer for download 10
The operation states of the first and second buffers 11 and 12 are switched according to an instruction sent from the external computer system 102. In addition, the microcomputer for download 10
Instruction codes and data sent from the external computer system 102 are stored in the SRAM 13.

The first and second buffers 11 and 12 exclusively switch between an enabled (operating) state and a disabled (stopped) state in accordance with the control of the download microcomputer 10, thereby connecting the SRAM 13 to the socket of the target board 101. This is to make it function similarly to a nonvolatile memory such as a ROM or a flash memory mounted on the memory 21. That is, the first buffer 11 is provided between the timing generation circuit 16 and the flat cable 17 and is enabled when an instruction code or data is supplied from the memory emulation device 100 to the target board 101. The first buffer 11 is disabled when the instruction code and data sent from the external computer system 102 are stored in the SRAM 13. On the other hand, the second buffer 12 is provided between the download microcomputer 10 and the timing generation circuit 16 and is enabled when the instruction code and data sent from the external computer system 102 are stored in the SRAM 13. . The second buffer 12 is disabled when the memory emulation device 100 supplies an instruction code or data to the target board 101.

The SRAM 13 is a randomly accessible semiconductor memory device that allows the download microcomputer 10 to store instruction codes and data received from an external computer system 102 so that it can be read by the target board 101. That is, SRAM
13 is a socket 21 provided in the target board 101
In place of the non-volatile memory mounted on the target board 101, an instruction code or data corresponding to an address signal or a control signal sent from the microcomputer 20 of the target board 101 is supplied.

The mode setting switch 14 is connected to the SRAM 13
This is for setting a read mode when reading the instruction code or data stored in the. That is, the mode setting switch 14 changes the read mode of the instruction code or the data stored in the SRAM 13 to the synchronous burst read mode in response to, for example, a manual switch by the user or a read mode designating signal supplied from the outside. , Or asynchronous page read mode. Here, the synchronous burst read mode is an operation mode in which an instruction code or data stored in the SRAM 13 is read in synchronization with a CLK1 signal which is a clock signal supplied from the target board 101. Also, the asynchronous page read mode is
Each time the address signal supplied from the target board 101 is switched, the read position of the stored data in the SRAM 13 is changed, and the data signal is output with a delay of a predetermined read delay time from the input of the address signal. This is an operation mode in which reading is performed in synchronization with an address signal.

The burst size setting switch 15 is for setting the size of a transfer data unit when the reading mode is set to the synchronous burst reading mode by the mode setting switch 14. At this time, the burst size setting switch 15 sets the size of the transfer data unit in accordance with, for example, a manual setting by the user or a size designation signal supplied from the outside.

The timing generation circuit 16 is for adjusting the input timing of various signals sent from the target board 101 when the target board 101 reads out instruction codes and data stored in the SRAM 13. As shown in FIG. 2, the timing generation circuit 16 includes a synchronous timing generation circuit 30 provided in parallel.
And an asynchronous timing generation circuit 31 and an AND gate band 32 for selecting a signal to be supplied to the SRAM 13.

The synchronous timing generation circuit 30 outputs a signal for reading out an instruction code or data stored in the SRAM 13 in response to a case where the read mode set by the mode setting switch 14 is a synchronous burst read mode. It is for doing. As shown in FIG. 3, the synchronization timing generation circuit 30
, An address generation counter 41 and an address selector 42.

The clock generation circuit 40 generates a CLK2 signal, which is a clock signal, according to a control signal sent from the target board 101. In other words, the clock generation circuit 40, for example, activates an ADV (ADdress Vali
d), a control signal including a CS (Chip Select) signal indicating the selected memory chip, a READ signal for validating the data output signal of the SRAM 13, and a CLK1 signal as a clock signal. These control signals are sent from the target board 101 via the first buffer 11, the flat cable 17, and the connector 18. The clock generation circuit 40 receiving the control signal generates a CLK2 signal which is a clock signal having a burst size (size of transfer data unit) set by the burst size setting switch 15.
The CLK2 signal generated by the clock generation circuit 40 is sent to the address generation counter 41.

The address generation counter 41 is a counting circuit that counts up in response to a change in the logic level of the CLK2 signal received from the clock generation circuit 40, for example.
It detects and counts the rising edge of the signal. The count value of the address generation counter 41 is sent to the address selector 42 as a lower address among addresses indicating the read position of the instruction code and data stored in the SRAM 13.

The address selector 42 is for selecting and outputting either the address signal indicating the upper address supplied from the target board 101 or the signal indicating the lower address sent from the address generation counter 41. . That is, the address selector 42
When the read mode set by the mode setting switch 14 is the synchronous burst read mode, one of the upper address signal and the lower address signal is selected and output. At this time, the address selector 42 outputs a control signal such as a CS signal or a READ signal sent from the target board 101 in synchronization with the selected address signal, so that the instruction code and data can be read from the SRAM 13. I do. The address signal and control signal output from the address selector 42 are sent to the AND gate band 32. When the read mode set by the mode setting switch 14 is the asynchronous page read mode, the address selector 42 sets the logic levels of the address signal and the control signals such as the CS signal and the READ signal to “Hi”, Send to AND gate zone 32.

The asynchronous timing generation circuit 31 shown in FIG.
Corresponds to the case where the read mode set by the mode setting switch 14 is the asynchronous page read mode,
This is for outputting a signal for reading out an instruction code or data stored in the RAM 13. For example,
As shown in FIG. 4, the asynchronous timing generation circuit 31
An address selector 43 is provided.

When the read mode set by the mode setting switch 14 is the asynchronous page read mode, the address selector 43 outputs an address signal supplied from the target board 101 and control signals such as a CS signal and a READ signal. . Also, the address selector 43
When the read mode set by the mode setting switch 14 is the synchronous burst read mode, the logic levels of the address signal and the control signal such as the CS signal and the READ signal are set to “Hi”, and the AND gate band 32 send.

The AND gate band 32 receives an address signal and a control signal from the synchronous timing generation circuit 30 and the asynchronous timing generation circuit 31, takes the logical product of the signals, and performs an AND operation.
The data is supplied to the RAM 13.

The flat cable 17 shown in FIG.
This is a cable for connecting between the buffer 11 and the connector 18, and sends an address signal and a control signal sent from the target board 101 to the first buffer 11.
The instruction code and data read from the RAM 13 are supplied to the connector 18.

The connector 18 is connected to the target board 101
The memory emulation device 100 is connected to the target board 101 by being fitted into a socket 21 for mounting a nonvolatile memory such as a ROM or a flash memory.

The operation of the memory emulation device 100 according to the embodiment of the present invention will be described below.

This memory emulation device 100
Is an apparatus for storing instruction codes and data received from an external computer system 102 in the SRAM 13 and supplying the instruction codes and data to the target board 101 in response to address signals and control signals sent from the target board 101.

Here, the memory emulation device 10
By changing the mode setting switch 14 to 0, the operation characteristics can be changed in accordance with the data reading operation on the target board 101.

That is, the mode setting switch 14 synchronizes the read mode of the instruction code or data stored in the SRAM 13 in response to, for example, a manual switching operation by a user or a read mode designation signal supplied from the outside. Set to either the burst read mode or the asynchronous page read mode.

The timing generation circuit 16 exclusively sets the synchronous timing generation circuit 30 and the asynchronous timing generation circuit 31 to active / inactive in accordance with the read mode set by the mode setting switch 14. That is, when the read mode set by the mode setting switch 14 is the synchronous burst read mode, the timing generation circuit 16
0 is set to active, and the asynchronous timing generation circuit 3
Set 1 to inactive. Further, when the read mode set by the mode setting switch 14 is the asynchronous page read mode, the timing generation circuit 16 sets the synchronous timing generation circuit 30 to inactive and sets the asynchronous timing generation circuit 31 to active. .

The operation when the read mode set by the mode setting switch 14 is the synchronous burst read mode will be described below.

The synchronous timing generation circuit 30 is activated when the read mode set by the mode setting switch 14 is the synchronous burst read mode, and the clock generation circuit 40 follows the control signal sent from the target board 101. A CLK2 signal, which is a clock signal, is generated. For example, the clock generation circuit 40 generates the CLK2 signal by passing the CLK1 signal, which is the clock signal transmitted from the target board 101, by an amount corresponding to the burst size specified by the burst size setting switch 15. The clock generation circuit 40 sends the generated CLK2 signal to the address generation counter 41.

The address generation counter 41 generates a lower address of a bit number corresponding to the size of the transfer data unit, for example, by counting the CLK2 signal sent from the clock generation circuit 40. For example, the address generation counter 41 functions as a 3-bit counting counter, thereby defining a 3-bit lower address among addresses that define a read position of an instruction code or data stored in the SRAM 13 and an 8-word address. Enables burst reading. The address generation counter 41 sends a signal indicating the lower address to the address selector 42.

Since the read mode set by the mode setting switch 14 is the synchronous burst read mode, the address selector 42 receives the address signal indicating the upper address sent from the target board 101 and the address signal sent from the address generation counter 41. And selects and outputs one of the signals indicating the lower address.
Send to The address selector 42 outputs a control signal such as a CS signal or a READ signal sent from the target board 101 and sends the control signal to the AND gate band 32.

On the other hand, the asynchronous timing generation circuit 31
Since the read mode set by the mode setting switch 14 is the synchronous burst read mode, it becomes inactive, and the logic levels of the address signal and the control signal such as the CS signal and the READ signal are set to “Hi”, and the AND gate band is set. Send to 32.

Since the logical levels of the address signal and the control signal sent from the asynchronous timing generation circuit 31 are "Hi", the AND gate band 32 applies the address signal and the control signal sent from the synchronous timing generation circuit 30 to each other. After passing through, it is supplied to the SRAM 13. That is, AN
The D gate band 32 selects the address signal and the control signal sent from the synchronous timing generation circuit 30 because the logic levels of the address signal and the control signal are set to “Hi” when the asynchronous timing generation circuit 31 is inactive. Then, the data is supplied to the SRAM 13.

FIG. 5 is a timing chart illustrating a read cycle when the read mode is the synchronous burst read mode. As shown in the figure, in the synchronous burst read mode, an address signal sent from the target board 101 is input to the SRAM 13 and a predetermined read delay time t
After the lapse of _D1 , the data signal is synchronized with the CLK1 signal.
The stored data is read by DATA. Data signal DATA
Is supplied to the target board 101 via the first buffer 11, the flat cable 17, and the connector 18. As a result, in the synchronous burst read mode, the SRAM 1
3 can be read and supplied to the target board 101.

Next, the operation when the operation mode set by the mode setting switch 14 is the asynchronous page read mode will be described.

The asynchronous timing generation circuit 31 becomes active when the read mode set by the mode setting switch 14 is the asynchronous page read mode, and the address selector 43 outputs the address signal and the CS signal transmitted from the target board 101. And a control signal such as a READ signal is sent to the AND gate band 32.

On the other hand, the synchronous timing generation circuit 30 becomes inactive because the read mode set by the mode setting switch 14 is the asynchronous page read mode, and the logic of the address signal and the control signal such as the CS signal and the READ signal is changed. The level is set to “Hi” and sent to the AND gate band 32.

Since the logical levels of the address signal and the control signal sent from the synchronous timing generation circuit 30 are “Hi”, the AND gate band 32 transmits the address signal and the control signal sent from the asynchronous timing generation circuit 31. After passing through, it is supplied to the SRAM 13. That is, AN
The D gate band 32 selects the address signal and the control signal sent from the asynchronous timing generation circuit 31 because the logic levels of the address signal and the control signal are set to “Hi” when the synchronous timing generation circuit 30 is inactive. Then, the data is supplied to the SRAM 13.

FIG. 6 is a timing chart illustrating a read cycle when the read mode is the asynchronous page read mode. As shown, in the asynchronous page read mode, an address signal sent from the target board 101 is input to the SRAM 13 and a predetermined read delay time T
After the lapse of _D2 , in synchronization with the change of the address signal,
The stored data is read by the data signal DATA. The data signal DATA is transmitted to the target board 101 via the first buffer 11, the flat cable 17, and the connector 18.
Supplied to As a result, the instruction code and data stored in the SRAM 13 can be read out in the asynchronous page read mode and supplied to the target board 101.

As described above, the AND gate band 32 selects the signal output from either the synchronous timing generation circuit 30 or the asynchronous timing generation circuit 31, and
M13. Here, the synchronization timing generation circuit 3
0 outputs a signal corresponding to a synchronous burst read mode in which data stored in the SRAM 13 is burst read in synchronization with a clock signal. Further, the asynchronous timing generation circuit 31 outputs a signal corresponding to an asynchronous page read mode in which data stored in the SRAM 13 is page-read asynchronously with a clock signal. As a result, data stored in the SRAM 13 can be read corresponding to the synchronous burst read mode or the asynchronous page read mode, and the operation characteristics can be changed in accordance with the data read operation on the target board.

As described above, according to the present invention,
According to the read mode set by the mode setting switch 14, one of the synchronous timing generation circuit 30 and the asynchronous timing generation circuit 31 is operated to enable the target board 101 to read an instruction code or data. Thereby, even when the read mode of the target board 101 is the synchronous burst read mode or the asynchronous page read mode, the SRAM is set in accordance with the read mode.
13 can be read, and the operation of the target board 101 can be more strictly verified.

In the above-described embodiment, the case of operating in the synchronous burst read mode and the asynchronous page read mode has been described. However, the present invention is not limited to this, and it is possible to set a conventional random access read mode. Is also good.

[0052]

According to the present invention, the operating characteristics can be changed in accordance with the data reading operation on the target board.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory emulation device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a timing generation circuit.

FIG. 3 is a diagram illustrating a configuration of a synchronization timing generation circuit.

FIG. 4 is a diagram illustrating a configuration of an asynchronous timing generation circuit.

FIG. 5 is a timing chart illustrating a read cycle when the read mode is a synchronous burst read mode.

FIG. 6 is a timing chart illustrating a read cycle when the read mode is an asynchronous page read mode.

FIG. 7 is a diagram showing a configuration of a conventional memory emulation device.

[Explanation of symbols]

 10, 50 Download microcomputer 11, 12, 51, 52 Buffer 13, 53 SRAM 14 Mode setting switch 15 Burst size setting switch 16 Timing generation circuit 17, 54 Flat cable 18, 55 Connector 20, 60 Microcomputer 21, 61 Socket 30 Synchronization Timing generation circuit 31 Asynchronous timing generation circuit 32 AND gate band 40 Clock generation circuit 41 Address generation counter 42, 43 Address selector 100, 200 Memory emulation device 101, 201 Target board 102, 202 Computer system

Claims (5)

[Claims] 1. A memory emulation device for supplying data for verifying the operation of a target board to a target board, wherein the memory emulation device is a random access memory, and is stored in the storage in synchronization with a clock signal. A first signal output means for outputting a signal corresponding to a synchronous burst read mode for burst reading data stored therein, and an asynchronous page read mode for page reading data stored in the storage means asynchronously with a clock signal. A second signal output unit that outputs a signal; and a signal output from any one of the first and second signal output units selected and supplied to the storage unit, thereby storing the signal in the storage unit. And selecting and supplying means for reading out the data stored in the memory and supplying the data to the target board. Configuration equipment. 2. A method according to claim 1, further comprising mode setting means for switching between a synchronous burst read mode and an asynchronous page read mode for setting, wherein said first signal output means sets a read mode set by said mode setting means to a synchronous burst read mode. And outputting a signal based on the address signal and the control signal sent from the target board, wherein the second signal output means is a read mode set by the mode setting means is an asynchronous page read mode. And outputting a signal based on the address signal and the control signal sent from the target board, wherein the selecting and supplying unit is configured to output the signal when the read mode set by the mode setting unit is a synchronous burst read mode. The signal output from the first signal output means is selected and supplied to the storage means. 2. The method according to claim 1, wherein when the set read mode is an asynchronous page read mode, a signal output from the second signal output unit is selected and supplied to the storage unit. Memory emulation device. 3. The apparatus according to claim 1, further comprising: a burst size setting unit configured to set a size of a transfer data unit when the read mode set by the mode setting unit is a synchronous burst read mode. When the read mode set by the setting means is a synchronous burst read mode, an address signal corresponding to the size of the transfer data unit set by the burst size setting means is generated and output. Item 3. The memory emulation device according to item 1 or 2. 4. A clock signal generating means for generating a clock signal having a size of a transfer data unit set by the burst size setting means, and a clock signal generated by the clock generating means. And an address signal output unit that outputs an address signal with the count value of the clock signal in the count unit as a lower address and sends the address signal to the selection and supply unit. The memory emulation device according to claim 3, comprising: 5. A storage means which can be randomly accessed;
And a data supply method for supplying data to a target board by a memory emulation device including a second signal output unit, a signal selection unit, and a mode setting unit, wherein the mode setting unit is synchronized with a clock signal. A mode setting step of switching between a synchronous burst read mode for performing burst read and an asynchronous page read mode for performing page read asynchronously with a clock signal to set a read mode of data stored in the storage means; The signal output means outputs a signal based on an address signal and a control signal sent from the target board when the read mode set by the mode setting means in the mode setting step is a synchronous burst read mode. A first signal output step of performing A second signal output step of outputting a signal based on the address signal and the control signal sent from the target board when the read mode set by the mode setting means in the mode setting step is the asynchronous page read mode; The signal selecting means, when the read mode set by the mode setting means in the mode setting step is a synchronous burst read mode, by the first signal output means in the first signal output step; The output signal is selected and supplied to the storage means. When the read mode set by the mode setting means in the mode setting step is an asynchronous page read mode, the second signal output step By selecting the signal output by the second signal output means and supplying it to the storage means, And a selection supply step of supplying to the target board reads the data stored in the unit, data supply wherein the.