JP2002305217A - Pad structure for semiconductor device and production method therefor - Google Patents

Pad structure for semiconductor device and production method therefor

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Publication number
JP2002305217A
JP2002305217A JP2001107952A JP2001107952A JP2002305217A JP 2002305217 A JP2002305217 A JP 2002305217A JP 2001107952 A JP2001107952 A JP 2001107952A JP 2001107952 A JP2001107952 A JP 2001107952A JP 2002305217 A JP2002305217 A JP 2002305217A
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JP
Japan
Prior art keywords
pad
layer
semiconductor device
pattern
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001107952A
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Japanese (ja)
Inventor
Hirobumi Kobayashi
博文 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2001107952A priority Critical patent/JP2002305217A/en
Publication of JP2002305217A publication Critical patent/JP2002305217A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To provide a pad structure for semiconductor device and a production method therefor, with which highly reliable bond lift measures are taken onto a pad surface. SOLUTION: An electrode pad PAD is a practical alminium layer 11 connected with an internal conductive region, formed on a layer insulating film 10, such as SiO2 film and configured to be exposed on the opening part of a passivation film 12 of the top layer. A bonding wire not shown is connected to the electrode pad PAD, for example. The pattern exposure plane of the electrode pad PAD is configured, while having a rugged form by being reflected with a rugged pattern 101 formed on a layer insulating film 10 of the lower layer. Because of the rugged form, the connection area of the bonding wire is expanded. Further, the contact area of the alminium layer 11 and the layer insulating film 10 is increased due to the rugged pattern 101.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置におけ
る外部接続用のパッド形成に係り、特にボンディングワ
イヤまたはバンプが接続される半導体装置のパッド構造
及びその製造方法に関する。The present invention relates to the formation of pads for external connection in a semiconductor device, and more particularly to a pad structure of a semiconductor device to which bonding wires or bumps are connected and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】半導体装置における外部接続用のパッド
は、接続されるボンディングワイヤやバンプ等の電気的
接続の安定性を得るため、また高抵抗化を避けるため
に、配線部材として適当な材料を選びつつある程度の大
きさを確保しなければならない。かつ、各種応力、衝撃
によって剥離するのを防止するために、下地の絶縁層と
密着性のよい材料で構成される必要がある。2. Description of the Related Art A pad for external connection in a semiconductor device is made of an appropriate material as a wiring member in order to obtain stability of electrical connection such as bonding wires and bumps to be connected and to avoid high resistance. You must secure a certain size while choosing. Further, in order to prevent peeling due to various stresses and impacts, it is necessary to be made of a material having good adhesion to the underlying insulating layer.

【０００３】図５は、半導体装置における従来のパッド
構造の構成を示す断面図である。図示しない内部の導電
領域と接続されるパッドの配線層構造は、一般にＢＰＳ
Ｇ（ボロン・リン珪化ガラス）膜やＳｉＯ2膜などの層
間絶縁膜５０上に形成され、最上層のパッシベーション
膜５４の開口部に構成されている。FIG. 5 is a sectional view showing a configuration of a conventional pad structure in a semiconductor device. A wiring layer structure of a pad connected to an internal conductive region (not shown) generally has a BPS
It is formed on an interlayer insulating film 50 such as a G (boron / phosphosilicide glass) film or a SiO 2 film, and is formed in an opening of the uppermost passivation film 54.

【０００４】アルミニウム層５３は、例えばＳｉＯ2膜
でなる層間絶縁膜５０上にバリアメタルとしてＴｉ層５
１／ＴｉＮ層５２の積層が形成され、その上に実質的な
アルミニウム層５３が形成されている、例えばＣｕを１
％未満（例えば０．５％）含有させたＡｌ−Ｃｕ構造と
している。An aluminum layer 53 is formed on an interlayer insulating film 50 made of, for example, a SiO 2 film by using a Ti layer 5 as a barrier metal.
1 / TiN layer 52 is formed thereon, and a substantial aluminum layer 53 is formed thereon.
% (For example, 0.5%).

【０００５】上記パッシベーション膜５４の開口部に構
成されたアルミニウム層５３の電極パッドＰＡＤには、
例えば図示しないボンディングワイヤが接続される。Ｔ
ｉ層５１／ＴｉＮ層５２の積層は、下地との密着性、バ
リア性が考慮されて設けられている。ＴｉＮ層５２は、
アルミニウム層５３のＡｌと素子のＳｉとの反応を抑制
する働きを有する。また、アルミニウム層５３とＴｉ層
５１は、間のＴｉＮ層５２によってＡｌとＴｉの反応が
抑制される。The electrode pad PAD of the aluminum layer 53 formed in the opening of the passivation film 54 has:
For example, a bonding wire (not shown) is connected. T
The lamination of the i-layer 51 / TiN layer 52 is provided in consideration of adhesion to the base and barrier properties. The TiN layer 52 is
It has a function of suppressing a reaction between Al of the aluminum layer 53 and Si of the element. In addition, the reaction between Al and Ti is suppressed by the TiN layer 52 between the aluminum layer 53 and the Ti layer 51.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、上記構
成では、下地のＳｉＯ2膜などの層間絶縁膜５０とＴｉ
層５１は、反応してＴｉＯ2層を形成し、密着性を劣化
させることが知られている。そこで、パッド強度を低下
させる構造になってしまうのを防ぐため、パッド部にお
けるＴｉ層５１／ＴｉＮ層５２の除去を対策することが
ある。しかし、このバリアメタルの除去は、層間の密着
性のみに着目している対策である。よって、未だなおボ
ンディングワイヤの剥離の懸念（ボンド・リフト強度の
低下）がある。However, in the above structure, the interlayer insulating film 50 such as an underlying SiO 2 film is
It is known that layer 51 reacts to form a TiO 2 layer, which degrades adhesion. Therefore, in order to prevent a structure in which the pad strength is reduced, a measure may be taken to remove the Ti layer 51 / TiN layer 52 in the pad portion. However, the removal of the barrier metal is a measure that focuses only on the adhesion between the layers. Therefore, there is still a fear of peeling of the bonding wire (reduction in bond lift strength).

【０００７】本発明は上記のような事情を考慮してなさ
れたもので、パッド表面に対して高信頼性のボンド・リ
フト対策を講じた半導体装置のパッド構造及びその製造
方法を提供しようとするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pad structure of a semiconductor device in which a highly reliable bond lift countermeasure is taken on the pad surface and a method of manufacturing the same. Things.

【０００８】[0008]

【課題を解決するための手段】本発明に係る半導体装置
のパッド構造は、半導体集積回路における絶縁膜上に設
けられた金属配線の端部であって、周辺が保護膜に囲ま
れた前記金属配線のパッドパターンとしての露出面が、
より下層に積極的に形成された凹凸を反映した凹凸面で
構成されていることを特徴とする。According to the present invention, there is provided a pad structure of a semiconductor device, comprising: a metal structure provided on an insulating film in a semiconductor integrated circuit; The exposed surface as the wiring pad pattern
It is characterized in that it is constituted by an uneven surface reflecting the unevenness actively formed in the lower layer.

【０００９】上記本発明に係る半導体装置のパッド構造
によれば、金属配線の露出面すなわちパッド表面が、よ
り下層において積極的に形成された凹凸を反映した凹凸
面で構成される。これにより、ボンディングワイヤ等パ
ッドに接触する部材の密着性向上に寄与する。According to the pad structure of the semiconductor device according to the present invention, the exposed surface of the metal wiring, that is, the pad surface is constituted by an uneven surface reflecting the unevenness formed more actively in the lower layer. This contributes to improving the adhesion of a member that contacts the pad such as a bonding wire.

【００１０】本発明に係るより好ましい実施態様として
の半導体装置のパッド構造は、半導体集積回路における
絶縁膜上に設けられた金属配線の端部であって、周辺が
保護膜に囲まれた前記金属配線のパッドパターンの露出
面が、より下層に存在する凹凸を有する絶縁層または導
電層の表面形状を反映した凹凸面で構成されていること
を特徴とする。[0010] A pad structure of a semiconductor device according to a more preferred embodiment of the present invention is the pad structure of the semiconductor integrated circuit, wherein the metal wiring is provided at an end of a metal wiring provided on an insulating film, and the periphery of the metal wiring is surrounded by a protective film. The exposed surface of the pad pattern of the wiring is constituted by an uneven surface which reflects the surface shape of an insulating layer or a conductive layer having an unevenness existing in a lower layer.

【００１１】上記本発明に係る半導体装置のパッド構造
によれば、金属配線の露出面すなわちパッド表面が、よ
り下層に形成された絶縁層または導電層の凹凸形状を反
映した凹凸面で構成される。これにより、ボンディング
ワイヤ等パッドに接触する部材の密着性向上に寄与す
る。According to the pad structure of the semiconductor device according to the present invention, the exposed surface of the metal wiring, that is, the pad surface is constituted by the uneven surface reflecting the uneven shape of the insulating layer or the conductive layer formed below. . This contributes to improving the adhesion of a member that contacts the pad such as a bonding wire.

【００１２】また、上記半導体装置のパッド構造におい
て、絶縁層または導電層は、少なくとも次のうち一つの
構成による凹凸形状を反映して構成されることを特徴と
する。第１に、上記半導体集積回路における基板上の選
択酸化による凹凸、第２に、上記半導体集積回路におけ
るゲートポリシリコン形成時のパターニングによる凹
凸、第３に、上記半導体集積回路におけるプラグ金属を
選択的にパターニングした凹凸の形状。Further, in the above-mentioned pad structure of the semiconductor device, the insulating layer or the conductive layer is characterized by reflecting at least one of the following structures. First, the unevenness due to the selective oxidation on the substrate in the semiconductor integrated circuit, second, the unevenness due to the patterning in forming the gate polysilicon in the semiconductor integrated circuit, and third, the plug metal in the semiconductor integrated circuit is selectively formed. Concavo-convex shape patterned into a pattern.

【００１３】本発明に係る半導体装置のパッド構造の製
造方法は、半導体集積回路における絶縁膜上に設けられ
る金属配線の端部の製造に関するものであって、前記金
属配線のパッドパターン形成予定領域における下層とな
るべき絶縁層または導電層のうち少なくともいずれか一
層に対し、リソグラフィ技術を用いて凹凸パターンを積
極的に形成する工程を付与し、実際に周辺が保護膜に囲
まれた金属配線のパッドパターンとしての露出面が、下
層の凹凸を反映した凹凸面を形成することを特徴とす
る。A method of manufacturing a pad structure of a semiconductor device according to the present invention relates to a method of manufacturing an end portion of a metal wiring provided on an insulating film in a semiconductor integrated circuit. At least one of an insulating layer and a conductive layer to be a lower layer is provided with a step of positively forming a concavo-convex pattern by using a lithography technique, and a pad of a metal wiring whose periphery is actually surrounded by a protective film. It is characterized in that the exposed surface as a pattern forms an uneven surface reflecting the unevenness of the lower layer.

【００１４】上記本発明に係る半導体装置のパッド構造
の製造方法によれば、上記リソグラフィ技術は、半導体
集積回路に必要な絶縁層または導電層をそれぞれパター
ニングするいずれかのリソグラフィ技術の共有で達成で
きる。これにより、工数を増やさずに凹凸面を有するパ
ッド構造が形成できる。According to the method of manufacturing a pad structure of a semiconductor device according to the present invention, the lithography technique can be achieved by sharing one of the lithography techniques for patterning an insulating layer or a conductive layer required for a semiconductor integrated circuit. . Thus, a pad structure having an uneven surface can be formed without increasing the number of steps.

【００１５】[0015]

【発明の実施の形態】図１は、本発明の第１実施形態に
係る半導体装置のパッド構造の構成を示す断面図であ
る。図示しない内部の導電領域と接続されるパッドの配
線層構造は、一般にＢＰＳＧ（ボロン・リン珪化ガラ
ス）膜やＳｉＯ2膜などの層間絶縁膜１０上に形成され
る。FIG. 1 is a sectional view showing a structure of a pad structure of a semiconductor device according to a first embodiment of the present invention. A wiring layer structure of a pad connected to an internal conductive region (not shown) is generally formed on an interlayer insulating film 10 such as a BPSG (boron / phosphorus silicide glass) film or a SiO 2 film.

【００１６】例えば、ＳｉＯ2膜でなる層間絶縁膜１０
上に形成される金属配線の端部つまり電極パッドＰＡＤ
は、最上層のパッシベーション膜１２の開口部に構成さ
れている。電極パッドＰＡＤは、実質的なアルミニウム
層１１で形成されている、アルミニウム層１１は、例え
ばＣｕを１％未満（例えば０．５％）含有させたＡｌ−
Ｃｕ構造としている。For example, an interlayer insulating film 10 made of a SiO 2 film
End of metal wiring formed on top, ie, electrode pad PAD
Are formed in the openings of the uppermost passivation film 12. The electrode pad PAD is formed of a substantial aluminum layer 11. The aluminum layer 11 is made of, for example, Al- containing less than 1% of Cu (for example, 0.5%).
It has a Cu structure.

【００１７】アルミニウム層１１の下地にはバリアメタ
ルとしてＴｉ層／ＴｉＮ層の積層が形成されるが、電極
パッドＰＡＤ形成領域上に関しては、このＴｉ層／Ｔｉ
Ｎ層の積層が除去されている。A laminate of a Ti layer / TiN layer is formed as a barrier metal under the aluminum layer 11, but the Ti layer / TiN layer is formed on the electrode pad PAD formation region.
The stack of N layers has been removed.

【００１８】この実施形態では、電極パッドＰＡＤのパ
ターン露出面が、下層の層間絶縁膜１０に形成された凹
凸パターン１０１を反映して凹凸形状を有して構成され
ている。これにより、電極パッドＰＡＤ表面に接触する
ボンディングワイヤ等の接続面積は増大し密着性向上に
寄与する。また、凹凸パターン１０１によってアルミニ
ウム層１１と層間絶縁膜１０との接触面積を増大させ密
着性をより強固なものとしている。これにより、高信頼
性のボンド・リフト対策が達成できる。In this embodiment, the pattern-exposed surface of the electrode pad PAD has an uneven shape reflecting the uneven pattern 101 formed on the lower interlayer insulating film 10. As a result, the connection area of the bonding wire or the like in contact with the surface of the electrode pad PAD increases, which contributes to the improvement of the adhesion. Further, the contact area between the aluminum layer 11 and the interlayer insulating film 10 is increased by the concavo-convex pattern 101, and the adhesion is further strengthened. Thereby, a highly reliable bond lift measure can be achieved.

【００１９】上記図１の構成における層間絶縁膜１０へ
の凹凸パターンの付与は、層間絶縁膜１０下の図示しな
いさらに下層の層間絶縁膜における下層配線とのコンタ
クト部の開口で実施するフォトリソグラフィ工程を利用
して形成する。あるいは、初期のフィールド絶縁膜形成
時、電極パッドＰＡＤのパターン形成予定領域において
予め凹凸を有するような選択酸化を実施しておくことも
考えられる（図示せず）。これにより、実質的なアルミ
ニウム層１１をスパッタ形成する時、下層の凹凸形状を
反映し、凹凸面で構成される。The provision of the concavo-convex pattern on the interlayer insulating film 10 in the structure shown in FIG. It is formed by utilizing. Alternatively, at the time of initial formation of the field insulating film, it is conceivable to carry out selective oxidation such that the pattern formation region of the electrode pad PAD has irregularities in advance (not shown). Thus, when the substantial aluminum layer 11 is formed by sputtering, the aluminum layer 11 has an uneven surface, reflecting the uneven shape of the lower layer.

【００２０】図２は、本発明の第２実施形態に係る半導
体装置のパッド構造の構成を示す断面図である。図１と
同様の箇所には同一の符号を付す。前記第１実施形態に
比べて、電極パッドＰＡＤのへの凹凸パターンが、ゲー
トポリシリコン形成時のパターニングによる凹凸を反映
して構成されていることを明示している。これにより、
層間絶縁膜１０の凹凸パターン１０１となり、電極パッ
ドＰＡＤのパターン露出面が、凹凸形状を反映し構成さ
れている。FIG. 2 is a sectional view showing the structure of a pad structure of a semiconductor device according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals. Compared to the first embodiment, it is clearly shown that the uneven pattern on the electrode pad PAD reflects the unevenness due to the patterning at the time of forming the gate polysilicon. This allows
The pattern becomes the uneven pattern 101 of the interlayer insulating film 10, and the pattern exposed surface of the electrode pad PAD reflects the uneven shape.

【００２１】図２によれば、ゲートポリシリコン形成時
のリソグラフィ工程により、電極パッドＰＡＤのパター
ン形成予定領域においてポリシリコン層２１をパターニ
ングしておく。これにより、その上に積層される層間絶
縁膜１０に凹凸パターン１０１を付与する。これによ
り、実質的なアルミニウム層１１をスパッタ形成する
時、下層の凹凸形状を反映し、電極パッドＰＡＤのパタ
ーン露出面が、凹凸形状を反映することになる。Referring to FIG. 2, a polysilicon layer 21 is patterned in a region where a pattern of an electrode pad PAD is to be formed by a lithography process when forming gate polysilicon. Thereby, the concavo-convex pattern 101 is given to the interlayer insulating film 10 laminated thereon. Accordingly, when the substantial aluminum layer 11 is formed by sputtering, the uneven shape of the lower layer is reflected, and the pattern exposed surface of the electrode pad PAD reflects the uneven shape.

【００２２】上記第２実施形態によっても、凹凸形状を
有する電極パッドＰＡＤは、その表面に接触するボンデ
ィングワイヤ等の密着性向上に寄与する。また、凹凸パ
ターン１０１によってアルミニウム層１１と層間絶縁膜
１０との接触面積を増大させ密着性をより強固なものと
している。これにより、高信頼性のボンド・リフト対策
が達成できる。According to the second embodiment as well, the electrode pad PAD having the uneven shape contributes to the improvement of the adhesion of the bonding wire or the like in contact with the surface. Further, the contact area between the aluminum layer 11 and the interlayer insulating film 10 is increased by the concavo-convex pattern 101, and the adhesion is further strengthened. Thereby, a highly reliable bond lift measure can be achieved.

【００２３】図３は、本発明の第３実施形態に係る半導
体装置のパッド構造の構成を示す断面図である。図１と
同様の箇所には同一の符号を付す。前記第１実施形態に
比べて、電極パッドＰＡＤのへの凹凸パターンが、プラ
グ金属を選択的にパターニングした凹凸を反映して構成
されていることを明示している。これにより、電極パッ
ドＰＡＤのパターン露出面が、凹凸形状を反映し構成さ
れている。FIG. 3 is a cross-sectional view showing a configuration of a pad structure of a semiconductor device according to a third embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals. Compared with the first embodiment, it is clearly shown that the uneven pattern on the electrode pad PAD reflects the unevenness obtained by selectively patterning the plug metal. Thereby, the exposed surface of the pattern of the electrode pad PAD reflects the uneven shape.

【００２４】図３によれば、層間絶縁膜３０に図示しな
い下層の配線層と接続するＷ（タングステン）等、プラ
グ金属でビアを形成する際、ドライエッチ及びエッチバ
ックを伴う。このパターニング工程で、電極パッドＰＡ
Ｄのパターン形成予定領域においてプラグ金属層３１を
パターニングしておく。これにより、実質的なアルミニ
ウム層１１をスパッタ形成する時、下層の凹凸形状を反
映し、電極パッドＰＡＤのパターン露出面が、凹凸形状
を反映することになる。Referring to FIG. 3, when a via is formed with a plug metal such as W (tungsten) connected to a lower wiring layer (not shown) in the interlayer insulating film 30, dry etching and etch back are involved. In this patterning step, the electrode pad PA
The plug metal layer 31 is patterned in the region where the pattern D is to be formed. Accordingly, when the substantial aluminum layer 11 is formed by sputtering, the uneven shape of the lower layer is reflected, and the pattern exposed surface of the electrode pad PAD reflects the uneven shape.

【００２５】上記第３実施形態によっても、凹凸形状を
有する電極パッドＰＡＤは、その表面に接触するボンデ
ィングワイヤ等の密着性向上に寄与する。また、プラグ
金属層３１の凹凸パターンによってアルミニウム層１１
との接触面積を増大させ密着性は向上する。これによ
り、高信頼性のボンド・リフト対策が達成できる。According to the third embodiment as well, the electrode pad PAD having the uneven shape contributes to the improvement of the adhesion of the bonding wire or the like in contact with the surface. Also, the aluminum layer 11 is formed by the uneven pattern of the plug metal layer 31.
The contact area is increased, and the adhesion is improved. Thereby, a highly reliable bond lift measure can be achieved.

【００２６】図４（ａ），（ｂ）は、それぞれ上記各実
施形態によって構成される電極パッドＰＡＤのパターン
例を示す平面図である。各図中、例えば斜線部分が凸部
で構成されるものとする。FIGS. 4A and 4B are plan views showing examples of patterns of the electrode pads PAD constituted by the above embodiments. In each drawing, for example, it is assumed that a hatched portion is formed of a convex portion.

【００２７】このように各実施形態によれば、電極パッ
ドＰＡＤの表面が、電極パッドより下層において積極的
に形成される凹凸を反映し、凹凸面で構成される。これ
により、ボンディングワイヤ等パッドに接触する部材の
密着性向上に寄与する。また、電極パッドより下層にお
いて積極的に形成される凹凸が層間の密着性を良好なも
のとする。これにより、その後に接続されるボンディン
グワイヤ（またはバンプ電極）の接触面積を増大させ密
着性を良好にする。特に、ボンディングワイヤの接続の
衝撃、剥離に強くなる。なお、上記各実施形態ではパッ
ド構造の配線層下にバリアメタルは設けなかったが、層
間の密着性に対して強度がとれるなら下地のバリアメタ
ルを選択的に除去しないで置いてもかまわない。As described above, according to each of the embodiments, the surface of the electrode pad PAD is formed of an uneven surface, reflecting the unevenness that is actively formed in a layer below the electrode pad. This contributes to improving the adhesion of a member that contacts the pad such as a bonding wire. In addition, the unevenness that is positively formed in the layer below the electrode pad improves the adhesion between the layers. As a result, the contact area of the bonding wire (or bump electrode) connected thereafter is increased, and the adhesion is improved. In particular, it is resistant to the impact and peeling of the bonding wire connection. In each of the above embodiments, the barrier metal is not provided under the wiring layer of the pad structure. However, if sufficient strength can be obtained for the adhesion between the layers, the barrier metal of the base may be provided without being selectively removed.

【００２８】[0028]

【発明の効果】以上説明したように、本発明によれば、
金属配線の露出面すなわちパッド表面が、より下層にお
いて積極的に形成された凹凸を反映した凹凸面で構成さ
れる。これにより、ボンディングワイヤ等パッドに接触
する部材の密着性向上に寄与する。この結果、パッド表
面におけるボンド・リフト対策に高い信頼性が得られる
半導体装置のパッド構造及びその製造方法を提供するこ
とができる。As described above, according to the present invention,
The exposed surface of the metal wiring, that is, the pad surface is constituted by an uneven surface reflecting the unevenness actively formed in the lower layer. This contributes to improving the adhesion of a member that contacts the pad such as a bonding wire. As a result, it is possible to provide a pad structure of a semiconductor device and a method of manufacturing the pad structure, which can obtain high reliability in measures against bond lift on the pad surface.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施形態に係る半導体装置のパッ
ド構造の構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a configuration of a pad structure of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第２実施形態に係る半導体装置のパッ
ド構造の構成を示す断面図である。FIG. 2 is a sectional view showing a configuration of a pad structure of a semiconductor device according to a second embodiment of the present invention.

【図３】本発明の第３実施形態に係る半導体装置のパッ
ド構造の構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a configuration of a pad structure of a semiconductor device according to a third embodiment of the present invention.

【図４】（ａ），（ｂ）は、それぞれ上記各実施形態に
よって構成される電極パッドＰＡＤのパターン例を示す
平面図である。FIGS. 4A and 4B are plan views each showing an example of a pattern of an electrode pad PAD configured according to each of the above embodiments.

【図５】半導体装置における従来のパッド構造の構成を
示す断面図である。FIG. 5 is a cross-sectional view showing a configuration of a conventional pad structure in a semiconductor device.

【符号の説明】[Explanation of symbols]

１０，３０，５０…層間絶縁膜 １１，５３…アルミニウム層 １２…パッシベーション膜 ２１…ポリシリコン層 ３１…プラグ金属、 ５１…Ｔｉ層 ５２…ＴｉＮ層 １０１…パッド下層の層間絶縁膜の凹凸パターン ＰＡＤ…電極パッド 10, 30, 50 ... interlayer insulating film 11, 53 ... aluminum layer 12 ... passivation film 21 ... polysilicon layer 31 ... plug metal, 51 ... Ti layer 52 ... TiN layer 101 ... unevenness pattern of interlayer insulating film below pad PAD ... Electrode pad

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 半導体集積回路における絶縁膜上に設け
られた金属配線の端部であって、 周辺が保護膜に囲まれた前記金属配線のパッドパターン
としての露出面が、より下層に積極的に形成された凹凸
を反映した凹凸面で構成されていることを特徴とする半
導体装置のパッド構造。1. An end portion of a metal wiring provided on an insulating film in a semiconductor integrated circuit, wherein an exposed surface as a pad pattern of the metal wiring surrounded by a protective film is more positively located in a lower layer. A pad structure for a semiconductor device, characterized in that the pad structure comprises an uneven surface reflecting the unevenness formed on the semiconductor device. 【請求項２】 半導体集積回路における絶縁膜上に設け
られた金属配線の端部であって、 周辺が保護膜に囲まれた前記金属配線のパッドパターン
の露出面が、より下層に存在する凹凸を有する絶縁層ま
たは導電層の表面形状を反映した凹凸面で構成されてい
ることを特徴とする半導体装置のパッド構造。2. An end portion of a metal wiring provided on an insulating film in a semiconductor integrated circuit, wherein an exposed surface of a pad pattern of the metal wiring surrounded by a protective film has unevenness existing in a lower layer. A pad structure for a semiconductor device, comprising a concave-convex surface reflecting the surface shape of an insulating layer or a conductive layer having the following. 【請求項３】 前記絶縁層または導電層は、少なくとも
前記半導体集積回路における層間絶縁膜に設けられた凹
凸を反映して構成されていることを特徴とする請求項２
記載の半導体装置のパッド構造。3. The semiconductor device according to claim 2, wherein the insulating layer or the conductive layer reflects at least unevenness provided on an interlayer insulating film in the semiconductor integrated circuit.
A pad structure of the semiconductor device described in the above. 【請求項４】 前記絶縁層または導電層は、少なくとも
前記半導体集積回路におけるゲートポリシリコン形成時
のパターニングによる凹凸を反映して構成されているこ
とを特徴とする請求項２記載の半導体装置のパッド構
造。4. The pad of a semiconductor device according to claim 2, wherein the insulating layer or the conductive layer reflects at least irregularities caused by patterning when forming gate polysilicon in the semiconductor integrated circuit. Construction. 【請求項５】 前記絶縁層または導電層は、少なくとも
前記半導体集積回路におけるプラグ金属を選択的にパタ
ーニングした凹凸を反映して構成されていることを特徴
とする請求項２記載の半導体装置のパッド構造。5. The pad of a semiconductor device according to claim 2, wherein the insulating layer or the conductive layer reflects at least irregularities obtained by selectively patterning a plug metal in the semiconductor integrated circuit. Construction. 【請求項６】 半導体集積回路における絶縁膜上に設け
られる金属配線の端部の製造に関するものであって、 前記金属配線のパッドパターン形成予定領域における下
層となるべき絶縁層または導電層のうち少なくともいず
れか一層に対し、リソグラフィ技術を用いて凹凸パター
ンを積極的に形成する工程を付与し、実際に周辺が保護
膜に囲まれた金属配線のパッドパターンとしての露出面
が、下層の凹凸を反映した凹凸面を形成することを特徴
とする半導体装置のパッド構造の製造方法。6. A method for manufacturing an end portion of a metal wiring provided on an insulating film in a semiconductor integrated circuit, wherein at least one of an insulating layer or a conductive layer to be a lower layer in a region where a pad pattern of the metal wiring is to be formed. A process of positively forming a concavo-convex pattern using lithography technology is applied to one of the layers, and the exposed surface of the metal wiring surrounded by the protective film as a pad pattern reflects the concavo-convex of the lower layer. A method of manufacturing a pad structure of a semiconductor device, comprising forming a roughened surface.
JP2001107952A 2001-04-06 2001-04-06 Pad structure for semiconductor device and production method therefor Withdrawn JP2002305217A (en)

Priority Applications (1)

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JP2001107952A JP2002305217A (en) 2001-04-06 2001-04-06 Pad structure for semiconductor device and production method therefor

Applications Claiming Priority (1)

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JP2001107952A JP2002305217A (en) 2001-04-06 2001-04-06 Pad structure for semiconductor device and production method therefor

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Publication Number Publication Date
JP2002305217A true JP2002305217A (en) 2002-10-18

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