JP2002304892A - Non-volatile semiconductor memory and its refreshing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which a high speed refresh function is realized at low cost. SOLUTION: A potential of a bit line is detected by bit line potential detecting circuits 21, 22 having different detection levels, a volatile cell is specified by comparing the outputs by a latch set circuit 26, the compared result is set to a latch circuit 23, and write-in operation is performed by a page program method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program having a refresh function and a program verify circuit technology in a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, flash EEPROMs have been widely used because stored information can be electrically rewritten.

Conventionally, as a method of speeding up a program operation, a data latch is provided for each bit line, and a word line 1 is provided.
A page program method is used in which main data is latched and a program and a program verify are simultaneously performed.

As a conventional example, Japanese Patent Application Laid-Open No. H11-328981
Japanese Patent Application Laid-Open Publication No. Hei 11 (1995) discloses a program / program verify circuit using such a method. This is because a latch circuit that holds program data, a transfer gate that electrically separates the latch circuit from the bit line, a bit line potential detection circuit that detects the potential of the bit line, and a latch that latches the output of the bit line potential detection circuit And a latch reset circuit for inverting the data.

In such a conventional example, at the time of programming, a selective page program is realized by applying a program voltage to a bit line by program data in a latch circuit via a transfer gate.

At the time of program verification, the potential of the bit line is detected by a bit line potential detection circuit to determine whether or not proper programming has been performed. When the proper programming is performed, the latch reset circuit is activated, rewrites the program data held in the latch circuit, and operates so as not to perform the subsequent programming. The program verify is realized by the above operation.

[0007]

The above-mentioned flash EEPROM stores and stores information by changing the threshold voltage by injecting / ejecting charges to / from the floating gate. If the charge is injected and then left as it is, there is a characteristic that the charge held in the floating gate is released. Due to this retention characteristic, when the threshold voltage decreases and becomes lower than the read determination level, there is a problem that stored information is lost.

As a method of preventing the loss of stored information due to the retention characteristics, there is a method of performing a refresh operation. In the refresh operation, first, a memory cell (hereinafter, volatile cell) that tends to lose stored information is specified. Then, writing is performed again on the memory cell.

However, when a circuit for a refresh operation is configured, conventionally, a volatile cell is specified by providing means for specifying a volatile cell in a sense amplifier of a normal read system, and writing is performed to an address of the volatile cell. , A refresh operation is realized.

However, in such a conventional configuration, there is a problem that the refresh operation speed is reduced because the number of read-system sense amplifiers is small. In order to solve this problem, if the number of sense amplifiers in the readout system is increased, the circuit scale increases and the cost increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device which realizes a high-speed refresh function at low cost without increasing the circuit scale. It is in.

[0012]

In order to achieve the above-mentioned object, a nonvolatile semiconductor memory device according to the present invention includes a bit line connected to a memory cell and program data provided for at least one bit line. A latch circuit for holding, a transfer gate for electrically separating the latch circuit and the bit line according to a control signal, and at least two detection levels having different detection levels for detecting the potential of the bit line.
A bit line potential detection circuit, and a latch set circuit that sets a result of comparison between output signals of the bit line potential detection circuit in a latch circuit.

In this case, the at least two bit line potential detection circuits include first and second bit line detection circuits, and the first bit line potential detection circuit is set to a logic determination level during a program verify operation. The second bit line potential detection circuit has a second detection level set near a logic determination level in a data read operation.

In order to achieve the above object, a refresh method of a nonvolatile semiconductor memory device according to the present invention detects a potential of a bit line connected to a memory cell based on different detection levels, and performs detection based on different detection levels. A memory cell having a tendency to volatilize is specified based on the comparison of the results, and a write operation of program data is performed by holding the comparison result.

In the above configuration and method, the potential of the bit line is detected by at least two bit line potential detection circuits having different detection levels, and the detection results are compared to identify a memory cell having a tendency to volatilize. The result of the comparison is held in a latch circuit, and a write operation is performed by a page program technique to realize a refresh function. Thus, the same number of memory cells as the page program can be simultaneously refreshed, and the refresh time can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing a partial configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention. FIG.
In the figure, 1 is a memory cell array, and 2 is a column latch having a program / program verify circuit having a refresh function.

The internal potential Vpp in the drawing changes according to the circuit operation and has at least two or more potentials. For example, in the case of a single-power-supply flash memory, the power supply potential Vdd and the internal booster circuit are used. The high potential at the time of rewriting corresponds to this, and in the case of a dual power supply flash memory,
A power supply potential higher than the power supply potential Vdd and another power supply potential corresponds to this.

FIG. 2 is a timing chart for explaining a program operation, a program verify operation, and a refresh operation in the nonvolatile semiconductor memory device of FIG.

FIG. 3 is a circuit diagram of the memory cell array 1 shown in FIG.
The threshold voltage in the gram and erase states.
It is a schematic diagram which shows the number-of-units distribution. In FIG. 3,
The arrow indicates the retention characteristic in the program state.
The threshold voltage distribution shown by the solid line from the threshold voltage distribution shown by the broken line.
Cloth, and the program verify judgment level VT _{twenty one}
Indicates a state in which it is overlapped.

As shown in FIG. 1, column latch 2 includes a transistor M for lowering bit line BL0 to ground potential.
D0, a transistor MP0 for charging the bit line BL0 to the internal potential Vpp, a bit line potential detection circuit 21 having a program verify detection level VT ₂₁ (program verify determination level), and a determination used during normal reading. Detection level VT near level
_And a latch circuit 2 for holding program data.
3. The transfer gate 24 for electrically separating the bit line BL0 from the latch circuit 23, and the Pch transistor MPT in the transfer gate 24 when the control signal TFG of the transfer gate 24 becomes active.
An inverter 25 for driving 0 to an active state, and a latch set circuit 26 for setting the result of comparison between the outputs of the bit line potential detection circuit 21 and the bit line potential detection circuit 22 in the latch circuit 23.

Latch circuit 2 for storing program data
3. Pch transistor MPT0 in transfer gate 24, inverter 25, bit line potential detection circuit 21
, And Pch transistors MPV2 and MV in the bit line potential detection circuit 22.
PV3 and the latch set circuit 26 have the internal potential V
pp is supplied.

The bit line potential detection circuit 21 has a "NOR
(Inverted OR), one input of which is connected to the bit line BL0 and the other input of which is connected to the control signal VRF. potential outputs a logic "H" when the signal falls below the detection level VT ₂₁ of the bit line potential detection circuit 21.

The bit line potential detection circuit 22 also has a NOR logic function, one input of which is connected to the bit line BL0 and the other input of which is connected to the control signal VRF.
RF outputs a logical "L" when a logical "L", and the potential of the bit line BL0 is higher than the detection level VT ₂₂ of the bit line potential detection circuit 22, the logic when falls below detection level VT ₂₂ "H Is output.

Here, the bit line potential detection circuit 21 and the bit line potential detection circuit 22 have different detection levels.
As shown in FIG. 3, the bit line potential detection circuit 21 has a detection level VT ₂₁ for program verification, and the bit line potential detection circuit 2 has a detection level VT set near a determination level used during normal reading. _{With 22} .

The output signals of the bit line potential detecting circuit 21 and the bit line potential detecting circuit 22 are input to a latch set circuit 26 having a logical function of "XOR (exclusive OR)". If the output signals of the bit line potential detection circuit 22 match, the level of the output signal V _N3 of the latch set circuit 26 is reduced to the ground potential,
If they do not match, the output signal V _N3 is raised to the internal potential Vpp. With this operation, the data held in the latch circuit 23 is determined.

The latch set circuit 26 is controlled by a control signal VRF, and the control signal VRF is set to a logic "L".
At this time, the latch set circuit 26 becomes active. When the control signal VRF is logic "H", the latch set circuit 26 is inactive and its output is in a high impedance state, so that the data in the latch circuit 23 is not rewritten.

Next, the program operation, program verify operation and refresh operation of the column latch 2 configured as described above will be described with reference to FIGS.

(Program Operation) At the time of a program operation, first, program data is loaded into the latch circuit 23. The latch circuit 23 connected to the memory cell to be programmed holds the state of logic "H" as a data signal, and the latch circuit 23 connected to the memory cell not programmed holds the state of logic "L" as a data signal. ing.

In order to program a memory cell,
First, the internal potential Vpp is set to 5 V which is a program voltage. Next, the transfer gate control signal TFG is set to 5 V to activate the transfer gate 24, and the bit line BL0 and the latch circuit 23 are electrically connected.

At the same timing as this operation, the word line WL0 of the selected memory cell MEM0 is set to -8 V, the control signal SLSEL of the source line SL0 is made inactive, and the source line SL0 is opened.

In order to apply a program voltage to the drain of memory cell MEM0, select gate STR is applied.
0 as a select gate control signal SG0.
Apply 8V. Here, since the internal potential Vpp (5 V) is applied to the drain of the select gate STR0, Vpp is selected as the select gate control signal SG0 so that the voltage drop due to the substrate bias effect does not occur.
A voltage of 8 V which is equal to or higher than + Vtn (Vtn is a threshold voltage of the select gate) is applied.

If the data held in the latch circuit 23 is logic "H", 5 V is supplied to the drain of the memory cell MEM0, and an electric field sufficient to generate FN tunneling is applied to the tunnel oxide film. And electrons are emitted from the floating gate across the tunnel oxide film.

On the other hand, if the data held in the latch circuit 23 is logic "L", the drain of the memory cell MEM0 becomes 0 V, so that no FN tunneling current flows and no programming is performed.

After setting the internal potential Vpp to 5 V which is the program voltage for a predetermined period, the transfer gate 2
4 and the select gate STR0 are deactivated to electrically isolate the bit line BL0 and the latch circuit 23, and at the same time, the word line WL0 and the source line SL0 are dropped to the ground potential.

Finally, the discharge signal DSC is set to logic "H" to activate the transistor MD0, and the select gate control signal SG0 is set to 8 V to activate the select gate STR0, thereby charging the bit line BL0. To discharge.
The above operation completes the program operation.

(Program Verify Operation) First, the internal potential Vpp is set to the level Vdd which is a verify drain voltage.

Next, the transfer gate control signal TF
G is set to Vdd to activate the transfer gate 24 and select gate control signal SG0.
Is set to 8 V to activate the select gate STR0, and the transfer gate control signal TFG is set to Vdd.
, The bit line BL0 is precharged to the verify drain voltage Vdd.

At the time when the precharge is completed, the transfer gate control signal TFG is deactivated, and a program verify voltage of 1 V is applied to the word line WL0 of the selected memory cell MEM0 to set the memory cell to the verify mode. .

At this time, if the programming of the memory cell is performed properly, a slight memory cell current flows, and the charge of bit line BL0 precharged to verify drain voltage Vdd is discharged (period in FIG. 2). T
d). Here, if there is a leak current from the unselected memory cell MEM1, the potential of the bit line BL0 decreases and causes an erroneous determination. Therefore, the unselected word line WL1 is dropped to the ground potential. Note that, if the non-selected word line WL1 is set to a negative voltage, the leak current can be further reduced.

When a control signal VRF of the latch set circuit 26, the bit line potential detection circuit 21, and the bit line potential detection circuit 22 is set to logic "L" (Vss) after the memory cell current flows for a predetermined period, the bit line The potential of BL0 is
The below both detection level VT ₂₂ of the detection level VT ₂₁ and the bit line potential detection circuit 22 in the bit line potential detection circuit 21,
The output signal V _N1 from the bit line potential detection circuit 21 and the output signal V _N2 from the bit line potential detection circuit 22 both become logic “H”.

Therefore, in the latch set circuit 26, since the logic of the output signal V _N1 from the bit line potential detection circuit 21 and the logic of the output signal V _N2 from the bit line potential detection circuit 22 are both “H”, they match. Logic "L" by XOR logic function
And rewrite the data in the latch circuit 23 to logic “L”. At this time, the logic circuit configuring the latch set circuit 26 is designed to have a greater driving capability than the latch circuit 23 so that the data in the latch circuit 23 can be rewritten.

If the proper programming has not been performed, no current flows through the bit line BL0, thereby
Since 0 potential is higher than the detection level VT _21, the output signal of the bit line potential detection circuit 21 becomes logical "L".
On the other hand, when the memory cell to be program-verified is an erased cell (hereinafter referred to as an erased cell), the bit line potential detection circuit 22 outputs a logic “L” to indicate a memory cell or a volatile cell which is insufficiently programmed. In this case, the logic "H" is output.

Therefore, the latch set circuit 26 writes logic "L" data into the latch circuit 23 in the case of an erased cell, and writes the logic "H" in the latch circuit 23 in the case of a memory cell or a volatile cell in which programming is insufficient. Write. As a result, program verification and identification of volatile cells are performed. Thus, the program verify operation is completed.

Here, since the program voltage is applied by the data in the latch circuit 23, the program voltage is not applied to the bit line BL0 from now on to the memory cells which have been properly programmed and the memory cells which are not volatile cells. .

(Refresh Operation) In the refresh operation, a write operation is performed after specifying volatile cells. The specific operation of the volatile cell is basically the same as the above-described program verify operation. However, during the specific operation of the volatile cell, it is necessary to perform the verify operation on the target memory cell regardless of the data held in the latch circuit 23. is there. For this reason, during the program verify operation, the precharge operation is performed by activating the transfer gate control signal TFG. However, during the specific operation of the volatile cell, the transfer gate control signal TFG signal is not activated and the precharge signal is not activated. The precharge operation is realized by activating the PRC.

However, the precharge signal PRC is not necessarily
It is not necessary to provide
All the data held in the latch circuit 23 are previously set to “1”.
If it is set to (write execution state), the specific operation of the volatile cell can be completely the same as the program verify operation.

In this embodiment, as described above, the difference between the volatile cell specifying operation and the program verify operation is as follows.
Since only the precharge signal PRC is activated instead of the transfer gate control signal TFG, the description is omitted.

After the specific operation of the volatile cell is completed,
Shift to the above program operation. Thus, the refresh operation is completed.

As described above, in the present embodiment, the bit line potential is detected by the two bit line potential detection circuits 21 and 22 having different detection levels, and the latch set circuit 26 is detected.
Thus, the volatile cell is specified by comparing its output, the comparison result is set in the latch circuit 23, and the write operation is performed by a page program technique, thereby realizing the refresh function. Thus, the same number of memory cells as the page program can be simultaneously refreshed, and the refresh time can be reduced.

[0051]

As described above, according to the present invention,
This provides a special effect that it is possible to provide a nonvolatile semiconductor memory device that realizes a high-speed refresh operation at low cost without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a partial configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention;

FIG. 2 is a timing chart for explaining a program operation, a program verify operation, and a refresh operation in the nonvolatile semiconductor memory device of FIG. 1;

FIG. 3 is a schematic diagram showing distribution of threshold voltages in a program state and an erase state of the memory cell array 1 of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Column latch 21 and 22 Bit line potential detection circuit 23 Latch circuit 24 Transfer gate 25 Inverter 26 Latch set circuit

Claims (3)

[Claims] 1. A bit line connected to a memory cell, a latch circuit provided for at least one bit line and holding program data, and electrically connecting the latch circuit and the bit line according to a control signal. Transfer gate, at least two bit line potential detection circuits having different detection levels for detecting the potential of the bit line, and a result of comparing output signals of the bit line potential detection circuit to the latch circuit. A nonvolatile semiconductor memory device comprising: a latch set circuit for setting. 2. The at least two bit line potential detection circuits include first and second bit line detection circuits,
The first bit line potential detection circuit has a first detection level set to a logic determination level at the time of a program verify operation, and the second bit line potential detection circuit has a logic determination level at a data read operation. 2. The nonvolatile semiconductor memory device according to claim 1, having a second detection level set near the level. 3. A method for refreshing a nonvolatile semiconductor memory device, comprising detecting a potential of a bit line connected to a memory cell based on different detection levels, and comparing the detection results based on the different detection levels. A method of writing a program data by specifying a memory cell having a tendency to volatilize and holding the comparison result.