JP2002304889A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leak current at the time of standby being a problem when a semiconductor memory of a current read-out type is made a low voltage and high speed type. SOLUTION: This memory is constituted of a current read-out type memory cell circuit 11 constituted of MOSFET connected between a power source and ground, a leak cut off switch element 18 connected in series to this memory cell circuit 11 and constituted of MOSFET having a leak current being smaller than that of MOSFET constituting the memory cell circuit 11, and a non-volatile memory element to which information stored in information holding nodes 19, 20 of the memory cell circuit 11 is supplied through a control switch.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory of a current reading method which realizes a low voltage, low power consumption and high speed operation by reducing a leakage current in a standby state.

[0002]

2. Description of the Related Art As the level of integration of semiconductor integrated circuits increases with the times, the demand for battery-driven LSIs has increased with the spread of mobile devices. In addition, low power consumption LSI is required.

[0003] In order to lower the operating voltage of the most common MOSFET constituting a semiconductor integrated circuit while maintaining its high-speed operation, it is necessary to lower the threshold voltage. However, when the threshold voltage is lowered, the off-state current during standby increases, or when the gate oxide film is thinned to lower the threshold voltage and increase the speed,
Problems such as an increase in gate leak current occur. Due to the large scale of the semiconductor integrated circuit, it is required that the off-state current of each transistor element be extremely small, and some countermeasures have been attempted.

For example, the inventors of the present invention have invented a method of adding a switch having a small leak current between a power supply line and a circuit as a method of cutting off a leak current at the time of standby in a semiconductor integrated circuit. No. 11-305344. However, this method can be applied to a general semiconductor integrated circuit, but cannot be applied to a semiconductor memory because power supply is indispensable even during standby for data retention.

In addition, when such a method is applied to individual memory cells, the conductivity of the switch in an active state decreases with a decrease in the power supply voltage, so that a large gate width is required, and the area of the memory cell is reduced. This increases the degree of integration of the semiconductor memory.

Further, the technique of turning off the power by temporarily saving data in a nonvolatile memory cannot be applied to a battery driven LSI because a huge leak current flows while the power is supplied. .

[0007]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory capable of reducing a standby leakage current which becomes a problem when a current reading type semiconductor memory is operated at a low voltage and at a high speed. Is to do.

[0008]

According to the present invention, there is provided a semiconductor memory, comprising: a current readout type memory cell circuit comprising a MOSFET connected between a power supply potential and a ground potential; The memory cell circuit comprises a leak cut-off switch element formed of a MOSFET having a smaller leak current than a MOSFET, and a nonvolatile memory element connected to an information holding node of the memory cell circuit via a control switch. It is assumed that.

Further, in the semiconductor memory of the present invention,
A voltage applied to a gate electrode of a MOSFET constituting the leak cutoff switch element is higher than a power supply voltage supplied to the memory cell circuit.

Further, in the semiconductor memory of the present invention, the gate oxide film thickness of the MOSFET forming the leak cutoff switch element is larger than the gate oxide film thickness of the MOSFET forming the memory cell circuit. is there.

Further, in the semiconductor memory according to the present invention, a threshold voltage of a MOSFET constituting the leak cutoff switch element is higher than a threshold voltage of a MOSFET constituting the memory cell circuit.

Further, in the semiconductor memory of the present invention, a plurality of the memory cell circuits are provided, and these memory cell circuits are arranged in a matrix in a row and column direction.
The leak cutoff switch element performs the standby control on a row-by-row basis by commonly connecting the plurality of memory cell circuits arranged in each of the rows.

Further, in the semiconductor memory of the present invention, a plurality of the memory cell circuits are provided, and these memory cell circuits are arranged in a matrix in the row and column directions.
The leak cutoff switch element is connected in common to a plurality of memory cell circuits arranged in a plurality of adjacent rows, so that the standby control is performed in block units with the plurality of rows as one block. It is a feature.

Further, in the semiconductor memory according to the present invention, a substrate terminal of a MOSFET constituting the memory cell circuit is connected to the power supply potential or the ground potential via the leak cutoff switch element. Things.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
This will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a memory cell circuit constituting a semiconductor memory of the present invention. The memory cell circuit 11 includes a memory cell section 12, a leak cutoff switch section 13, and a backup cell section 14. The memory cell section 12 is constituted by a MOSFET having a high current driving force but a large leak current, and constitutes a memory cell which operates at high speed at a low voltage. That is, the memory cell section 12 includes a flip-flop circuit 17 composed of two CMOS inverter circuits 15 and 16. One end of the flip-flop circuit 17 has the power supply potential VDD.
The other end is connected to a ground potential VSS via a leak cutoff switch element 18 included in the leak cutoff switch section 13.
It is connected to the. Information holding nodes 19 and 20 for holding binary information (1, 0) of the flip-flop circuit 17 are connected to bit lines BL and / BL via transfer gate transistors 21 and 22, respectively. The gate electrodes of the two transfer gate transistors 21 and 22 are connected to a word line WL.

Next, a control line A for controlling ON / OFF of the switch element 18 is connected to the gate electrode of the leak cut-off switch element 18 of the leak cut-off switch section 13. Here, the leak cutoff switch element 18
Are composed of MOSFETs having a smaller leakage current than the MOSFETs forming the two CMOS inverter circuits 15 and 16 included in the memory cell unit 12. For MOSFETs with low leakage current, as described above, make the gate oxide film thicker,
This can be realized by setting the threshold potential to be high and making the potential given to the gate electrode by the gate control line A high.

The backup cell section 14 includes two gate transistors 23 and 24 and two nonvolatile memory elements 25 and 26 such as a ferroelectric memory. Gate transistor 23 is connected in series to nonvolatile memory element 25, and the other end of gate transistor 23 is connected to information holding node 19 of memory cell unit 12. The other end of the nonvolatile memory element 25 is connected to a plate line P for driving the nonvolatile memory element 25.
L. On the other hand, the gate transistor 24 is connected in series to the nonvolatile memory element 26, and the other end of the gate transistor 24 is connected to the information holding node 20 of the memory cell unit 12. The other end of the nonvolatile memory element 26 is connected to a plate line PL for driving the nonvolatile memory element 26.

The memory cell circuit 11 having such a configuration is
A memory array is formed by arranging the matrix vertically and horizontally. However, in the memory array having such a configuration, the leak cutoff switch element 18 of the leak cutoff switch section 13 is provided in each memory cell, and the occupied area per memory cell increases. By providing one memory cell belonging to the row of the array and sharing the memory cell with a plurality of memory cells belonging to the row, the occupied area per memory cell can be reduced.

FIG. 2 is a block diagram showing a memory array having such a configuration. In the figure, portions corresponding to the configuration of FIG. 1 are denoted by the same reference numerals. In this memory array, the memory cell section 12 and the backup cell section 14 are arranged in a matrix, and one leak cutoff switch element 18 of the leak cutoff switch section 13 is provided for each row. A plurality of memory cell units 12 arranged in a corresponding row are connected to the leak cutoff switch element 18. That is, the memory cell unit 12 shown in FIG.
, The common connection portion V of the two CMOS inverter circuits 15 and 16 is connected to each other by a VSSV line,
This VSSV line is connected to the ground potential VSS via the leak cutoff switch element 18.

Next, the standby operation in the memory of the present invention thus configured will be described. When entering the standby state, first, the data stored in the information holding nodes 19 and 20 of the memory cell unit 12 is written into the nonvolatile memories 25 and 26 by the control lines (C1 and PL) in the backup cell unit 14. Here, positive and negative potentials enabling writing of information to the nonvolatile memories 25 and 26 are alternately applied to the plate line PL, and this potential and the information holding nodes 19 and 20 of the memory cell unit 12 are held. The binary information corresponding to the potential of the information holding nodes 19 and 20 is written to the nonvolatile memory by the potential difference from the applied potential.

Thereafter, the potential of the control line A of the leak cutoff switch section 13 is switched from a high level to a low level, that is, turned off, so that the leak cutoff switch element 18 is turned off. As a result, the two Cs of the memory cell unit 12 move from the power supply potential VDD to the ground potential VSS.
The leakage current that constantly flows through the MOS inverter circuits 15 and 16 is cut off. At this time, since the nodes 19 and 20 of the memory cell unit 12 have the same potential as VDD, the data held in the memory cell unit 12 is lost.

Next, when returning to the active state, the potential of the control line A of the leak cutoff switch section 13 is turned on and the control line C1 is turned on to store the data in the nonvolatile memories 25 and 26. The data is returned to the memory cell unit 12.

In the memory array of FIG. 2, standby control is performed on a row-by-row basis. At this time, in order to return only the selected row to active, the control line A and the control line C1 are connected simultaneously with the word line WL. Turn on. As a result, the leak cutoff switch element 18 and the gate transistor 2
As soon as 3 and 24 are turned on and data is returned to the memory cell section 12, a potential difference is generated between the bit lines BL and / BL, and the read operation of the memory cell section 12 is performed.

FIGS. 3 and 4 are a circuit diagram of a memory cell and a block diagram of a memory array showing another embodiment of the present invention.

In the memory cell circuit 11 of FIG. 1, an n-type MOSFET is inserted between the VSS and the memory cell section 12 as the leak cutoff switch 18, but in the memory cell circuit 11 'of FIG. As the cutoff switch 18 ′, a p-type MOSFET is inserted between VDD and the memory cell unit 12. In this case, a control line / A for applying a potential obtained by inverting the potential given by the control line A in FIG. 1 is connected to the gate electrode of the leak cutoff switch 18 '. In this embodiment, the leak current flowing from the VDD side to the set potential VSS via the memory cell unit 12 can be blocked by the leak cutoff switch 18 '. However, the transfer gate transistor 2 is connected to the bit lines BL and / BL.
The leak current flowing to the installation potential VSS via 1 'and 22' cannot be cut off by the leak cutoff switch 18 '. Therefore, the transfer gate MOSFET transistors 21 ′ and 22 ′ connected to the bit line use the same one as the leak cutoff switch 18 shown in FIG. 1 to cut off the leak current from the bit lines BL and / BL. I have.

FIG. 4 shows such a memory cell section 12 of FIG.
And a backup cell unit 14. The memory array includes a leak cutoff switch unit 1 as in FIG.
The three leak cutoff switch elements 18 'are provided in common for the plurality of memory cell units 12 arranged in one row. That is, the common connection portion V of the two CMOS inverter circuits 15 and 16 included in the memory cell portion 12 shown in FIG. 3 is connected to each other by a VDDV line (pseudo VDD line), and this VDDV line is 18 'is connected to the power supply potential VDD.

Since the other components in FIGS. 3 and 4 are the same as those in FIGS. 1 and 2, corresponding components are denoted by corresponding reference numerals and detailed description thereof will be omitted.

According to the embodiment of the present invention described above,
The following effects can be obtained. 1. High-speed operation at low voltage is realized by configuring the memory cells with MOSFETs with high driving power. As a result, power consumption during operation can be reduced. At this time, an off-leak current that increases with an increase in the driving force of the memory cell is not a problem because it is cut off by a leak cut-off switch constituted by a MOSFET having a small leak current. Further, even when the power supply is stopped, the data is retained by the nonvolatile memory. 2. By increasing the conductivity of the leak cutoff switch in the active state, the gate width can be reduced, and an increase in the area of the memory cell can be suppressed. 3. By reducing the leakage current in the leakage cutoff switch, power consumption during standby is reduced. 4. Although a memory cell in an active state has a large leak current, by performing standby control on a row-by-row basis, the number of memory cells in the active state is minimized and its off-leakage current is suppressed. In addition, since reading of data from the semiconductor memory is generally performed in units of rows, standby control synchronized with reading can be performed. 5. Since the leak cutoff switch can be arranged outside the memory cell portion, an increase in the area of the memory cell can be suppressed. Also, it has a high affinity with the standby control on a line-by-line basis.

FIGS. 5 and 6 are block diagrams of a memory array showing still another embodiment of the present invention. In these embodiments, the leak cutoff switch is provided for each block, with the memory cell units 12 in a plurality of rows as blocks. In the memory array of FIG. 5, an n-type MOSFET is used as the leak cutoff switch element 18 and a common line VSSV that interconnects the memory cell units 12 belonging to a plurality of rows.
(Pseudo VSS line) and one ground potential VSS.

On the other hand, in the memory array of FIG. 6, one p-type MOSFET is connected as the leak cutoff switch element 18 'between the VDDV line interconnecting the memory cell sections 12 belonging to a plurality of rows and the power supply potential VDD. Have been. Since the other components in FIGS. 5 and 6 are the same as those in FIGS. 2 and 4, corresponding components are denoted by corresponding reference numerals and detailed description thereof will be omitted.

According to this embodiment, the following effects can be obtained in addition to the effects described above. 1. Prior to data reading, a block including a row to be read can be returned to an active state, and the time required to restore data from the nonvolatile memory in reading data of each row can be reduced. Become. In general, in a semiconductor memory, adjacent rows are often read continuously, so that the transition between active and standby can be reduced as compared with a case where standby control is performed on a row-by-row basis. It is possible to suppress the deterioration of the write resistance of the volatile memory. 2. Since the leak cutoff switch can be arranged outside the memory cell portion, an increase in the area of the memory cell can be suppressed. In addition, since reading of data from the semiconductor memory is performed in units of rows, the required conductivity at the time of active is about the same as that in the case of connection in units of rows. Therefore, it is possible to suppress the area increase due to the leak cutoff switch as compared with the case where the connection is made in units of rows. Further, it has high affinity with the above-described standby control in units of blocks.

FIG. 7 is a circuit diagram of a memory cell showing still another embodiment of the present invention. CMO of memory cell section 12
The substrate terminals of the MOSFETs constituting the S inverter circuits 15 and 16 are usually connected to VDD for the p-type MOSFET and to VSS for the n-type MOSFET. In this embodiment, the substrate terminals 27 and 28 of the p-type MOSFET are Is connected to VDD, and the substrate terminals 29 and 30 of the n-type MOSFET are connected to the n-type MOSFET leak cutoff switch 1.
8 to the ground potential VSS. This makes it possible to prevent a gate tunnel leak and a junction leak in the MOSFETs forming the CMOS inverter circuits 15 and 16.

Since the other components in FIG. 7 are the same as those in FIG. 1, the corresponding components are denoted by the corresponding reference numerals, and detailed description is omitted.

FIG. 8 is a circuit diagram of a memory cell showing still another embodiment of the present invention. CMO of memory cell section 12
Of the substrate terminals of the MOSFETs constituting the S inverter circuits 15 and 16, the substrate terminals 27 and 28 of the p-type MOSFET are p-type MOSFETs.
Connected to VDD via T leak cutoff switch 18 '. The substrate terminals 29 and 30 of the n-type MOSFET are connected to VSS. This makes it possible to prevent a gate tunnel leak and a junction leak in the MOSFETs forming the CMOS inverter circuits 15 and 16.

Since the other components in FIG. 8 are the same as those in FIG. 1, the corresponding components are denoted by the corresponding reference numerals, and detailed description is omitted.

In the above embodiment, the SRAM is used as the memory cell and the ferroelectric memory is used as the nonvolatile memory. However, any combination of the current readout type memory and the nonvolatile memory, or the integration such as the EEPROM can be used. The present invention is also applicable to a memory that has been used.

In the above embodiment, the SRAM is used as the memory cell and the ferroelectric memory is used as the nonvolatile memory. However, any combination of the current read type memory and the nonvolatile memory, or the integration such as the EEPROM can be used. The present invention is also applicable to a memory that has been used.

[0039]

According to the present invention, it is possible to provide a semiconductor memory capable of reducing a leakage current at the time of standby which is a problem when a current reading type semiconductor memory is operated at a low voltage and at a high speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a memory cell circuit forming a semiconductor memory of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory array in which the memory cell circuits 11 of FIG. 1 are arranged vertically and horizontally in a matrix.

FIG. 3 is a circuit diagram of a memory cell showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a memory array using the memory cell circuit diagram shown in FIG. 3;

FIG. 5 is a block diagram of a memory array showing still another embodiment of the present invention.

FIG. 6 is a block diagram of a memory array showing still another embodiment of the present invention.

FIG. 7 is a circuit diagram of a memory cell showing still another embodiment of the present invention.

8 is a block diagram showing a memory array using the memory cell circuit diagram shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Memory cell circuit 12 Memory cell part 13 Leakage cutoff switch part 14 Backup cell part 15 CMOS inverter circuit 16 CMOS inverter circuit 17 Flip-flop circuit 18 Leakage cutoff switch element 19, 20 Information holding node 21, 22 Transfer gate transistor 23, 24 Gate Transistors 25, 26 Nonvolatile memory elements

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takashi Inukai 4-6-1, Komaba, Meguro-ku, Tokyo F-term (Reference) 5B015 HH04 JJ05 KA06 KA10 QQ01 QQ03 QQ17

Claims (7)

[Claims] 1. A power supply connected between a power supply potential and a ground potential.
A current readout memory cell circuit composed of MOSFETs;
An MO connected in series to the memory cell circuit and having a smaller leakage current than the MOSFETs constituting the memory cell circuit.
A semiconductor memory, comprising: a leak cutoff switch element configured by an SFET; and a nonvolatile memory element connected to a data holding node of the memory cell circuit via a control switch. 2. The leak cutoff switch element is configured.
2. The semiconductor memory according to claim 1, wherein a voltage applied to a gate electrode of the MOSFET is higher than a power supply voltage supplied to the memory cell circuit. 3. The leak cutoff switch element is configured.
2. The semiconductor memory according to claim 1, wherein a gate oxide film thickness of the MOSFET is larger than a gate oxide film thickness of a MOSFET constituting the memory cell circuit. 4. The leak cutoff switch element is configured.
The threshold voltage of the MOSFET is the MOSF constituting the memory cell circuit.
2. The semiconductor memory according to claim 1, wherein the semiconductor memory is higher than a threshold voltage of ET. 5. The memory cell circuit according to claim 1, wherein a plurality of memory cell circuits are provided.
These memory cell circuits are arranged in a matrix in the row and column directions, and the leak cutoff switch element is connected in common to a plurality of memory cell circuits arranged in each of the rows, whereby the standby control is performed on a row basis. 2. The semiconductor memory according to claim 1, wherein the processing is performed by: 6. A plurality of memory cell circuits are provided,
These memory cell circuits are arranged in a matrix in a row and column direction, and the leak cutoff switch element is connected to a plurality of memory cell circuits arranged in a plurality of adjacent rows in common, thereby performing the standby control. 2. The mounted semiconductor memory according to claim 1, wherein the processing is performed in units of a block in which the plurality of rows are one block. 7. The semiconductor memory according to claim 1, wherein a substrate terminal of a MOSFET constituting said memory cell circuit is connected to said power supply potential or ground potential via said leak cutoff switch element.