JP2002304308A - Test method for semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test method for a semiconductor chip capable of reducing a test time for packet transfer. SOLUTION: When nodes of an IEEE1394 PHY chip 11 and a tester 13 rise, arbitration of a bus between the PHY chip 11 and the tester 13 is started. A request state (request) transmitted from the PHY chip 11 and a grant state (grant) received by the tester 13 are omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor chip for performing packet transfer. In particular, the present invention relates to a method for testing a semiconductor chip that can reduce the test time for packet transfer.

[0002]

2. Description of the Related Art Conventionally, IEEE (Institute of Electri)
When a packet transfer test is performed on a semiconductor chip such as a 1394 PHY chip, the following procedure is used.

FIG. 7 is a flowchart showing a conventional semiconductor chip test method. FIG. 8 is a diagram showing initialization of a bus between a semiconductor chip and a target (tester) connected to the semiconductor chip. FIG. 9 is a diagram showing bus arbitration and data transfer between a semiconductor chip and a target (tester) connected to the semiconductor chip.

In FIG. 7, first, IEEE 1394
A command for making a transition to the test mode from the input unit is input to the PHY chip, and the test is started.
(Step 101).

When the test is started, the IEEE 1394
Initialize the bus with the tester connected to the PHY chip (step 103). The initialization of the bus is to change the voltage between the nodes of the IEEE 1394 PHY chip and the tester from the state of Z (high impedance) to the common voltage (1.85 V) as shown in FIG. . In this work, after the connection work is started, the IEEE 1394 PH
It takes about 330 ms until the own node of the Y chip starts up. In addition, it takes about 5.3 ms until the partner (tester) node starts up.

When the nodes of the IEEE 1394 PHY chip and the tester start up (step 105), arbitration of the bus between the IEEE 1394 PHY chip and the tester is started as shown in FIG.

First, a request state (request) is transmitted from the IEEE1394 PHY chip to the tester (step 107).

[0008] The tester receives a request state from the IEEE1394 PHY chip and receives a grant state.
(grant) is received (step 109).

Next, a data prefix state is transmitted from the IEEE1394 PHY chip to the tester.
x) is transmitted (step 111).

Following the data prefix state,
Data transfer is started (step 113).
Data transfer is performed by handshake while taking confirmation and response.

Finally, a data end state (Data End) is transmitted from the IEEE1394 PHY chip to the tester (step 115).

[0012]

When performing a packet transfer test, arbitration is performed in the same manner as in a normal packet transfer, so that the time required for the test is increased. Further, since a large variety of large state machine circuits of the PHY logic section are directly transited at the time of a test, the test time is further increased.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a method of testing a semiconductor chip capable of shortening a packet transfer test time.

[0014]

According to a first aspect of the present invention, there is provided a method for testing a semiconductor chip, comprising the steps of: transmitting a packet between a semiconductor chip and a target connected to the chip; A test method of a semiconductor chip for performing a transfer test, wherein the semiconductor chip is provided with external pins, data for transitioning to a test is input from the external pins, and the semiconductor chip is transitioned to a test mode, In the test mode, the arbitration request state and grant state are omitted.

Since the request state and the grant state are omitted during the packet transfer test, the test time can be reduced. In addition, the cost required for the test can be reduced.

According to a second aspect of the present invention, there is provided a semiconductor chip test method for performing a packet transfer test with a target connected to the semiconductor chip using the semiconductor chip. An external pin is provided on the semiconductor chip, data for transitioning to a test is input from the external pin, the semiconductor chip is transitioned to a test mode, and the request state of arbitration is omitted in the test mode. Features.

Since the request state is omitted during the packet transfer test, the test time can be reduced. In addition, the cost required for the test can be reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, IEEE (Institut
e of Electrical and Electronics Engineers) 139
A 4PHY chip will be described as an example, but the test method of the present invention is not limited to this.
The present invention is also applicable to communication control chips such as CSI (Small Computer System Interface).

First, a method for testing a semiconductor chip according to the first embodiment of the present invention will be described.

FIG. 1 is a block diagram showing a schematic configuration of an apparatus for executing a method for testing a semiconductor chip according to a first embodiment of the present invention. FIG. 2 is a diagram showing a schematic configuration of an IEEE 1394 PHY chip of an apparatus for performing the semiconductor chip test method according to the first embodiment of the present invention.

As shown in FIG. 1, an apparatus for performing a method for testing a semiconductor chip according to a first embodiment of the present invention includes a control unit 3 for controlling the entire apparatus, and a storage / load of a test program and the like. Storage unit 5, an input unit 7 for inputting a command or the like for instructing a test, a display unit 9 for displaying a test result or the like, and an IEEE for packet transfer with an external device
And an E1394 PHY chip 11. IEEE
A target 13 for performing packet transfer is connected to the E1394 PHY chip 11. At the time of the packet transfer test, a tester is connected as the target 13.

An external pin 17 is provided on the IEEE 1394 PHY chip 11 of the apparatus for performing the semiconductor chip test method of this embodiment. External pin 1
7 is connected to the control unit 3 of the execution device. IEEE
A command for transition to the test mode is input from the input unit 7 to the external pin 17 of the 1394 PHY chip 11, and the IEEE 1394 PHY chip 11 transitions to the test mode.

Further, as shown in FIG.
Reser of PHY register of 394PHY chip 11
SpeedCode and PHYID
Is stored. SpeedCode is IEEE1
Shows information on the maximum transfer speed of packet data when performing packet transfer with the tester 13 connected to the 394 PHY chip 11. The PHY ID indicates an ID for specifying a node of the tester 13 connected to the IEEE1394 PHY chip 11. As described above, since the maximum transfer speed of the packet data with the tester 13 connected at the time of the test and the ID of the tester 13 are known in advance, they are set to IEEE
Res of PHY register of E1394PHY chip 11
The connection work is shortened by storing it in the erve area 19.

Further, as shown in FIG.
Reset of PHY register of 1394 PHY chip 11
In the rve area 19, a FirstTime bit is provided. In the test mode, the IEEE1394P
The FirstTime bit = “1” is input to the Reserve area 19 of the PHY register of the HY chip 11. When the FirstTime bit is 1, the handshake time specified in the standard for packet transfer is reduced. The handshake time is conventionally defined to take about 330 ms, but in this embodiment,
This is reduced to 1-2 μs.

Next, a method for testing a semiconductor chip according to the first embodiment of the present invention will be described.

FIG. 3 is a flowchart showing a method for testing a semiconductor chip according to the first embodiment of the present invention. FIG. 4 is a diagram showing bus arbitration and data transfer between a semiconductor chip and a target (tester) connected to the semiconductor chip.

In FIG. 3, first, IEEE1394
A command for transitioning to the test mode from the input unit 7 (see FIG. 1) is input to the external pin 17 (see FIGS. 1 and 2) of the PHY chip 11 (see FIGS. 1 and 2), and the IEEE
The 1394 PHY chip 11 transitions to the test mode (step 1).

In this embodiment, the IEEE
First Time bit = “1” is input from the input unit 7 to the external pin 17 of the E1394 PHY chip 11 (step 3).

When the IEEE1394 PHY chip 11 transitions to the test mode, the Spe of the connected tester 13
edCode and PHYID information are transferred to IEEE1394
It is read from the Reserve area 19 (see FIGS. 1 and 2) of the PHY register of the PHY chip 11 and virtually set (step 5).

The SpeedCod of the connected tester 53
e and the PHYID information are virtually set, so that the bus initialization shown in FIG. 7 is not required,
The node starts up in a short time (step 7).

When the nodes of the IEEE1394 PHY chip 11 and the tester 13 start up, as shown in FIG.
Arbitration of the bus between the IEEE1394 PHY chip 11 and the tester 13 is started.

Here, as shown in FIG. 4, in this embodiment, the request state (request) and the grant state (grant) of FIG. 9 are omitted.

Next, the IEEE1394 PHY chip 11
To the tester 13 from the data prefix state (Data
Prefix) is transmitted (step 11).

Following the data prefix state,
Data transfer is started (step 13). Data transfer is performed by handshake while taking confirmation and response. Here, in this embodiment, Fir
The test mode is recognized by the stTime bit, and this is shortened to 1-2 μs.

Finally, IEEE 1394 PHY chip 1
Data end state (Data End) from 1 to tester 13
Is transmitted (step 15).

In the method of testing a semiconductor chip according to this embodiment, since the maximum transfer speed of packet data with a tester connected at the time of testing and the ID of the tester are known in advance, the IEEE1394 PHY is used.
It is stored in the Reserve area of the PHY register of the chip. Thus, the initialization of the bus can be omitted in the test mode, so that the simulation time and the test time can be reduced. In addition, the cost required for the test can be reduced.

The PHY ID of the node connected to the Reserve area of the PHY register (I
D) and SpeedCode (maximum transfer speed of packet data), PHYID and Speed
The dCode can be set arbitrarily, and the setting of Parent and Child during arbitration can be freely determined.

Also, at the time of packet transfer, the handshake time specified in the standard can be reduced.

Further, at the time of packet transfer test, a request state (request) and a grant state (gran
Since t) is omitted, the test time can be reduced. In addition, the cost required for the test can be reduced.

Next, a method of testing a semiconductor chip according to a second embodiment of the present invention will be described.

FIG. 5 is a flowchart showing a method for testing a semiconductor chip according to the second embodiment of the present invention. FIG. 6 is a diagram showing bus arbitration and data transfer between a semiconductor chip and a target (tester) connected to the semiconductor chip.

In FIG. 5, first, IEEE 1394
A command for transitioning to the test mode from the input unit 7 (see FIG. 1) is input to the external pin 17 (see FIGS. 1 and 2) of the PHY chip 11 (see FIGS. 1 and 2), and the IEEE
The 1394 PHY chip 11 transitions to the test mode (step 21).

In this embodiment, the IEEE
First Time bit = '1' is input from the input unit 7 to the external pin 17 of the E1394PHY chip 11 (step 23).

When the IEEE1394 PHY chip 11 transitions to the test mode, the Spe
edCode and PHYID information are transferred to IEEE1394
It is read from the Reserve area 19 (see FIGS. 1 and 2) of the PHY register of the PHY chip 11 and virtually set (step 25).

The SpeedCod of the connected tester 53
e and the PHYID information are virtually set, so that the bus initialization shown in FIG. 7 is not required,
The node starts up in a short time (step 27).

When the nodes of the IEEE1394 PHY chip 11 and the tester 13 start up, as shown in FIG.
Arbitration of the bus between the IEEE1394 PHY chip 11 and the tester 13 is started.

First, the IEEE1394 PHY chip 11
Transmits a request state (request) to the tester 13 (step 29).

Here, as shown in FIG. 6, in this embodiment, the grant state shown in FIG. 9 is omitted.

Next, the IEEE1394 PHY chip 11
To the tester 13 from the data prefix state (Data
Prefix) is transmitted (step 31).

Following the data prefix state,
Data transfer is started (step 33). Data transfer is performed by handshake while taking confirmation and response. Here, in this embodiment, Fir
The test mode is recognized by the stTime bit, and this is shortened to 1-2 μs.

Finally, a data end state (Data End) is transmitted from the IEEE 1394 PHY chip to the tester (step 35).

In the semiconductor chip test method according to this embodiment, since the maximum transfer speed of packet data with the tester to be connected at the time of test and the ID of the tester are known in advance, the IEEE 1394 PHY is used.
It is stored in the Reserve area of the PHY register of the chip. Thus, the initialization of the bus can be omitted in the test mode, so that the simulation time and the test time can be reduced. In addition, the cost required for the test can be reduced.

The PHY ID of the node connected to the Reserve area of the PHY register (I
D) and SpeedCode (maximum transfer speed of packet data), PHYID and Speed
The dCode can be set arbitrarily, and the setting of Parent and Child during arbitration can be freely determined.

Also, at the time of packet transfer, the handshake time specified in the standard can be reduced.

Further, at the time of the packet transfer test, the request state (request) is omitted, so that the test time can be reduced. In addition, the cost required for the test can be reduced.

[0056]

As is clear from the above description, according to the present invention, the test time for packet transfer can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an apparatus for executing a test method of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is an IEEE1394P of an apparatus for executing the test method of the semiconductor chip according to the first embodiment of the present invention;
It is a figure showing the schematic structure of a HY chip.

FIG. 3 is a flowchart illustrating a method for testing a semiconductor chip according to the first embodiment of the present invention.

FIG. 4 is a diagram showing bus arbitration and data transfer between a semiconductor chip and a target (tester) connected to the semiconductor chip.

FIG. 5 is a flowchart illustrating a method for testing a semiconductor chip according to a second embodiment of the present invention.

FIG. 6 is a diagram showing bus arbitration and data transfer between a semiconductor chip and a target (tester) connected to the semiconductor chip.

FIG. 7 is a flowchart illustrating a conventional semiconductor chip test method.

FIG. 8 is a diagram showing initialization of a bus between a semiconductor chip and a target (tester) connected to the semiconductor chip.

FIG. 9 is a diagram showing bus arbitration and data transfer between a semiconductor chip and a target (tester) connected to the semiconductor chip.

[Explanation of symbols]

 3 control unit 5 storage unit 7 input unit 9 display unit 11 IEEE1394 PHY chip 13 target (tester) 15 dedicated ROM 17 external pin

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Claims (2)

[Claims] 1. A test method for a semiconductor chip, wherein a packet transfer test is performed between the semiconductor chip and a target connected to the semiconductor chip, wherein the semiconductor chip is provided with external pins. A method for testing a semiconductor chip, comprising: inputting data for transition from a pin to a test, causing the semiconductor chip to transition to a test mode, and omitting a request state and a grant state of arbitration in the test mode. 2. A test method for a semiconductor chip, wherein a packet transfer test is performed between the semiconductor chip and a target connected to the semiconductor chip, wherein the semiconductor chip is provided with external pins. A method for testing a semiconductor chip, comprising: inputting data for transition from a pin to a test, causing the semiconductor chip to transition to a test mode, and omitting an arbitration request state in the test mode.