JP2002299839A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JP2002299839A JP2002299839A JP2001100554A JP2001100554A JP2002299839A JP 2002299839 A JP2002299839 A JP 2002299839A JP 2001100554 A JP2001100554 A JP 2001100554A JP 2001100554 A JP2001100554 A JP 2001100554A JP 2002299839 A JP2002299839 A JP 2002299839A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- thickness
- circuit board
- insulating substrate
- signal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Waveguides (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は多層回路板に関し、
特にインピーダンス整合を達成できて、高速シグナル反
射（すなわち、高速信号反射）および電磁波障害を軽減
できる多層回路板に関する。The present invention relates to a multilayer circuit board,
In particular, the present invention relates to a multilayer circuit board capable of achieving impedance matching and reducing high-speed signal reflection (that is, high-speed signal reflection) and electromagnetic interference.
【０００２】[0002]
【従来の技術】工業規格によれば、８配線層の多層回路
板は、通常１．２ｍｍ型と１．６ｍｍ型を含む。図５に
示すのは約１．２ｍｍの厚さの多層回路板であり、連続
的に互いに上下積層して配置される第１、第２、第３、
第４、第５、第６、および第７の絶縁基板（Ａ１、Ａ
２、Ａ３、Ａ４、Ａ５、Ａ６およびＡ７）を含み、第１
のシグナル配線層（Ｓ１）が第１の絶縁基板（Ａ１）の
第２の絶縁基板（Ａ２）と相対する向きの反対側の面に
配置されて、第１の接地配線層（ＧＮＤ１）が第１と第
２の絶縁基板（Ａ１、Ａ２）の間に設けられ、第２のシ
グナル配線層（Ｓ２）が第２と第３の絶縁基板（Ａ２、
Ａ３）の間に配設され、第２のシグナル配線層（Ｓ３）
が第３と第４の絶縁基板（Ａ３、Ａ４）の間に設けら
れ、電源配線層（ＰＯＷＥＲ）が第４と第５の絶縁基板
（Ａ４、Ａ５）の間に配設され、第４のシグナル配線層
（Ｓ４）が第５と第６の絶縁基板（Ａ５、Ａ６）の間に
設けられ、第２の接地配線層（ＧＮＤ２）が第６と第７
の絶縁基板（Ａ６、Ａ７）の間に配設され、第５のシグ
ナル配線層（Ｓ５）が第７の絶縁基板（Ａ７）の第６の
絶縁基板（Ａ６）と相対する向きの反対側の面に設けら
れる。該第１、第３、第５および第７の絶縁基板（Ａ
１、Ａ３、Ａ５およびＡ７）はそれぞれポリエステルプ
リプレグによって形成され、第２、第４および第６の絶
縁基板（Ａ２、Ａ４およびＡ６）はそれぞれ紙あるいは
ガラス繊維を含んだ繊維質心材によって造られる。2. Description of the Related Art According to industry standards, a multilayer circuit board having eight wiring layers usually includes a 1.2 mm type and a 1.6 mm type. FIG. 5 shows a multilayer circuit board having a thickness of about 1.2 mm, in which first, second, third,
Fourth, fifth, sixth, and seventh insulating substrates (A1, A
2, A3, A4, A5, A6 and A7), the first
Is arranged on the surface of the first insulating substrate (A1) on the opposite side to the direction facing the second insulating substrate (A2), and the first ground wiring layer (GND1) is The second signal wiring layer (S2) is provided between the first and second insulating substrates (A1, A2) and the second and third insulating substrates (A2,
A3), a second signal wiring layer (S3)
Is provided between the third and fourth insulating substrates (A3, A4), and the power supply wiring layer (POWER) is provided between the fourth and fifth insulating substrates (A4, A5). A signal wiring layer (S4) is provided between the fifth and sixth insulating substrates (A5, A6), and a second ground wiring layer (GND2) is provided between the fifth and sixth insulating substrates (A5, A6).
And a fifth signal wiring layer (S5) on the opposite side of the direction in which the seventh insulating substrate (A7) faces the sixth insulating substrate (A6). Provided on the surface. The first, third, fifth and seventh insulating substrates (A
1, A3, A5, and A7) are each formed of a polyester prepreg, and the second, fourth, and sixth insulating substrates (A2, A4, and A6) are each formed of a fibrous core containing paper or glass fiber.
【０００３】さらに、第１および第７の絶縁基板（Ａ
１、Ａ７）はそれぞれ約２．５ｍｉｌ（ミルとも記す：
１ｍｉｌ＝０．０２５４ｍｍ＝２５．４μｍの関係にな
っている）の厚さ（Ｈ４）を有し、第２および第６の絶
縁基板（Ａ２、Ａ６）はそれぞれ約８ｍｉｌの厚さ（Ｈ
３）を有し、第３および第５の絶縁基板（Ａ３、Ａ５）
はそれぞれ約５ｍｉｌの厚さ（Ｈ２）を有し、第４の絶
縁基板（Ａ４）は約８ｍｉｌの厚さ（Ｈ１）を有する。
第１のシグナル配線層（Ｓ１）は、第１の接地配線層
（ＧＮＤ１）との間に第１の抵抗（Ｒｓ１）を有し、第
２のシグナル配線層（Ｓ２）は、第１の接地配線層（Ｇ
ＮＤ１）と電源配線層（ＰＯＷＥＲ）との間に第２の抵
抗（Ｒｓ２）を有し、第３のシグナル配線層（Ｓ３）
は、第１の接地配線層（ＧＮＤ１）と電源配線層（ＰＯ
ＷＥＲ）との間に第３の抵抗（Ｒｓ３）を有して、第４
のシグナル配線層（Ｓ４）は、第２の接地配線層（ＧＮ
Ｄ２）と電源配線層（ＰＯＷＥＲ）との間に第４の抵抗
（Ｒｓ４）を有し、第５のシグナル配線層（Ｓ５）は、
第２の接地配線層（ＧＮＤ２）との間に第５の抵抗（Ｒ
ｓ５）を有する。そのうち、第１および第５の抵抗（Ｒ
ｓ１、Ｒｓ５）の抵抗値は約４４オーム（Ωとも記す）
で、第２、第３および第４の抵抗（Ｒｓ２、Ｒｓ３およ
びＲｓ４）の抵抗値は約５１オームである。Further, first and seventh insulating substrates (A
1, A7) are each about 2.5 mil (also referred to as mill:
1mil = 0.0254 mm = 25.4 μm), and the second and sixth insulating substrates (A2, A6) each have a thickness (H2) of about 8 mil.
3) and the third and fifth insulating substrates (A3, A5)
Have a thickness (H2) of about 5 mils each, and the fourth insulating substrate (A4) has a thickness (H1) of about 8 mils.
The first signal wiring layer (S1) has a first resistor (Rs1) between itself and a first ground wiring layer (GND1), and the second signal wiring layer (S2) has a first ground. Wiring layer (G
ND1) and a power supply wiring layer (POWER), a second resistor (Rs2), and a third signal wiring layer (S3).
Are the first ground wiring layer (GND1) and the power supply wiring layer (PO
WER) and a third resistor (Rs3).
Signal wiring layer (S4) of the second ground wiring layer (GN
D2) and a power supply wiring layer (POWER), a fourth resistor (Rs4), and a fifth signal wiring layer (S5)
A fifth resistor (R) is provided between the second resistor and the second ground wiring layer (GND2).
s5). The first and fifth resistors (R
s1, Rs5) have a resistance of about 44 ohms (also referred to as Ω)
The resistance values of the second, third and fourth resistors (Rs2, Rs3 and Rs4) are about 51 ohms.
【０００４】図６に示すのは、従来の約１．６ｍｍの厚
さの多層回路板であり、上記１．２ｍｍ回路板と異なる
ところは上記Ｈ４が２．５ｍｉｌでなく９．５ｍｉｌ
で、その結果、第１および第５の抵抗（Ｒｓ１、Ｒｓ
５）の抵抗値が約７６．４オームである。これらの構成
のため、図５および図６に示す従来の多層回路板は下記
の欠点がある。 （ｉ）重大な高速シグナル反射がある。Ｉｎｔｅｌの設
定した標準理論値によれば、高速シグナル伝送の際にお
ける回路板の両隣接配線層間の抵抗値は５５＋１０％オ
ームの範囲、例えば４９．５オーム〜６０．５オームが
最も好ましいが、上記従来の１．２ｍｍ回路板の第１お
よび第５の抵抗（Ｒｓ１、Ｒｓ５）の抵抗値は約４４オ
ームで、Ｉｎｔｅｌの勧める好ましい範囲外にあって、
加えるに第１および第５の抵抗（Ｒｓ１、Ｒｓ５）の抵
抗値と第２、第３および第４の抵抗（Ｒｓ２、Ｒｓ３お
よびＲｓ４）の抵抗値との間に７オームの違いがあり、
この違いがインピーダンスの不釣合いを形成する。この
ように、高速シグナルが従来の１．２ｍｍ回路板を伝送
通過して、第１あるいは第５のシグナル配線層（Ｓ１、
またはＳ５）を経由して第２、第３あるいは第４のシグ
ナル配線層（Ｓ２、Ｓ３、またはＳ４）に至ると、シグ
ナルが反射を生じ、それによって、シグナルが逆反射伝
送をする。同様に、上記従来の１．６ｍｍ回路板の第１
および第５の抵抗（Ｒｓ１、Ｒｓ５）の抵抗値も理論範
囲外に陥り、第１および第５の抵抗（Ｒｓ１、Ｒｓ５）
の抵抗値と第２、第３および第４の抵抗（Ｒｓ２、Ｒｓ
３、Ｒｓ４）の抵抗値との間に大きな違いがある。それ
によりシグナル反射の問題が極めて重大となる。１．２
ｍｍ回路板の高速シグナルの反射指数は下記のように計
算できる。 Ｐ＝（Ｚ１−Ｚ０）/（Ｚ１＋Ｚ０）＝（Ｒｓ１−Ｒｓ
２）/（Ｒｓ１＋Ｒｓ２）＝０．０７ １．６ｍｍ回路板の反射指数も類似の方式で計算でき
て、さらに高い０．２である。それによりシグナル反射
の問題が極めて重大になり、波形を歪めてシグナルの品
質が悪化する。 （ｉｉ）磁束の反作用力が弱められる。高速シグナルの
反射によって定常波が生ずると、高速シグナルの電磁輻
射が増大して、回路板の磁束の反作用力が弱められ、か
なり高電磁波障害が発生する。FIG. 6 shows a conventional multi-layer circuit board having a thickness of about 1.6 mm. The difference from the above-described 1.2 mm circuit board is that the H4 is not 2.5 mil but 9.5 mil.
As a result, the first and fifth resistors (Rs1, Rs1,
5) The resistance value is about 76.4 ohms. Due to these configurations, the conventional multilayer circuit boards shown in FIGS. 5 and 6 have the following disadvantages. (I) There is significant fast signal reflection. According to the standard theoretical value set by Intel, the resistance value between both adjacent wiring layers of the circuit board during high-speed signal transmission is most preferably in the range of 55 + 10% ohm, for example, 49.5 ohm to 60.5 ohm. The resistance of the first and fifth resistors (Rs1, Rs5) of the conventional 1.2 mm circuit board is about 44 ohms, which is outside the preferred range recommended by Intel,
In addition, there is a 7 ohm difference between the resistance of the first and fifth resistors (Rs1, Rs5) and the resistance of the second, third and fourth resistors (Rs2, Rs3 and Rs4),
This difference forms an impedance imbalance. As described above, the high-speed signal is transmitted and transmitted through the conventional 1.2 mm circuit board, and the first or fifth signal wiring layer (S1,
Alternatively, when the signal reaches the second, third, or fourth signal wiring layer (S2, S3, or S4) via S5), the signal reflects, whereby the signal performs retroreflective transmission. Similarly, the first of the above conventional 1.6 mm circuit boards.
Also, the resistance values of the fifth and fifth resistors (Rs1, Rs5) fall outside the theoretical range, and the first and fifth resistors (Rs1, Rs5)
And the second, third and fourth resistors (Rs2, Rs
3, there is a great difference between Rs4) and the resistance value. This makes the problem of signal reflection extremely critical. 1.2
The reflection index of the high speed signal of the mm circuit board can be calculated as follows. P = (Z1-Z0) / (Z1 + Z0) = (Rs1-Rs
2) / (Rs1 + Rs2) = 0.07 The reflection index of a 1.6 mm circuit board can be calculated in a similar manner, and is even higher, 0.2. This makes the problem of signal reflection very serious, distorting the waveform and deteriorating the signal quality. (Ii) The reaction force of the magnetic flux is weakened. When a standing wave is generated by the reflection of the high-speed signal, the electromagnetic radiation of the high-speed signal increases, the reaction force of the magnetic flux of the circuit board is weakened, and a considerably high electromagnetic wave disturbance occurs.
【０００５】[0005]
【発明が解決しようとする課題】それゆえに、本発明
は、インピーダンス整合を達成できて、高速シグナル反
射および電磁波障害を軽減できる多層回路板を提供する
ことを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multilayer circuit board that can achieve impedance matching and reduce high-speed signal reflection and electromagnetic interference.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明の多層回路板は、上から下へと順に重畳配置
される第１、第２、第３、第４、第５、第６および第７
の絶縁基板を含んで、第１のシグナル配線層が第１の絶
縁基板の第２の絶縁基板と相対する向きの反対側の面に
配置され、第１の接地配線層が第１の絶縁基板と第２の
絶縁基板との間に配設され、第２のシグナル配線層が第
２の絶縁基板と第３の絶縁基板との間に配設され、第３
シグナル配線層が第３の絶縁基板と第４の絶縁基板との
間に配設され、電源配線層が第４の絶縁基板と第５の絶
縁基板との間に配設され、第４のシグナル配線層が第５
の絶縁基板と第６の絶縁基板との間に配設され、第２の
接地配線層が第６の絶縁基板と第７の絶縁基板との間に
配設され、第５のシグナル配線層が第７の絶縁基板の第
６の絶縁基板と相対する向きの反対側の面に配設され
て、第１および第７の絶縁基板の厚さがそれぞれ２．５
ｍｉｌ〜６．５ｍｉｌの範囲内にあり、第２、第４およ
び第６の絶縁基板の厚さがそれぞれ３ｍｉｌ〜９ｍｉｌ
の範囲内にあり、第３および第５の絶縁基板の厚さがそ
れぞれ３ｍｉｌ〜２３ ｍｉｌの範囲内にあり、第１の
シグナル配線層は、第１の接地配線層との間に第１の抵
抗を有し、第２のシグナル配線層は、第１の接地配線層
と電源配線層との間に第２の抵抗を有し、第３のシグナ
ル配線層は、第１の接地配線層と電源配線層との間に第
３の抵抗を有し、第４のシグナル配線層は、第２の接地
配線層と電源配線層との間に第４の抵抗を有し、第５の
シグナル配線層は、第２の接地配線層との間に第５の抵
抗を有すると共に、これらの第１、第２、第３、第４お
よび第５の抵抗の抵抗値は４９．５オーム〜６０．５オ
ームの範囲内に規制される。In order to achieve the above object, a multilayer circuit board according to the present invention comprises first, second, third, fourth, fifth and fifth layers which are superposed and arranged in order from top to bottom. 6th and 7th
The first signal wiring layer is disposed on the surface of the first insulating substrate opposite to the direction facing the second insulating substrate, and the first ground wiring layer is formed on the first insulating substrate. A second signal wiring layer disposed between the second insulating substrate and the third insulating substrate; and a third signal wiring layer disposed between the second insulating substrate and the third insulating substrate.
A signal wiring layer is provided between the third insulating substrate and the fourth insulating substrate, a power wiring layer is provided between the fourth insulating substrate and the fifth insulating substrate, and a fourth signal wiring layer is provided. 5th wiring layer
The second ground wiring layer is disposed between the sixth insulating substrate and the seventh insulating substrate, and the fifth signal wiring layer is disposed between the sixth insulating substrate and the sixth insulating substrate. The first and seventh insulating substrates are disposed on a surface of the seventh insulating substrate opposite to the direction facing the sixth insulating substrate, and each of the first and seventh insulating substrates has a thickness of 2.5.
mil to 6.5 mil, and the thickness of the second, fourth, and sixth insulating substrates is 3 mil to 9 mil, respectively.
, The thickness of each of the third and fifth insulating substrates is within a range of 3 mil to 23 mil, and the first signal wiring layer is provided between the first signal wiring layer and the first ground wiring layer. The second signal wiring layer has a second resistance between the first ground wiring layer and the power supply wiring layer, and the third signal wiring layer has a resistance between the first ground wiring layer and the first ground wiring layer. The fourth signal wiring layer has a third resistance between the second ground wiring layer and the power supply wiring layer, and has a fifth signal wiring between the second ground wiring layer and the power supply wiring layer. The layer has a fifth resistor between the second ground wiring layer and the first, second, third, fourth, and fifth resistors having a resistance value of 49.5 ohm to 60.000 ohm. Regulated to within 5 ohms.
【０００７】上記のように構成された本発明の多層回路
板は、それぞれ抵抗が共にＩｎｔｅｌが設定する４９．
５オーム〜６０．５オームの範囲内に保持されて、実質
上、反射指数は従来技術と比べて随分と低くなり、高速
シグナルの反射をかなり軽減、もしくは除去して、高速
シグナルの伝送に適する回路板を形成する。また、高速
シグナル反射が低減したことから、定常波の発生がなく
なり、磁束の反作用が高められて、電磁波障害を低める
ことができる。上記優点から高速シグナルレイアウトに
適して、現在の工業が高速シグナルへと発展している傾
向に対応でき、かつインピーダンス整合のために、シグ
ナル配線層のトレース幅を変える必要がない。In the multilayer circuit board of the present invention configured as described above, each of the resistors is set by Intel.
Maintained within the range of 5 ohms to 60.5 ohms, the reflection index is substantially lower than in the prior art, significantly reducing or eliminating the reflection of high speed signals, making it suitable for high speed signal transmission. Form a circuit board. In addition, since the high-speed signal reflection is reduced, the generation of the standing wave is eliminated, the reaction of the magnetic flux is increased, and the electromagnetic interference can be reduced. From the above advantages, it is suitable for a high-speed signal layout, can cope with the tendency of the current industry to develop a high-speed signal, and does not need to change the trace width of a signal wiring layer for impedance matching.
【０００８】[0008]
【発明の実施の形態】以下、本発明を実施の形態に基づ
いて具体的に説明するが、本発明はこの例だけに限定さ
れるものではない。図１〜３に示す如く、本発明に係る
１．２ｍｍの厚さの多層回路板２の比較的好ましい第１
の実施例は、順に上から下へと互いに重畳配設される第
１、第２、第３、第４、第５、第６および第７の絶縁基
板（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ５、Ｂ６およびＢ７）
を含んで、第１のシグナル配線層（Ｓ１）が第１の絶縁
基板（Ｂ１）の第２の絶縁基板（Ｂ２）と相対する向き
の反対側の面に配置され、第１の接地配線層（ＧＮＤ
１）が第１と第２の絶縁基板（Ｂ１、Ｂ２）の間に配設
され、第２のシグナル配線層（Ｓ２）が第２と第３の絶
縁基板（Ｂ２、Ｂ３）の間に配設され、第３のシグナル
配線層（Ｓ３）が第３と第４の絶縁基板（Ｂ３、Ｂ４）
の間に配設され、電源配線層（ＰＯＷＥＲ）が第４と第
５の絶縁基板（Ｂ４、Ｂ５）の間に配設され、第４のシ
グナル配線層（Ｓ４）が第５と第６の絶縁基板（Ｂ５、
Ｂ６）の間に配設され、第２の接地配線層（ＧＮＤ２）
が第６と第７の絶縁基板（Ｂ６、Ｂ７）の間に配設さ
れ、第５のシグナル配線層（Ｓ５）が第７の絶縁基板
（Ｂ７）の第６の絶縁基板（Ｂ６）と相対する向きの反
対側の面に配設されて、第１、第２、第３、第４および
第５のシグナル配線層（Ｓ１、Ｓ２、Ｓ３、Ｓ４および
Ｓ５）は通常銅金属コイルによって造られ、第１および
第５のシグナル配線層（Ｓ１、Ｓ５）により電子部材
（図示せず）に装設される。該第１、第３、第５、第７
の絶縁基板（Ｂ１、Ｂ３、Ｂ５およびＢ７）の少なくと
もいずれかがポリエステルプリプレグによって造られ、
該第２、第４、第６の絶縁基板（Ｂ２、Ｂ４、Ｂ６）の
少なくともいずれかが紙あるいはガラス繊維を含んだ繊
維質心材によって造られる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described based on embodiments, but the present invention is not limited to these examples. As shown in FIGS. 1-3, a relatively preferred first circuit board 2 of 1.2 mm thickness according to the present invention.
Of the first, second, third, fourth, fifth, sixth and seventh insulating substrates (B1, B2, B3, B4, B5) , B6 and B7)
The first signal wiring layer (S1) is disposed on the surface of the first insulating substrate (B1) opposite to the direction opposite to the second insulating substrate (B2), and the first ground wiring layer (GND
1) is disposed between the first and second insulating substrates (B1, B2), and the second signal wiring layer (S2) is disposed between the second and third insulating substrates (B2, B3). The third signal wiring layer (S3) is provided on the third and fourth insulating substrates (B3, B4).
The power supply wiring layer (POWER) is disposed between the fourth and fifth insulating substrates (B4, B5), and the fourth signal wiring layer (S4) is disposed between the fifth and sixth insulating substrates. Insulating substrate (B5,
B6), a second ground wiring layer (GND2)
Is disposed between the sixth and seventh insulating substrates (B6, B7), and the fifth signal wiring layer (S5) is positioned relative to the sixth insulating substrate (B6) of the seventh insulating substrate (B7). The first, second, third, fourth and fifth signal wiring layers (S1, S2, S3, S4 and S5), which are arranged on the opposite side of the direction of the The first and fifth signal wiring layers (S1, S5) are provided on an electronic member (not shown). The first, third, fifth, seventh
At least one of the insulating substrates (B1, B3, B5 and B7) is made of polyester prepreg,
At least one of the second, fourth, and sixth insulating substrates (B2, B4, B6) is made of a fibrous core material containing paper or glass fiber.
【０００９】本発明において、第１と第７の絶縁基板
（Ｂ１、Ｂ７）はそれぞれ２．５〜６．５ｍｉｌ範囲内
の厚さ（Ｈ４）を有し、第２および第６の絶縁基板（Ｂ
２、Ｂ６）はそれぞれ３ｍｉｌ〜９ｍｉｌの範囲内の厚
さ（Ｈ３）を有し、第３および第５の絶縁基板（Ｂ３、
Ｂ５）はそれぞれ３ｍｉｌ〜２３ ｍｉｌの範囲内の厚
さ（Ｈ２）を有し、第４の絶縁基板（Ｌ４）は３ｍｉｌ
〜９ｍｉｌの範囲内の厚さ（Ｈ２）を有している。好ま
しくは、第１および第７の絶縁基板（Ｂ１、Ｂ７）の厚
さ（Ｈ４）がそれぞれ等しく、第２および第６の絶縁基
板（Ｂ２、Ｂ６）の厚さ（Ｈ３）がそれぞれ等しく、第
３および第５の絶縁基板（Ｂ３、Ｂ５）の厚さ（Ｈ２）
がそれぞれ等しい。In the present invention, the first and seventh insulating substrates (B1, B7) each have a thickness (H4) in the range of 2.5 to 6.5 mils, and the second and sixth insulating substrates (B1, B7) each have a thickness (H4) of 2.5 to 6.5 mil. B
2, B6) each have a thickness (H3) in the range of 3 mil to 9 mil, and the third and fifth insulating substrates (B3,
B5) each have a thickness (H2) in the range of 3 mils to 23 mils, and the fourth insulating substrate (L4) has a thickness of 3 mils.
It has a thickness (H2) in the range of ９9 mil. Preferably, the first and seventh insulating substrates (B1, B7) have the same thickness (H4), and the second and sixth insulating substrates (B2, B6) have the same thickness (H3). Thickness (H2) of third and fifth insulating substrates (B3, B5)
Are equal.
【００１０】上記第１、第２、第３、第４、第５、第６
および第７の絶縁基板（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ
５、Ｂ６、Ｂ７）と、上記第１、第２、第３、第４およ
び第５のシグナル配線層（Ｓ１、Ｓ２、Ｓ３、Ｓ４、Ｓ
５）と、上記第１および第２の接地配線層（ＧＮＤ１、
ＧＮＤ２）と、上記電源配線層（ＰＯＷＥＲ）は、互い
にプレス接着して約１．２ｍｍの厚さの回路板２に形成
される。該回路板２をプレス接着する場合は、第３のシ
グナル配線層（Ｓ３）と電源配線層（ＰＯＷＥＲ）が第
４の絶縁基板（Ｂ４）を挟み付けるように配設され、つ
ぎに、第２のシグナル配線層（Ｓ２）と第３のシグナル
配線層（Ｓ３）、および第４のシグナル配線層（Ｓ４）
と電源配線層（ＰＯＷＥＲ）が、それぞれ第３および第
５の絶縁基板（Ｂ３、Ｂ５）を挟み付けるように配設さ
れ、さらに、第１の接地配線層（ＧＮＤ１）と第２のシ
グナル配線層（Ｓ２）、および第４のシグナル配線層
（Ｓ４）と第２の接地配線層（ＧＮＤ２）が、それぞれ
第２および第６の絶縁基板（Ｂ２、Ｂ６）を挟み付ける
ように配設され、最後に第１のシグナル配線層（Ｓ１）
と第１の接地配線層（ＧＮＤ１）、および第５のシグナ
ル配線層（Ｓ５）と第２の接地配線層（ＧＮＤ２）が、
それぞれ第１および第７の絶縁基板（Ｂ１、Ｂ７）を挟
み付けるように配設されて１．２ｍｍ多層回路板２を形
成する。The first, second, third, fourth, fifth, sixth
And a seventh insulating substrate (B1, B2, B3, B4, B
5, B6, B7) and the first, second, third, fourth and fifth signal wiring layers (S1, S2, S3, S4, S).
5) and the first and second ground wiring layers (GND1,
GND2) and the power supply wiring layer (POWER) are press-bonded to each other to form a circuit board 2 having a thickness of about 1.2 mm. When the circuit board 2 is press-bonded, the third signal wiring layer (S3) and the power supply wiring layer (POWER) are arranged so as to sandwich the fourth insulating substrate (B4). Signal wiring layer (S2), third signal wiring layer (S3), and fourth signal wiring layer (S4)
And a power supply wiring layer (POWER) are provided so as to sandwich the third and fifth insulating substrates (B3, B5), respectively, and further a first ground wiring layer (GND1) and a second signal wiring layer (S2), and the fourth signal wiring layer (S4) and the second ground wiring layer (GND2) are disposed so as to sandwich the second and sixth insulating substrates (B2, B6), respectively. First signal wiring layer (S1)
And a first ground wiring layer (GND1), and a fifth signal wiring layer (S5) and a second ground wiring layer (GND2).
The 1.2 mm multilayer circuit board 2 is formed so as to sandwich the first and seventh insulating substrates (B1, B7), respectively.
【００１１】上記の第１の実施例において、第１および
第５のシグナル配線層（Ｓ１、Ｓ５）は、それぞれ約
１．４ｍｉｌの厚さを有し、第２、第３および第４のシ
グナル配線層（Ｓ２、Ｓ３、Ｓ４）、第１および第２の
接地配線層（DND１、ＧＮＤ２）、ならびに電源配線層
（ＰＯＷＥＲ）は、それぞれ約０．７ｍｉｌの厚さを有
している。さらに、第３および第５の絶縁基板（Ｂ３、
Ｂ５）は、それぞれ好ましい３ｍｉｌ〜９ｍｉｌ範囲内
のより好ましい６ｍｉｌの厚さ（Ｈ２）を有し、第１お
よび第７の絶縁基板（Ｂ１、Ｂ７）は、それぞれ好まし
い４．５ｍｉｌの厚さ（Ｈ４）を有し、第２、第４およ
び第６の絶縁基板（Ｂ２、Ｂ４、Ｂ６）は、それぞれ好
ましい６ｍｉｌの厚さ（Ｈ３、Ｈ１）を有する。第１の
シグナル配線層（Ｓ１）は、第１の接地配線層（ＧＮＤ
１）との間に第１の抵抗（Ｒｓ１）を有し、第２のシグ
ナル配線層（Ｓ２）は、第１の接地配線層（ＧＮＤ１）
と電源配線層（ＰＯＷＥＲ）との間に第２の抵抗（Ｒｓ
２）を有し、第３のシグナル配線層（Ｓ３）は、第１の
接地配線層（ＧＮＤ１）と電源配線層（ＰＯＷＥＲ）と
の間に第３の抵抗（Ｒｓ３）を有し、第４のシグナル配
線層（Ｓ４）は、第２の接地配線層（ＧＮＤ２）と電源
配線層（ＰＯＷＥＲ）との間に第４の抵抗（Ｒｓ４）を
有し、第５のシグナル配線層（Ｓ５）は、第２の接地配
線層（ＧＮＤ２）との間に第５の抵抗（Ｒｓ５）を有す
る。これらの絶縁層（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ５、
Ｂ６およびＢ７）の厚さをそれぞれ上記範囲内にコント
ロールすると、第１、第２、第３、第４および第５の抵
抗（Ｒｓ１、Ｒｓ２、Ｒｓ３、Ｒｓ４およびＲｓ５）の
抵抗値をそれぞれ４９．５オーム〜６０．５オームの範
囲内に保持できて、インピーダンス整合の効果を達成す
る。In the first embodiment described above, the first and fifth signal wiring layers (S1, S5) each have a thickness of about 1.4 mil, and the second, third and fourth signal wiring layers have a thickness of about 1.4 mil. The wiring layers (S2, S3, S4), the first and second ground wiring layers (DND1, GND2), and the power supply wiring layer (POWER) each have a thickness of about 0.7 mil. Further, third and fifth insulating substrates (B3,
B5) each has a more preferred thickness of 6 mil (H2) in the preferred range of 3 mils to 9 mils, and the first and seventh insulating substrates (B1, B7) each have a preferred thickness of 4.5 mils (H4). ), And the second, fourth and sixth insulating substrates (B2, B4, B6) each have a preferred thickness (H3, H1) of 6 mil. The first signal wiring layer (S1) includes a first ground wiring layer (GND)
1) between the first ground wiring layer (GND1) and the second signal wiring layer (S2).
A second resistor (Rs) is provided between the power supply wiring layer (POWER) and a second resistor (Rs).
2), the third signal wiring layer (S3) has a third resistor (Rs3) between the first ground wiring layer (GND1) and the power supply wiring layer (POWER), and The signal wiring layer (S4) has a fourth resistor (Rs4) between the second ground wiring layer (GND2) and the power supply wiring layer (POWER), and the fifth signal wiring layer (S5) And a second ground wiring layer (GND2). These insulating layers (B1, B2, B3, B4, B5,
When the thicknesses of B6 and B7) are controlled within the above ranges, respectively, the resistance values of the first, second, third, fourth and fifth resistors (Rs1, Rs2, Rs3, Rs4 and Rs5) are respectively 49. It can be kept in the range of 5 ohm to 60.5 ohm to achieve the effect of impedance matching.
【００１２】続いて、各絶縁基板（Ｂ１、Ｂ２、Ｂ３、
Ｂ４、Ｂ５、Ｂ６およびＢ７）のそれぞれの厚さの概算
を下記の通りに説明する。まず、第１と第５の抵抗（Ｒ
ｓ１、Ｒｓ５）の抵抗値を次の式（１）で計算する。Subsequently, each of the insulating substrates (B1, B2, B3,
Estimation of the thickness of each of B4, B5, B6 and B7) is described as follows. First, the first and fifth resistors (R
s1, Rs5) are calculated by the following equation (1).
【数１】 ここで、ＥR は誘導係数で４．５であり、Ｈ４は第１と
第７の絶縁基板（Ｂ１、Ｂ７）の厚さであり、Ｗは第１
と第５のシグナル配線層（Ｓ１、Ｓ５）のトレース幅で
あって２ｍｉｌ〜８ｍｉｌの範囲内にあるが、本実施例
では５ｍｉｌになっており、Ｔ１は第１と第４のシグナ
ル配線層（Ｓ１、Ｓ４）の厚さであって１．４ｍｉｌで
ある。つぎに、第２と第３の抵抗（Ｒｓ２、Ｒｓ３）の
抵抗値を下記の式（２）および式（３）から得る。(Equation 1) Here, E R is an induction coefficient of 4.5, H4 is the thickness of the first and seventh insulating substrates (B1, B7), and W is the first
And the trace width of the fifth signal wiring layer (S1, S5) is in the range of 2 mil to 8 mil, but is 5 mil in this embodiment, and T1 is the first and fourth signal wiring layers (S1, S5). S1, S4), which is 1.4 mil. Next, the resistance values of the second and third resistors (Rs2, Rs3) are obtained from the following equations (2) and (3).
【数２】 (Equation 2)
【数３】 ここで、ＥR は誘導係数で４．５であり、Ｈ３は第２と
第６の絶縁基板（Ｂ２、Ｂ６）の厚さであって第４の絶
縁基板（Ｂ４）の厚さＨ１に等しい。さらに、Ｈ２は第
３と第５の絶縁基板（Ｂ３、Ｂ５）の厚さであり、Ｔ２
は第２のシグナル配線層（Ｓ２）の厚さであって０．７
ｍｉｌであり、また第３のシグナル配線層（Ｓ３）の厚
さでもある。Ｗは第２と第３のシグナル配線層（Ｓ２、
Ｓ３）のトレース幅であって２ｍｉｌ〜８ｍｉｌの範囲
内にあるが、本実施例では５ｍｉｌになっている。第４
の抵抗（Ｒｓ４）の抵抗値は下記の式（４）を使って得
られる。(Equation 3) Here, E R is an induction coefficient of 4.5, and H3 is the thickness of the second and sixth insulating substrates (B2, B6) and is equal to the thickness H1 of the fourth insulating substrate (B4). . H2 is the thickness of the third and fifth insulating substrates (B3, B5), and T2
Is the thickness of the second signal wiring layer (S2) and 0.7
mil and the thickness of the third signal wiring layer (S3). W represents the second and third signal wiring layers (S2,
The trace width of S3) is in the range of 2 mil to 8 mil, but is 5 mil in this embodiment. 4th
The resistance value of the resistor (Rs4) can be obtained using the following equation (4).
【数４】 ここで、ＥR は誘導係数で４．５であり、Ｈ３は第２と
第６の絶縁基板（Ｂ２、Ｂ６）の厚さであり、Ｈ２は第
３と第５の絶縁基板（Ｂ３、Ｂ５）の厚さであり、Ｔ２
は第４シグナル配線層（Ｓ４）の厚さであって０．７ｍ
ｉｌであり、Ｗは第４のシグナル配線層（Ｓ４）のトレ
ース幅であって２ｍｉｌ〜８ｍｉｌの範囲内にあるが、
本実施例では５ｍｉｌになっている。加えるに、回路板
の合計厚さは１．２ｍｍ（約４８ｍｉｌに相当する）、
あるいはその許容誤差範囲内に規制すべきで、下記の式
（５）によって表される。(Equation 4) Here, E R is an induction coefficient of 4.5, H3 is the thickness of the second and sixth insulating substrates (B2, B6), and H2 is the third and fifth insulating substrates (B3, B5). ) And T2
Is the thickness of the fourth signal wiring layer (S4), which is 0.7 m
il, and W is the trace width of the fourth signal wiring layer (S4), which is in the range of 2 mil to 8 mil,
In this embodiment, it is 5 mil. In addition, the total thickness of the circuit board is 1.2 mm (corresponding to about 48 mil),
Alternatively, it should be regulated within the allowable error range, and is represented by the following equation (5).
【数５】 この式（５）に基づいて、それぞれ絶縁基板の好ましい
厚さの値を得ることができる。すなわち、第４の絶縁基
板（Ｂ４）の厚さＨ１が３ｍｉｌ〜９ｍｉｌの範囲内に
ある場合は６ｍｉｌが好ましく、第３と第５の絶縁基板
（Ｂ３、Ｂ５）の厚さＨ２が３ｍｉｌ〜９ｍｉｌの範囲
内にある場合は６ｍｉｌが好ましく、第２と第６の絶縁
基板（Ｂ２、Ｂ６）の厚さＨ３が３ｍｉｌ〜９ｍｉｌの
範囲内にある場合は６ｍｉｌが好ましく、第１と第７の
絶縁基板（Ｂ１、Ｂ７）の厚さＨ４が２．５ｍｉｌ〜
６．５ｍｉｌの範囲内にある場合は４．５ｍｉｌが好ま
しい。この条件の下で、第１と第５の抵抗（Ｒｓ１、Ｒ
ｓ５）の抵抗値は略５８オームで、第２と第３の抵抗
（Ｒｓ２、Ｒｓ３）の抵抗値は略５７オームで、第４の
抵抗（Ｒｓ４）の抵抗値は略５０オームであり、これら
の抵抗値は全てＩｎｔｅｌが高速シグナル伝送のために
設定した理論範囲の４９．５オーム〜６０．５オーム内
にある。なお、前述の式（５）によって算出した回路板
２の厚さの総計は、２Ｈ４＋２Ｈ３＋２Ｈ２＋１Ｈ１＋
２Ｔ１＋６Ｔ２＝２×４．５ｍｉｌ＋２×６ｍｉｌ＋２
×６ｍｉｌ＋１×６ｍｉｌ＋２×１．４ｍｉｌ＋６×
０．７ｍｉｌ＝４６ｍｉｌ≒１．２ｍｍ（許容誤差の範
囲内）である。(Equation 5) Based on the equation (5), it is possible to obtain a preferable value of the thickness of each of the insulating substrates. That is, when the thickness H1 of the fourth insulating substrate (B4) is in the range of 3 mil to 9 mil, 6 mil is preferable, and the thickness H2 of the third and fifth insulating substrates (B3, B5) is 3 mil to 9 mil. 6 mil is preferable when the thickness is within the range, and 6 mil is preferable when the thickness H3 of the second and sixth insulating substrates (B2, B6) is within the range of 3 mil to 9 mil. The thickness H4 of the substrate (B1, B7) is 2.5 mil or more.
When it is within the range of 6.5 mil, 4.5 mil is preferable. Under this condition, the first and fifth resistors (Rs1, Rs1
s5) has a resistance of approximately 58 ohms, the second and third resistors (Rs2, Rs3) have a resistance of approximately 57 ohms, and the fourth resistor (Rs4) has a resistance of approximately 50 ohms. Are all within the theoretical range of 49.5 ohms to 60.5 ohms set by Intel for high-speed signal transmission. The total thickness of the circuit board 2 calculated by the above equation (5) is 2H4 + 2H3 + 2H2 + 1H1 +
2T1 + 6T2 = 2 × 4.5 mil + 2 × 6 mil + 2
× 6 mil + 1 × 6 mil + 2 × 1.4 mil + 6 ×
0.7 mil = 46 mil ≒ 1.2 mm (within allowable error).
【００１３】図４に示すのは、本発明に係る多層回路板
２’の比較的好ましい第２の実施例であり、この回路板
２’は図示の如く、第１、第２、第３、第４、第５、第
６および第７の絶縁基板（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ
５、Ｂ６、Ｂ７）と、第１、第２、第３、第４および第
５のシグナル配線層（Ｓ１、Ｓ２、Ｓ３、Ｓ４、Ｓ５）
と、第１および第２の接地配線層（ＧＮＤ１、ＧＮＤ
２）および電源配線層（ＰＯＷＥＲ）を含んで、それら
が互いにプレス接着して約１．６ｍｍ厚さの回路板２を
形成する。本実施例が上記第１の実施例と異なるところ
は、第３と第５の絶縁基板（Ｂ３’、Ｂ５’）がそれぞ
れ９ｍｉｌ〜２３ｍｉｌ範囲内の厚さ（Ｈ２）を有し
て、上記式に基づいて計算した結果、下記の好ましいＨ
１、Ｈ２、Ｈ３およびＨ４の値を得た。Ｈ１の好ましい
範囲は３ｍｉｌ〜９ｍｉｌで、より好ましくは６ｍｉｌ
であり、Ｈ２の好ましい範囲は９ｍｉｌ〜２３ｍｉｌ
で、より好ましくは１６ｍｉｌであり、Ｈ３の好ましい
範囲は３ｍｉｌ〜９ｍｉｌで、より好ましくは６ｍｉｌ
であり、Ｈ４の好ましい範囲は２．５ｍｉｌ〜６．５ｍ
ｉｌで、より好ましくは４．５ｍｉｌである。それによ
り、第１と第５の抵抗の抵抗値が６０オームで、第２と
第３の抵抗の抵抗値が約５５オーム、第４の抵抗の抵抗
値が約６０オームで、これらの抵抗値はいずれもＩｎｔ
ｅｌの決めた理論範囲内にある。FIG. 4 shows a second preferred embodiment of a multilayer circuit board 2 'according to the present invention, wherein the circuit board 2' comprises first, second, third, Fourth, fifth, sixth and seventh insulating substrates (B1, B2, B3, B4, B
5, B6, B7) and the first, second, third, fourth and fifth signal wiring layers (S1, S2, S3, S4, S5)
And first and second ground wiring layers (GND1, GND
2) and a power wiring layer (POWER), which are press bonded to each other to form a circuit board 2 having a thickness of about 1.6 mm. This embodiment differs from the first embodiment in that the third and fifth insulating substrates (B3 ′, B5 ′) each have a thickness (H2) in the range of 9 mil to 23 mil, and As a result of calculation based on
The values of 1, H2, H3 and H4 were obtained. The preferred range of H1 is 3 mil to 9 mil, more preferably 6 mil.
And the preferable range of H2 is 9 mil to 23 mil.
, More preferably 16 mil, and the preferred range of H3 is 3 mil to 9 mil, more preferably 6 mil.
And the preferable range of H4 is 2.5 mil to 6.5 m.
il, more preferably 4.5 mil. Accordingly, the resistance values of the first and fifth resistors are 60 ohms, the resistance values of the second and third resistors are about 55 ohms, and the resistance values of the fourth resistor are about 60 ohms. Are all Int
It is within the theoretical range determined by el.
【００１４】[0014]
【発明の効果】したがって、本発明の多層回路板は下記
の優点・効果を有している。 １）高速シグナル反射が低減する。第１および第２の実
施例のそれぞれの抵抗が共に５５オーム±１０％の設定
範囲内にあって、反射指数が従来技術と比べて随分と低
くなり、高速シグナルの反射をかなり軽減、若しくは除
去して、高速シグナルの伝送に適する回路板を形成でき
る。 ２）電磁波障害が軽減する。高速シグナル反射が低減し
たため、定常波の発生がなくなり、磁束の反作用が高め
られて、電磁波障害を低め、現在のＥＭＩ標準に符合で
きる。 ３）高速シグナルのレイアウトへの適応性が優れてい
る。上記優点から本発明の回路板は高速シグナルレイア
ウトに適して、現在の業が高速シグナルへと発展してい
る傾向に対応し、製品の市場価格や競争力を高める。 ４）レイアウトの時効性が向上する。インピーダンス整
合のために、シグナル配線層のトレース幅を変える必要
がなく、レイアウトの時効性を促進する。Accordingly, the multilayer circuit board of the present invention has the following advantages and effects. 1) Fast signal reflection is reduced. The respective resistances of the first and second embodiments are both within the setting range of 55 ohms ± 10%, the reflection index is considerably lower than that of the prior art, and the reflection of high-speed signals is considerably reduced or eliminated. Thus, a circuit board suitable for high-speed signal transmission can be formed. 2) Electromagnetic interference is reduced. Due to the reduced high-speed signal reflection, the generation of the standing wave is eliminated, the reaction of the magnetic flux is enhanced, the electromagnetic wave interference is reduced, and the current EMI standard can be met. 3) Excellent adaptability to high-speed signal layout. Due to the above advantages, the circuit board of the present invention is suitable for a high-speed signal layout, responds to the tendency of the current industry to develop a high-speed signal, and increases the market price and competitiveness of products. 4) The aging effect of the layout is improved. It is not necessary to change the trace width of the signal wiring layer for impedance matching, which promotes the aging effect of the layout.
【図１】本発明に係る比較的好ましい第１の実施例にお
ける１．２ｍｍの厚さの多層回路板の概略図である。FIG. 1 is a schematic view of a 1.2 mm thick multilayer circuit board in a first preferred embodiment according to the present invention.
【図２】第１の実施例の部分断面図である。FIG. 2 is a partial cross-sectional view of the first embodiment.
【図３】第１の実施例の他の部分断面図である。FIG. 3 is another partial sectional view of the first embodiment.
【図４】本発明に係る比較的好ましい第２の実施例にお
ける１．６ｍｍの厚さの多層回路板の概略図である。FIG. 4 is a schematic diagram of a 1.6 mm thick multilayer circuit board in a second preferred embodiment according to the present invention.
【図５】従来の１．２ｍｍの厚さの多層回路板の概略図
である。FIG. 5 is a schematic view of a conventional multilayer circuit board having a thickness of 1.2 mm.
【図６】従来の１．６ｍｍの厚さの多層回路板の概略図
である。FIG. 6 is a schematic view of a conventional multilayer circuit board having a thickness of 1.6 mm.
Ｂ１、Ｂ２、Ｂ３．Ｂ４、Ｂ５、Ｂ６およびＢ７…第
１、第２、第３、第４、第５、第６および第７の絶縁基
板 Ｓ１、Ｓ２、Ｓ３、Ｓ４およびＳ５…第１、第２、第
３、第４および第５のシグナル配線層 ＧＮＤ１、ＧＮＤ２…第１および第２の接地配線層 Ｈ１…第４の絶縁基板の厚さ Ｈ２…第３の絶縁基板の厚さ、および第５の絶縁基板の
厚さ Ｈ３…第２の絶縁基板の厚さ、および第６の絶縁基板の
厚さ Ｈ４…第１の絶縁基板の厚さ、および第７の絶縁基板の
厚さ Ｒｓ１、Ｒｓ２、Ｒｓ３、Ｒｓ４およびＲｓ５…第１、
第２、第３、第４および第５の抵抗B1, B2, B3. B4, B5, B6 and B7 ... first, second, third, fourth, fifth, sixth and seventh insulating substrates S1, S2, S3, S4 and S5 ... first, second, third, Fourth and fifth signal wiring layers GND1, GND2... First and second ground wiring layers H1... Thickness of fourth insulating substrate H2... Thickness of third insulating substrate and fifth insulating substrate Thickness H3: thickness of the second insulating substrate, and thickness of the sixth insulating substrate H4: thickness of the first insulating substrate, and thickness of the seventh insulating substrate Rs1, Rs2, Rs3, Rs4 and Rs5 ... first,
Second, third, fourth and fifth resistors
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成１３年４月１２日（２００１．４．１
２）[Submission date] April 12, 2001 (2001.4.1
2)
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】全文[Correction target item name] Full text
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【書類名】 明細書[Document Name] Statement
【発明の名称】 多層回路板[Title of the Invention] Multilayer circuit board
【特許請求の範囲】[Claims]
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は多層回路板に関し、
特にインピーダンス整合を達成できて、高速シグナル反
射（すなわち、高速信号反射）および電磁波障害を軽減
できる多層回路板に関する。The present invention relates to a multilayer circuit board,
In particular, the present invention relates to a multilayer circuit board capable of achieving impedance matching and reducing high-speed signal reflection (that is, high-speed signal reflection) and electromagnetic interference.
【０００２】[0002]
【従来の技術】工業規格によれば、８配線層の多層回路
板は、通常１．２ｍｍ型と１．６ｍｍ型を含む。図５に
示すのは約１．２ｍｍの厚さの多層回路板であり、連続
的に互いに上下積層して配置される第１、第２、第３、
第４、第５、第６、および第７の絶縁基板（Ａ１、Ａ
２、Ａ３、Ａ４、Ａ５、Ａ６およびＡ７）を含み、第１
のシグナル配線層（Ｓ１）が第１の絶縁基板（Ａ１）の
第２の絶縁基板（Ａ２）と相対する向きの反対側の面に
配置されて、第１の接地配線層（ＧＮＤ１）が第１と第
２の絶縁基板（Ａ１、Ａ２）の間に設けられ、第２のシ
グナル配線層（Ｓ２）が第２と第３の絶縁基板（Ａ２、
Ａ３）の間に配設され、第２のシグナル配線層（Ｓ３）
が第３と第４の絶縁基板（Ａ３、Ａ４）の間に設けら
れ、電源配線層（ＰＯＷＥＲ）が第４と第５の絶縁基板
（Ａ４、Ａ５）の間に配設され、第４のシグナル配線層
（Ｓ４）が第５と第６の絶縁基板（Ａ５、Ａ６）の間に
設けられ、第２の接地配線層（ＧＮＤ２）が第６と第７
の絶縁基板（Ａ６、Ａ７）の間に配設され、第５のシグ
ナル配線層（Ｓ５）が第７の絶縁基板（Ａ７）の第６の
絶縁基板（Ａ６）と相対する向きの反対側の面に設けら
れる。該第１、第３、第５および第７の絶縁基板（Ａ
１、Ａ３、Ａ５およびＡ７）はそれぞれポリエステルプ
リプレグによって形成され、第２、第４および第６の絶
縁基板（Ａ２、Ａ４およびＡ６）はそれぞれ紙あるいは
ガラス繊維を含んだ繊維質心材によって造られる。2. Description of the Related Art According to industry standards, a multilayer circuit board having eight wiring layers usually includes a 1.2 mm type and a 1.6 mm type. FIG. 5 shows a multilayer circuit board having a thickness of about 1.2 mm, in which first, second, third,
Fourth, fifth, sixth, and seventh insulating substrates (A1, A
2, A3, A4, A5, A6 and A7), the first
Is arranged on the surface of the first insulating substrate (A1) on the opposite side to the direction facing the second insulating substrate (A2), and the first ground wiring layer (GND1) is The second signal wiring layer (S2) is provided between the first and second insulating substrates (A1, A2) and the second and third insulating substrates (A2,
A3), a second signal wiring layer (S3)
Is provided between the third and fourth insulating substrates (A3, A4), and the power supply wiring layer (POWER) is provided between the fourth and fifth insulating substrates (A4, A5). A signal wiring layer (S4) is provided between the fifth and sixth insulating substrates (A5, A6), and a second ground wiring layer (GND2) is provided between the fifth and sixth insulating substrates (A5, A6).
And a fifth signal wiring layer (S5) on the opposite side of the direction in which the seventh insulating substrate (A7) faces the sixth insulating substrate (A6). Provided on the surface. The first, third, fifth and seventh insulating substrates (A
1, A3, A5, and A7) are each formed of a polyester prepreg, and the second, fourth, and sixth insulating substrates (A2, A4, and A6) are each formed of a fibrous core containing paper or glass fiber.
【０００３】さらに、第１および第７の絶縁基板（Ａ
１、Ａ７）はそれぞれ約６３．５μｍ（約２．５ｍｉ
ｌ）（１ｍｉｌ＝０．０２５４ｍｍ＝２５．４μｍの関
係になっている）の厚さ（Ｈ４）を有し、第２および第
６の絶縁基板（Ａ２、Ａ６）はそれぞれ約２０３．２μ
ｍの厚さ（Ｈ３）を有し、第３および第５の絶縁基板
（Ａ３、Ａ５）はそれぞれ約１２７μｍの厚さ（Ｈ２）
を有し、第４の絶縁基板（Ａ４）は約２０３．２μｍの
厚さ（Ｈ１）を有する。第１のシグナル配線層（Ｓ１）
は、第１の接地配線層（ＧＮＤ１）との間に第１の抵抗
（Ｒｓ１）を有し、第２のシグナル配線層（Ｓ２）は、
第１の接地配線層（ＧＮＤ１）と電源配線層（ＰＯＷＥ
Ｒ）との間に第２の抵抗（Ｒｓ２）を有し、第３のシグ
ナル配線層（Ｓ３）は、第１の接地配線層（ＧＮＤ１）
と電源配線層（ＰＯＷＥＲ）との間に第３の抵抗（Ｒｓ
３）を有して、第４のシグナル配線層（Ｓ４）は、第２
の接地配線層（ＧＮＤ２）と電源配線層（ＰＯＷＥＲ）
との間に第４の抵抗（Ｒｓ４）を有し、第５のシグナル
配線層（Ｓ５）は、第２の接地配線層（ＧＮＤ２）との
間に第５の抵抗（Ｒｓ５）を有する。そのうち、第１お
よび第５の抵抗（Ｒｓ１、Ｒｓ５）の抵抗値は約４４オ
ーム（Ωとも記す）で、第２、第３および第４の抵抗
（Ｒｓ２、Ｒｓ３およびＲｓ４）の抵抗値は約５１オー
ムである。Further, first and seventh insulating substrates (A
1, A7) are each about 63.5 μm (about 2.5 mi )
l ) ( 1 mil = 0.0254 mm = 25.4 μm) and the second and sixth insulating substrates (A2, A6) each have a thickness of about 203.2 μm.
m , and the third and fifth insulating substrates (A3, A5) each have a thickness (H2) of about 127 μm.
And the fourth insulating substrate (A4) has a thickness (H1) of about 203.2 μm. First signal wiring layer (S1)
Has a first resistance (Rs1) between the first ground wiring layer (GND1) and the second signal wiring layer (S2).
A first ground wiring layer (GND1) and a power supply wiring layer (POWE)
R) between the first ground wiring layer (GND1) and the second signal wiring layer (S3).
A third resistor (Rs) is provided between the power supply wiring layer (POWER) and a third resistor (Rs).
3), the fourth signal wiring layer (S4) is
Ground wiring layer (GND2) and power supply wiring layer (POWER)
And the fifth signal wiring layer (S5) has a fifth resistance (Rs5) between itself and the second ground wiring layer (GND2). The resistance of the first and fifth resistors (Rs1, Rs5) is about 44 ohms (also referred to as Ω), and the resistance of the second, third, and fourth resistors (Rs2, Rs3, and Rs4) is about 44 ohms. It is 51 ohms.
【０００４】図６に示すのは、従来の約１．６ｍｍの厚
さの多層回路板であり、上記１．２ｍｍ回路板と異なる
ところは上記Ｈ４が６３．５μｍでなく２４１．３μｍ
で、その結果、第１および第５の抵抗（Ｒｓ１、Ｒｓ
５）の抵抗値が約７６．４オームである。これらの構成
のため、図５および図６に示す従来の多層回路板は下記
の欠点がある。 （ｉ）重大な高速シグナル反射がある。Ｉｎｔｅｌの設
定した標準理論値によれば、高速シグナル伝送の際にお
ける回路板の両隣接配線層間の抵抗値は５５＋１０％オ
ームの範囲、例えば４９．５オーム〜６０．５オームが
最も好ましいが、上記従来の１．２ｍｍ回路板の第１お
よび第５の抵抗（Ｒｓ１、Ｒｓ５）の抵抗値は約４４オ
ームで、Ｉｎｔｅｌの勧める好ましい範囲外にあって、
加えるに第１および第５の抵抗（Ｒｓ１、Ｒｓ５）の抵
抗値と第２、第３および第４の抵抗（Ｒｓ２、Ｒｓ３お
よびＲｓ４）の抵抗値との間に７オームの違いがあり、
この違いがインピーダンスの不釣合いを形成する。この
ように、高速シグナルが従来の１．２ｍｍ回路板を伝送
通過して、第１あるいは第５のシグナル配線層（Ｓ１、
またはＳ５）を経由して第２、第３あるいは第４のシグ
ナル配線層（Ｓ２、Ｓ３、またはＳ４）に至ると、シグ
ナルが反射を生じ、それによって、シグナルが逆反射伝
送をする。同様に、上記従来の１．６ｍｍ回路板の第１
および第５の抵抗（Ｒｓ１、Ｒｓ５）の抵抗値も理論範
囲外に陥り、第１および第５の抵抗（Ｒｓ１、Ｒｓ５）
の抵抗値と第２、第３および第４の抵抗（Ｒｓ２、Ｒｓ
３、Ｒｓ４）の抵抗値との間に大きな違いがある。それ
によりシグナル反射の問題が極めて重大となる。１．２
ｍｍ回路板の高速シグナルの反射指数は下記のように計
算できる。 Ｐ＝（Ｚ１−Ｚ０）/（Ｚ１＋Ｚ０）＝（Ｒｓ１−Ｒｓ
２）/（Ｒｓ１＋Ｒｓ２）＝０．０７ １．６ｍｍ回路板の反射指数も類似の方式で計算でき
て、さらに高い０．２である。それによりシグナル反射
の問題が極めて重大になり、波形を歪めてシグナルの品
質が悪化する。 （ｉｉ）磁束の反作用力が弱められる。高速シグナルの
反射によって定常波が生ずると、高速シグナルの電磁輻
射が増大して、回路板の磁束の反作用力が弱められ、か
なり高電磁波障害が発生する。FIG. 6 shows a conventional multi-layer circuit board having a thickness of about 1.6 mm. The difference from the above-described 1.2 mm circuit board is that the H4 is 241.3 μm instead of 63.5 μm.
As a result, the first and fifth resistors (Rs1, Rs1
5) The resistance value is about 76.4 ohms. Due to these configurations, the conventional multilayer circuit boards shown in FIGS. 5 and 6 have the following disadvantages. (I) There is significant fast signal reflection. According to the standard theoretical value set by Intel, the resistance value between both adjacent wiring layers of the circuit board during high-speed signal transmission is most preferably in the range of 55 + 10% ohm, for example, 49.5 ohm to 60.5 ohm. The resistance of the first and fifth resistors (Rs1, Rs5) of the conventional 1.2 mm circuit board is about 44 ohms, which is outside the preferred range recommended by Intel,
In addition, there is a 7 ohm difference between the resistance of the first and fifth resistors (Rs1, Rs5) and the resistance of the second, third and fourth resistors (Rs2, Rs3 and Rs4),
This difference forms an impedance imbalance. As described above, the high-speed signal is transmitted and transmitted through the conventional 1.2 mm circuit board, and the first or fifth signal wiring layer (S1,
Alternatively, when the signal reaches the second, third, or fourth signal wiring layer (S2, S3, or S4) via S5), the signal reflects, whereby the signal performs retroreflective transmission. Similarly, the first of the above conventional 1.6 mm circuit boards.
Also, the resistance values of the fifth and fifth resistors (Rs1, Rs5) fall outside the theoretical range, and the first and fifth resistors (Rs1, Rs5)
And the second, third and fourth resistors (Rs2, Rs
3, there is a great difference between Rs4) and the resistance value. This makes the problem of signal reflection extremely critical. 1.2
The reflection index of the high speed signal of the mm circuit board can be calculated as follows. P = (Z1-Z0) / (Z1 + Z0) = (Rs1-Rs
2) / (Rs1 + Rs2) = 0.07 The reflection index of a 1.6 mm circuit board can be calculated in a similar manner, and is even higher, 0.2. This makes the problem of signal reflection very serious, distorting the waveform and deteriorating the signal quality. (Ii) The reaction force of the magnetic flux is weakened. When a standing wave is generated by the reflection of the high-speed signal, the electromagnetic radiation of the high-speed signal increases, the reaction force of the magnetic flux of the circuit board is weakened, and a considerably high electromagnetic wave disturbance occurs.
【０００５】[0005]
【発明が解決しようとする課題】それゆえに、本発明
は、インピーダンス整合を達成できて、高速シグナル反
射および電磁波障害を軽減できる多層回路板を提供する
ことを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multilayer circuit board that can achieve impedance matching and reduce high-speed signal reflection and electromagnetic interference.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明の多層回路板は、上から下へと順に重畳配置
される第１、第２、第３、第４、第５、第６および第７
の絶縁基板を含んで、第１のシグナル配線層が第１の絶
縁基板の第２の絶縁基板と相対する向きの反対側の面に
配置され、第１の接地配線層が第１の絶縁基板と第２の
絶縁基板との間に配設され、第２のシグナル配線層が第
２の絶縁基板と第３の絶縁基板との間に配設され、第３
シグナル配線層が第３の絶縁基板と第４の絶縁基板との
間に配設され、電源配線層が第４の絶縁基板と第５の絶
縁基板との間に配設され、第４のシグナル配線層が第５
の絶縁基板と第６の絶縁基板との間に配設され、第２の
接地配線層が第６の絶縁基板と第７の絶縁基板との間に
配設され、第５のシグナル配線層が第７の絶縁基板の第
６の絶縁基板と相対する向きの反対側の面に配設され
て、第１および第７の絶縁基板の厚さがそれぞれ６３．
５〜１６５．１μｍの範囲内にあり、第２、第４および
第６の絶縁基板の厚さがそれぞれ７６．２〜２２８．６
μｍの範囲内にあり、第３および第５の絶縁基板の厚さ
がそれぞれ７６．２〜５８４．２μｍの範囲内にあり、
第１のシグナル配線層は、第１の接地配線層との間に第
１の抵抗を有し、第２のシグナル配線層は、第１の接地
配線層と電源配線層との間に第２の抵抗を有し、第３の
シグナル配線層は、第１の接地配線層と電源配線層との
間に第３の抵抗を有し、第４のシグナル配線層は、第２
の接地配線層と電源配線層との間に第４の抵抗を有し、
第５のシグナル配線層は、第２の接地配線層との間に第
５の抵抗を有すると共に、これらの第１、第２、第３、
第４および第５の抵抗の抵抗値は４９．５オーム〜６
０．５オームの範囲内に規制される。In order to achieve the above object, a multilayer circuit board according to the present invention comprises first, second, third, fourth, fifth and fifth layers which are superposed and arranged in order from top to bottom. 6th and 7th
The first signal wiring layer is disposed on the surface of the first insulating substrate opposite to the direction facing the second insulating substrate, and the first ground wiring layer is formed on the first insulating substrate. A second signal wiring layer disposed between the second insulating substrate and the third insulating substrate; and a third signal wiring layer disposed between the second insulating substrate and the third insulating substrate.
A signal wiring layer is provided between the third insulating substrate and the fourth insulating substrate, a power wiring layer is provided between the fourth insulating substrate and the fifth insulating substrate, and a fourth signal wiring layer is provided. 5th wiring layer
The second ground wiring layer is disposed between the sixth insulating substrate and the seventh insulating substrate, and the fifth signal wiring layer is disposed between the sixth insulating substrate and the sixth insulating substrate. The first and seventh insulating substrates are disposed on a surface of the seventh insulating substrate opposite to the direction facing the sixth insulating substrate, and each of the first and seventh insulating substrates has a thickness of 63.
The thickness of the second, fourth, and sixth insulating substrates is 76.2 to 228.6, respectively .
μm , and the thicknesses of the third and fifth insulating substrates are respectively within the range of 76.2 to 584.2 μm,
The first signal wiring layer has a first resistance between the first ground wiring layer and the first signal wiring layer, and the second signal wiring layer has a second resistance between the first ground wiring layer and the power supply wiring layer. , The third signal wiring layer has a third resistance between the first ground wiring layer and the power supply wiring layer, and the fourth signal wiring layer has a second resistance
Having a fourth resistor between the ground wiring layer and the power supply wiring layer,
The fifth signal wiring layer has a fifth resistance between the fifth signal wiring layer and the second ground wiring layer, and has the first, second, third,
The resistance values of the fourth and fifth resistors are 49.5 ohm to 6
Regulated to within 0.5 ohm.
【０００７】上記のように構成された本発明の多層回路
板は、それぞれ抵抗が共にＩｎｔｅｌが設定する４９．
５オーム〜６０．５オームの範囲内に保持されて、実質
上、反射指数は従来技術と比べて随分と低くなり、高速
シグナルの反射をかなり軽減、もしくは除去して、高速
シグナルの伝送に適する回路板を形成する。また、高速
シグナル反射が低減したことから、定常波の発生がなく
なり、磁束の反作用が高められて、電磁波障害を低める
ことができる。上記優点から高速シグナルレイアウトに
適して、現在の工業が高速シグナルへと発展している傾
向に対応でき、かつインピーダンス整合のために、シグ
ナル配線層のトレース幅を変える必要がない。In the multilayer circuit board of the present invention configured as described above, each of the resistors is set by Intel.
Maintained within the range of 5 ohms to 60.5 ohms, the reflection index is substantially lower than in the prior art, significantly reducing or eliminating the reflection of high speed signals, making it suitable for high speed signal transmission. Form a circuit board. In addition, since the high-speed signal reflection is reduced, the generation of the standing wave is eliminated, the reaction of the magnetic flux is increased, and the electromagnetic interference can be reduced. From the above advantages, it is suitable for a high-speed signal layout, can cope with the tendency of the current industry to develop a high-speed signal, and does not need to change the trace width of a signal wiring layer for impedance matching.
【０００８】[0008]
【発明の実施の形態】以下、本発明を実施の形態に基づ
いて具体的に説明するが、本発明はこの例だけに限定さ
れるものではない。図１〜３に示す如く、本発明に係る
１．２ｍｍの厚さの多層回路板２の比較的好ましい第１
の実施例は、順に上から下へと互いに重畳配設される第
１、第２、第３、第４、第５、第６および第７の絶縁基
板（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ５、Ｂ６およびＢ７）
を含んで、第１のシグナル配線層（Ｓ１）が第１の絶縁
基板（Ｂ１）の第２の絶縁基板（Ｂ２）と相対する向き
の反対側の面に配置され、第１の接地配線層（ＧＮＤ
１）が第１と第２の絶縁基板（Ｂ１、Ｂ２）の間に配設
され、第２のシグナル配線層（Ｓ２）が第２と第３の絶
縁基板（Ｂ２、Ｂ３）の間に配設され、第３のシグナル
配線層（Ｓ３）が第３と第４の絶縁基板（Ｂ３、Ｂ４）
の間に配設され、電源配線層（ＰＯＷＥＲ）が第４と第
５の絶縁基板（Ｂ４、Ｂ５）の間に配設され、第４のシ
グナル配線層（Ｓ４）が第５と第６の絶縁基板（Ｂ５、
Ｂ６）の間に配設され、第２の接地配線層（ＧＮＤ２）
が第６と第７の絶縁基板（Ｂ６、Ｂ７）の間に配設さ
れ、第５のシグナル配線層（Ｓ５）が第７の絶縁基板
（Ｂ７）の第６の絶縁基板（Ｂ６）と相対する向きの反
対側の面に配設されて、第１、第２、第３、第４および
第５のシグナル配線層（Ｓ１、Ｓ２、Ｓ３、Ｓ４および
Ｓ５）は通常銅金属コイルによって造られ、第１および
第５のシグナル配線層（Ｓ１、Ｓ５）により電子部材
（図示せず）に装設される。該第１、第３、第５、第７
の絶縁基板（Ｂ１、Ｂ３、Ｂ５およびＢ７）の少なくと
もいずれかがポリエステルプリプレグによって造られ、
該第２、第４、第６の絶縁基板（Ｂ２、Ｂ４、Ｂ６）の
少なくともいずれかが紙あるいはガラス繊維を含んだ繊
維質心材によって造られる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described based on embodiments, but the present invention is not limited to these examples. As shown in FIGS. 1-3, a relatively preferred first circuit board 2 of 1.2 mm thickness according to the present invention.
Of the first, second, third, fourth, fifth, sixth and seventh insulating substrates (B1, B2, B3, B4, B5) , B6 and B7)
The first signal wiring layer (S1) is disposed on the surface of the first insulating substrate (B1) opposite to the direction opposite to the second insulating substrate (B2), and the first ground wiring layer (GND
1) is disposed between the first and second insulating substrates (B1, B2), and the second signal wiring layer (S2) is disposed between the second and third insulating substrates (B2, B3). The third signal wiring layer (S3) is provided on the third and fourth insulating substrates (B3, B4).
The power supply wiring layer (POWER) is disposed between the fourth and fifth insulating substrates (B4, B5), and the fourth signal wiring layer (S4) is disposed between the fifth and sixth insulating substrates. Insulating substrate (B5,
B6), a second ground wiring layer (GND2)
Is disposed between the sixth and seventh insulating substrates (B6, B7), and the fifth signal wiring layer (S5) is positioned relative to the sixth insulating substrate (B6) of the seventh insulating substrate (B7). The first, second, third, fourth and fifth signal wiring layers (S1, S2, S3, S4 and S5), which are arranged on the opposite side of the direction of the The first and fifth signal wiring layers (S1, S5) are provided on an electronic member (not shown). The first, third, fifth, seventh
At least one of the insulating substrates (B1, B3, B5 and B7) is made of polyester prepreg,
At least one of the second, fourth, and sixth insulating substrates (B2, B4, B6) is made of a fibrous core material containing paper or glass fiber.
【０００９】本発明において、第１と第７の絶縁基板
（Ｂ１、Ｂ７）はそれぞれ６３．５〜１６５．１μｍの
範囲内の厚さ（Ｈ４）を有し、第２および第６の絶縁基
板（Ｂ２、Ｂ６）はそれぞれ７６．２〜２２８．６μｍ
の範囲内の厚さ（Ｈ３）を有し、第３および第５の絶縁
基板（Ｂ３、Ｂ５）はそれぞれ７６．２〜５８４．２μ
ｍの範囲内の厚さ（Ｈ２）を有し、第４の絶縁基板（Ｌ
４）は７６．２〜２２８．６μｍの範囲内の厚さ（Ｈ
２）を有している。好ましくは、第１および第７の絶縁
基板（Ｂ１、Ｂ７）の厚さ（Ｈ４）がそれぞれ等しく、
第２および第６の絶縁基板（Ｂ２、Ｂ６）の厚さ（Ｈ
３）がそれぞれ等しく、第３および第５の絶縁基板（Ｂ
３、Ｂ５）の厚さ（Ｈ２）がそれぞれ等しい。In the present invention, the first and seventh insulating substrates (B1, B7) each have a thickness (H4) within the range of 63.5 to 165.1 μm, and the second and the seventh insulating substrates (B1, B7) each have a thickness (H4). No. 6 insulating substrates (B2, B6) were 76.2 to 228.6 μm, respectively .
And the third and fifth insulating substrates (B3, B5) have a thickness (H3) in the range of 76.2 to 584.2 μm, respectively .
m in the range (H2) and the fourth insulating substrate (L
4) has a thickness (H) in the range of 76.2 to 228.6 μm.
2). Preferably, the thicknesses (H4) of the first and seventh insulating substrates (B1, B7) are respectively equal,
The thickness (H) of the second and sixth insulating substrates (B2, B6)
3) are equal to each other, and the third and fifth insulating substrates (B
3, B5) have the same thickness (H2).
【００１０】上記第１、第２、第３、第４、第５、第６
および第７の絶縁基板（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ
５、Ｂ６、Ｂ７）と、上記第１、第２、第３、第４およ
び第５のシグナル配線層（Ｓ１、Ｓ２、Ｓ３、Ｓ４、Ｓ
５）と、上記第１および第２の接地配線層（ＧＮＤ１、
ＧＮＤ２）と、上記電源配線層（ＰＯＷＥＲ）は、互い
にプレス接着して約１．２ｍｍの厚さの回路板２に形成
される。該回路板２をプレス接着する場合は、第３のシ
グナル配線層（Ｓ３）と電源配線層（ＰＯＷＥＲ）が第
４の絶縁基板（Ｂ４）を挟み付けるように配設され、つ
ぎに、第２のシグナル配線層（Ｓ２）と第３のシグナル
配線層（Ｓ３）、および第４のシグナル配線層（Ｓ４）
と電源配線層（ＰＯＷＥＲ）が、それぞれ第３および第
５の絶縁基板（Ｂ３、Ｂ５）を挟み付けるように配設さ
れ、さらに、第１の接地配線層（ＧＮＤ１）と第２のシ
グナル配線層（Ｓ２）、および第４のシグナル配線層
（Ｓ４）と第２の接地配線層（ＧＮＤ２）が、それぞれ
第２および第６の絶縁基板（Ｂ２、Ｂ６）を挟み付ける
ように配設され、最後に第１のシグナル配線層（Ｓ１）
と第１の接地配線層（ＧＮＤ１）、および第５のシグナ
ル配線層（Ｓ５）と第２の接地配線層（ＧＮＤ２）が、
それぞれ第１および第７の絶縁基板（Ｂ１、Ｂ７）を挟
み付けるように配設されて１．２ｍｍ多層回路板２を形
成する。The first, second, third, fourth, fifth, sixth
And a seventh insulating substrate (B1, B2, B3, B4, B
5, B6, B7) and the first, second, third, fourth and fifth signal wiring layers (S1, S2, S3, S4, S).
5) and the first and second ground wiring layers (GND1,
GND2) and the power supply wiring layer (POWER) are press-bonded to each other to form a circuit board 2 having a thickness of about 1.2 mm. When the circuit board 2 is press-bonded, the third signal wiring layer (S3) and the power supply wiring layer (POWER) are arranged so as to sandwich the fourth insulating substrate (B4). Signal wiring layer (S2), third signal wiring layer (S3), and fourth signal wiring layer (S4)
And a power supply wiring layer (POWER) are provided so as to sandwich the third and fifth insulating substrates (B3, B5), respectively, and further a first ground wiring layer (GND1) and a second signal wiring layer (S2), and the fourth signal wiring layer (S4) and the second ground wiring layer (GND2) are disposed so as to sandwich the second and sixth insulating substrates (B2, B6), respectively. First signal wiring layer (S1)
And a first ground wiring layer (GND1), and a fifth signal wiring layer (S5) and a second ground wiring layer (GND2).
The 1.2 mm multilayer circuit board 2 is formed so as to sandwich the first and seventh insulating substrates (B1, B7), respectively.
【００１１】上記の第１の実施例において、第１および
第５のシグナル配線層（Ｓ１、Ｓ５）は、それぞれ約３
５．５６μｍの厚さを有し、第２、第３および第４のシ
グナル配線層（Ｓ２、Ｓ３、Ｓ４）、第１および第２の
接地配線層（ＧＮＤ１、ＧＮＤ２）、ならびに電源配線
層（ＰＯＷＥＲ）は、それぞれ約１７．７８μｍの厚さ
を有している。さらに、第３および第５の絶縁基板（Ｂ
３、Ｂ５）は、それぞれ好ましい７６．２〜２２８．６
μｍの範囲内のより好ましい１５２．４μｍの厚さ（Ｈ
２）を有し、第１および第７の絶縁基板（Ｂ１、Ｂ７）
は、それぞれ好ましい１１４．３μｍの厚さ（Ｈ４）を
有し、第２、第４および第６の絶縁基板（Ｂ２、Ｂ４、
Ｂ６）は、それぞれ好ましい１５２．４μｍの厚さ（Ｈ
３、Ｈ１）を有する。第１のシグナル配線層（Ｓ１）
は、第１の接地配線層（ＧＮＤ１）との間に第１の抵抗
（Ｒｓ１）を有し、第２のシグナル配線層（Ｓ２）は、
第１の接地配線層（ＧＮＤ１）と電源配線層（ＰＯＷＥ
Ｒ）との間に第２の抵抗（Ｒｓ２）を有し、第３のシグ
ナル配線層（Ｓ３）は、第１の接地配線層（ＧＮＤ１）
と電源配線層（ＰＯＷＥＲ）との間に第３の抵抗（Ｒｓ
３）を有し、第４のシグナル配線層（Ｓ４）は、第２の
接地配線層（ＧＮＤ２）と電源配線層（ＰＯＷＥＲ）と
の間に第４の抵抗（Ｒｓ４）を有し、第５のシグナル配
線層（Ｓ５）は、第２の接地配線層（ＧＮＤ２）との間
に第５の抵抗（Ｒｓ５）を有する。これらの絶縁層（Ｂ
１、Ｂ２、Ｂ３、Ｂ４、Ｂ５、Ｂ６およびＢ７）の厚さ
をそれぞれ上記範囲内にコントロールすると、第１、第
２、第３、第４および第５の抵抗（Ｒｓ１、Ｒｓ２、Ｒ
ｓ３、Ｒｓ４およびＲｓ５）の抵抗値をそれぞれ４９．
５オーム〜６０．５オームの範囲内に保持できて、イン
ピーダンス整合の効果を達成する。In the first embodiment, each of the first and fifth signal wiring layers (S1 and S5) has about 3
A second, third, and fourth signal wiring layers (S2, S3, S4), first and second ground wiring layers ( GND1 , GND2), and a power supply wiring layer having a thickness of 5.56 μm; (POWER) each have a thickness of about 17.78 μm. Further, the third and fifth insulating substrates (B
3, B5) are preferably 76.2 to 228.6.
The thickness of the more preferred 152.4μm in the range of [mu] m (H
2), the first and seventh insulating substrates (B1, B7)
Each have a preferred thickness (H4) of 114.3 μm, and the second, fourth and sixth insulating substrates (B2, B4,
B6) has a preferred thickness of 152.4 μm (H
3, H1). First signal wiring layer (S1)
Has a first resistance (Rs1) between the first ground wiring layer (GND1) and the second signal wiring layer (S2).
A first ground wiring layer (GND1) and a power supply wiring layer (POWE)
R) between the first ground wiring layer (GND1) and the second signal wiring layer (S3).
A third resistor (Rs) is provided between the power supply wiring layer (POWER) and a third resistor (Rs).
3), the fourth signal wiring layer (S4) has a fourth resistor (Rs4) between the second ground wiring layer (GND2) and the power supply wiring layer (POWER), and has a fifth The signal wiring layer (S5) has a fifth resistor (Rs5) between itself and the second ground wiring layer (GND2). These insulating layers (B
1, B2, B3, B4, B5, B6 and B7) are controlled to fall within the above ranges, respectively, so that the first, second, third, fourth and fifth resistors (Rs1, Rs2, R
s3, Rs4 and Rs5) respectively.
It can be kept in the range of 5 ohm to 60.5 ohm to achieve the effect of impedance matching.
【００１２】続いて、各絶縁基板（Ｂ１、Ｂ２、Ｂ３、
Ｂ４、Ｂ５、Ｂ６およびＢ７）のそれぞれの厚さの概算
を下記の通りに説明する。まず、第１と第５の抵抗（Ｒ
ｓ１、Ｒｓ５）の抵抗値を次の式（１）で計算する。Subsequently, each of the insulating substrates (B1, B2, B3,
Estimation of the thickness of each of B4, B5, B6 and B7) is described as follows. First, the first and fifth resistors (R
s1, Rs5) are calculated by the following equation (1).
【数１】 ここで、ＥR は誘導係数で４．５であり、Ｈ４は第１と
第７の絶縁基板（Ｂ１、Ｂ７）の厚さであり、Ｗは第１
と第５のシグナル配線層（Ｓ１、Ｓ５）のトレース幅で
あって５０．３〜２０３．２μｍの範囲内にあるが、本
実施例では１２７μｍになっており、Ｔ１は第１と第４
のシグナル配線層（Ｓ１、Ｓ４）の厚さであって３５．
５６μｍである。つぎに、第２と第３の抵抗（Ｒｓ２、
Ｒｓ３）の抵抗値を下記の式（２）および式（３）から
得る。(Equation 1) Here, E R is an induction coefficient of 4.5, H4 is the thickness of the first and seventh insulating substrates (B1, B7), and W is the first
And the trace width of the fifth signal wiring layer (S1, S5) is in the range of 50.3 to 203.2 μm. In this embodiment, it is 127 μm , and T1 is the first and fourth.
35. The thickness of the signal wiring layer (S1, S4)
It is 56 μm . Next, the second and third resistors (Rs2,
The resistance value of Rs3) is obtained from the following equations (2) and (3).
【数２】 (Equation 2)
【数３】 ここで、ＥR は誘導係数で４．５であり、Ｈ３は第２と
第６の絶縁基板（Ｂ２、Ｂ６）の厚さであって第４の絶
縁基板（Ｂ４）の厚さＨ１に等しい。さらに、Ｈ２は第
３と第５の絶縁基板（Ｂ３、Ｂ５）の厚さであり、Ｔ２
は第２のシグナル配線層（Ｓ２）の厚さであって１７．
７８μｍであり、また第３のシグナル配線層（Ｓ３）の
厚さでもある。Ｗは第２と第３のシグナル配線層（Ｓ
２、Ｓ３）のトレース幅であって５０．８〜２０３．２
μｍの範囲内にあるが、本実施例では１２７μｍになっ
ている。第４の抵抗（Ｒｓ４）の抵抗値は下記の式
（４）を使って得られる。(Equation 3) Here, E R is an induction coefficient of 4.5, and H3 is the thickness of the second and sixth insulating substrates (B2, B6) and is equal to the thickness H1 of the fourth insulating substrate (B4). . H2 is the thickness of the third and fifth insulating substrates (B3, B5), and T2
Is the thickness of the second signal wiring layer (S2), and 17.
78 μm, which is also the thickness of the third signal wiring layer (S3). W is the second and third signal wiring layers (S
2, S3) is a trace width of 50.8 to 203.2
Although it is within the range of μm , it is 127 μm in this embodiment. The resistance value of the fourth resistor (Rs4) can be obtained using the following equation (4).
【数４】 ここで、ＥR は誘導係数で４．５であり、Ｈ３は第２と
第６の絶縁基板（Ｂ２、Ｂ６）の厚さであり、Ｈ２は第
３と第５の絶縁基板（Ｂ３、Ｂ５）の厚さであり、Ｔ２
は第４シグナル配線層（Ｓ４）の厚さであって１７．７
８μｍであり、Ｗは第４のシグナル配線層（Ｓ４）のト
レース幅であって５０．８〜２０３．２μｍの範囲内に
あるが、本実施例では１２７μｍになっている。加える
に、回路板の合計厚さは１．２ｍｍ（約４８ｍｉｌに相
当する）、あるいはその許容誤差範囲内に規制すべき
で、下記の式（５）によって表される。(Equation 4) Here, E R is an induction coefficient of 4.5, H3 is the thickness of the second and sixth insulating substrates (B2, B6), and H2 is the third and fifth insulating substrates (B3, B5). ) And T2
Is the thickness of the fourth signal wiring layer (S4), which is 17.7.
8 μm , and W is the trace width of the fourth signal wiring layer (S4), which is in the range of 50.8 to 203.2 μm , but is 127 μm in this embodiment. In addition, the total thickness of the circuit board should be regulated to 1.2 mm (corresponding to about 48 mil), or within an allowable error range, and is represented by the following equation (5).
【数５】 この式（５）に基づいて、それぞれ絶縁基板の好ましい
厚さの値を得ることができる。すなわち、第４の絶縁基
板（Ｂ４）の厚さＨ１が７６．２〜２２８．６μｍの範
囲内にある場合は１５２．４μｍが好ましく、第３と第
５の絶縁基板（Ｂ３、Ｂ５）の厚さＨ２が７６．２〜２
２８．６μｍの範囲内にある場合は１５２．４μｍが好
ましく、第２と第６の絶縁基板（Ｂ２、Ｂ６）の厚さＨ
３が７６．２〜２２８．６μｍの範囲内にある場合は１
５２．４μｍが好ましく、第１と第７の絶縁基板（Ｂ
１、Ｂ７）の厚さＨ４が６３．５〜１６５．１μｍの範
囲内にある場合は１１４．３μｍが好ましい。この条件
の下で、第１と第５の抵抗（Ｒｓ１、Ｒｓ５）の抵抗値
は略５８オームで、第２と第３の抵抗（Ｒｓ２、Ｒｓ
３）の抵抗値は略５７オームで、第４の抵抗（Ｒｓ４）
の抵抗値は略５０オームであり、これらの抵抗値は全て
Ｉｎｔｅｌが高速シグナル伝送のために設定した理論範
囲の４９．５オーム〜６０．５オーム内にある。なお、
前述の式（５）によって算出した回路板２の厚さの総計
は、２Ｈ４＋２Ｈ３＋２Ｈ２＋１Ｈ１＋２Ｔ１＋６Ｔ２
＝２×１１４．３μｍ＋２×１５２．４μｍ＋２×１５
２．４μｍ＋１×１５２．４μｍ＋２×３５．５６μｍ
＋６×１７．７８μｍ＝１１６８．４μｍ≒１．２ｍｍ
（許容誤差の範囲内）である。(Equation 5) Based on the equation (5), it is possible to obtain a preferable value of the thickness of each of the insulating substrates. That is, when the thickness H1 of the fourth insulating substrate (B4) is in the range of 76.2~228.6μm is preferably 152.4Myuemu, the thickness of the third and fifth insulating substrate (B3, B5) H2 is 76.2-2
When it is within the range of 28.6 μm, it is preferably 152.4 μm, and the thickness H of the second and sixth insulating substrates (B2, B6)
1 when 3 is in the range of 76.2 to 228.6 μm
52.4 μm is preferable, and the first and seventh insulating substrates (B
When the thickness H4 of (1, B7) is in the range of 63.5 to 165.1 μm, the thickness is preferably 114.3 μm . Under this condition, the resistance values of the first and fifth resistors (Rs1, Rs5) are approximately 58 ohms, and the second and third resistors (Rs2, Rs5)
The resistance value of 3) is approximately 57 ohms, and the fourth resistance (Rs4)
Are approximately 50 ohms, all of which fall within the theoretical range of 49.5 ohms to 60.5 ohms set by Intel for high-speed signal transmission. In addition,
The total thickness of the circuit board 2 calculated by the above equation (5) is 2H4 + 2H3 + 2H2 + 1H1 + 2T1 + 6T2
= 2 × 114.3 μm + 2 × 152.4 μm + 2 × 15
2.4 μm + 1 × 152.4 μm + 2 × 35.56 μm
+ 6 × 17.78 μm = 1168.4 μm ≒ 1.2 mm
(Within the tolerance).
【００１３】図４に示すのは、本発明に係る多層回路板
２’の比較的好ましい第２の実施例であり、この回路板
２’は図示の如く、第１、第２、第３、第４、第５、第
６および第７の絶縁基板（Ｂ１、Ｂ２、Ｂ３、Ｂ４、Ｂ
５、Ｂ６、Ｂ７）と、第１、第２、第３、第４および第
５のシグナル配線層（Ｓ１、Ｓ２、Ｓ３、Ｓ４、Ｓ５）
と、第１および第２の接地配線層（ＧＮＤ１、ＧＮＤ
２）および電源配線層（ＰＯＷＥＲ）を含んで、それら
が互いにプレス接着して約１．６ｍｍ厚さの回路板２を
形成する。本実施例が上記第１の実施例と異なるところ
は、第３と第５の絶縁基板（Ｂ３’、Ｂ５’）がそれぞ
れ２２８．６〜５８４．２μｍの範囲内の厚さ（Ｈ２）
を有して、上記式に基づいて計算した結果、下記の好ま
しいＨ１、Ｈ２、Ｈ３およびＨ４の値を得た。Ｈ１の好
ましい範囲は７６．２〜２２８．６μｍで、より好まし
くは１５２．４μｍであり、Ｈ２の好ましい範囲は２２
８．６〜５８４．２μｍで、より好ましくは４０６．４
μｍであり、Ｈ３の好ましい範囲は７６．２〜２２８．
６μｍで、より好ましくは１５２．４μｍであり、Ｈ４
の好ましい範囲は６３．５〜１６５．１μｍで、より好
ましくは１１４．３μｍである。それにより、第１と第
５の抵抗の抵抗値が６０オームで、第２と第３の抵抗の
抵抗値が約５５オーム、第４の抵抗の抵抗値が約６０オ
ームで、これらの抵抗値はいずれもＩｎｔｅｌの決めた
理論範囲内にある。FIG. 4 shows a second preferred embodiment of a multilayer circuit board 2 'according to the present invention, wherein the circuit board 2' comprises first, second, third, Fourth, fifth, sixth and seventh insulating substrates (B1, B2, B3, B4, B
5, B6, B7) and the first, second, third, fourth and fifth signal wiring layers (S1, S2, S3, S4, S5)
And first and second ground wiring layers (GND1, GND
2) and a power wiring layer (POWER), which are press bonded to each other to form a circuit board 2 having a thickness of about 1.6 mm. This embodiment differs from the first embodiment in that the third and fifth insulating substrates (B3 ', B5') each have a thickness (H2) in the range of 228.6 to 584.2 μm.
As a result of calculation based on the above formula, the following preferable values of H1, H2, H3 and H4 were obtained. The preferred range of H1 is 76.2 to 228.6 μm , more preferably 152.4 μm , and the preferred range of H2 is 22
8.6 to 584.2 μm , more preferably 406.4
μm , and the preferred range of H3 is 76.2 to 228.
6 μm , more preferably 152.4 μm ,
Is preferably 63.5 to 165.1 μm , and more preferably 114.3 μm . Accordingly, the resistance values of the first and fifth resistors are 60 ohms, the resistance values of the second and third resistors are about 55 ohms, and the resistance values of the fourth resistor are about 60 ohms. Are all within the theoretical range determined by Intel.
【００１４】[0014]
【発明の効果】したがって、本発明の多層回路板は下記
の優点・効果を有している。 １）高速シグナル反射が低減する。第１および第２の実
施例のそれぞれの抵抗が共に５５オーム±１０％の設定
範囲内にあって、反射指数が従来技術と比べて随分と低
くなり、高速シグナルの反射をかなり軽減、若しくは除
去して、高速シグナルの伝送に適する回路板を形成でき
る。 ２）電磁波障害が軽減する。高速シグナル反射が低減し
たため、定常波の発生がなくなり、磁束の反作用が高め
られて、電磁波障害を低め、現在のＥＭＩ標準に符合で
きる。 ３）高速シグナルのレイアウトへの適応性が優れてい
る。上記優点から本発明の回路板は高速シグナルレイア
ウトに適して、現在の業が高速シグナルへと発展してい
る傾向に対応し、製品の市場価格や競争力を高める。 ４）レイアウトの時効性が向上する。インピーダンス整
合のために、シグナル配線層のトレース幅を変える必要
がなく、レイアウトの時効性を促進する。Accordingly, the multilayer circuit board of the present invention has the following advantages and effects. 1) Fast signal reflection is reduced. The respective resistances of the first and second embodiments are both within the setting range of 55 ohms ± 10%, the reflection index is considerably lower than that of the prior art, and the reflection of high-speed signals is considerably reduced or eliminated. Thus, a circuit board suitable for high-speed signal transmission can be formed. 2) Electromagnetic interference is reduced. Due to the reduced high-speed signal reflection, the generation of the standing wave is eliminated, the reaction of the magnetic flux is enhanced, the electromagnetic wave interference is reduced, and the current EMI standard can be met. 3) Excellent adaptability to high-speed signal layout. Due to the above advantages, the circuit board of the present invention is suitable for a high-speed signal layout, responds to the tendency of the current industry to develop a high-speed signal, and increases the market price and competitiveness of products. 4) The aging effect of the layout is improved. It is not necessary to change the trace width of the signal wiring layer for impedance matching, which promotes the aging effect of the layout.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明に係る比較的好ましい第１の実施例にお
ける１．２ｍｍの厚さの多層回路板の概略図である。FIG. 1 is a schematic view of a 1.2 mm thick multilayer circuit board in a first preferred embodiment according to the present invention.
【図２】第１の実施例の部分断面図である。FIG. 2 is a partial cross-sectional view of the first embodiment.
【図３】第１の実施例の他の部分断面図である。FIG. 3 is another partial sectional view of the first embodiment.
【図４】本発明に係る比較的好ましい第２の実施例にお
ける１．６ｍｍの厚さの多層回路板の概略図である。FIG. 4 is a schematic diagram of a 1.6 mm thick multilayer circuit board in a second preferred embodiment according to the present invention.
【図５】従来の１．２ｍｍの厚さの多層回路板の概略図
である。FIG. 5 is a schematic view of a conventional multilayer circuit board having a thickness of 1.2 mm.
【図６】従来の１．６ｍｍの厚さの多層回路板の概略図
である。FIG. 6 is a schematic view of a conventional multilayer circuit board having a thickness of 1.6 mm.
【符号の説明】 Ｂ１、Ｂ２、Ｂ３．Ｂ４、Ｂ５、Ｂ６およびＢ７…第
１、第２、第３、第４、第５、第６および第７の絶縁基
板 Ｓ１、Ｓ２、Ｓ３、Ｓ４およびＳ５…第１、第２、第
３、第４および第５のシグナル配線層 ＧＮＤ１、ＧＮＤ２…第１および第２の接地配線層 Ｈ１…第４の絶縁基板の厚さ Ｈ２…第３の絶縁基板の厚さ、および第５の絶縁基板の
厚さ Ｈ３…第２の絶縁基板の厚さ、および第６の絶縁基板の
厚さ Ｈ４…第１の絶縁基板の厚さ、および第７の絶縁基板の
厚さ Ｒｓ１、Ｒｓ２、Ｒｓ３、Ｒｓ４およびＲｓ５…第１、
第２、第３、第４および第５の抵抗[Description of Signs] B1, B2, B3. B4, B5, B6 and B7 ... first, second, third, fourth, fifth, sixth and seventh insulating substrates S1, S2, S3, S4 and S5 ... first, second, third, Fourth and fifth signal wiring layers GND1, GND2... First and second ground wiring layers H1... Thickness of fourth insulating substrate H2... Thickness of third insulating substrate and fifth insulating substrate Thickness H3: thickness of the second insulating substrate, and thickness of the sixth insulating substrate H4: thickness of the first insulating substrate, and thickness of the seventh insulating substrate Rs1, Rs2, Rs3, Rs4 and Rs5 ... first,
Second, third, fourth and fifth resistors
【手続補正２】[Procedure amendment 2]
【補正対象書類名】図面[Document name to be amended] Drawing
【補正対象項目名】図１[Correction target item name] Fig. 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図１】 FIG.
【手続補正３】[Procedure amendment 3]
【補正対象書類名】図面[Document name to be amended] Drawing
【補正対象項目名】図４[Correction target item name] Fig. 4
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図４】 FIG. 4
【手続補正４】[Procedure amendment 4]
【補正対象書類名】図面[Document name to be amended] Drawing
【補正対象項目名】図５[Correction target item name] Fig. 5
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図５】 FIG. 5
【手続補正５】[Procedure amendment 5]
【補正対象書類名】図面[Document name to be amended] Drawing
【補正対象項目名】図６[Correction target item name] Fig. 6
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図６】 FIG. 6
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 1/02 Ｈ０５Ｋ 1/02 Ｎ Ｆターム(参考） 5E338 AA03 AA15 BB13 CC01 CC02 CC04 CC06 EE13 5E346 AA12 AA15 AA22 AA32 AA34 AA43 AA51 BB02 BB03 BB04 BB06 BB07 BB11 BB15 BB16 CC02 CC08 CC12 DD02 DD09 DD12 EE09 FF27 FF45 GG28 HH03 HH06 5J014 CA23 CA55 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification FI theme coat テ ー マ (reference) H05K 1/02 H05K 1/02 NF term (reference) 5E338 AA03 AA15 BB13 CC01 CC02 CC04 CC06 EE13 5E346 AA12 AA15 AA22 AA32 AA34 AA43 AA51 BB02 BB03 BB04 BB06 BB07 BB11 BB15 BB16 CC02 CC08 CC12 DD02 DD09 DD12 EE09 FF27 FF45 GG28 HH03 HH06 5J014 CA23 CA55
Claims (13)
第２、第３、第４、第５、第６および第７の絶縁基板
と、 第１の絶縁基板の第２の絶縁基板と相対する向きの反対
側の面に配置される第１のシグナル配線層と、 第１の絶縁基板と第２の絶縁基板との間に配設される第
１の接地配線層と、 第２の絶縁基板と第３の絶縁基板との間に配設される第
２のシグナル配線層と、 第３の絶縁基板と第４の絶縁基板との間に配設される第
３のシグナル配線層と、 第４の絶縁基板と第５の絶縁基板との間に配設される電
源配線層と、 第５の絶縁基板と第６の絶縁基板との間に配設される第
４のシグナル配線層と、 第６の絶縁基板と第７の絶縁基板との間に配設される第
２の接地配線層と、 第７の絶縁基板の第６の絶縁基板と相対する向きの反対
側の面に配設される第５のシグナル配線層とを含み、 第１および第７の絶縁基板の厚さがそれぞれ２．５ｍｉ
ｌ〜６．５ｍｉｌの範囲内にあり、 第２、第４および第６の絶縁基板の厚さがそれぞれ３ｍ
ｉｌ〜９ｍｉｌの範囲内にあって、 第３および第５の絶縁基板の厚さがそれぞれ３ｍｉｌ〜
２３ｍｉｌの範囲内にあり、 第１のシグナル配線層は、第１の接地配線層との間に第
１の抵抗を有し、第２のシグナル配線層は、第１の接地
配線層と電源配線層との間に第２の抵抗を有し、第３の
シグナル配線層は、第１の接地配線層と電源配線層との
間に第３の抵抗を有し、第４のシグナル配線層は、第２
の接地配線層と電源配線層との間に第４の抵抗を有し、
第５のシグナル配線層は、第２の接地配線層との間に第
５の抵抗を有すると共に、前記の第１、第２、第３、第
４および第５の抵抗の抵抗値がそれぞれ４９．５オーム
〜６０．５オームの範囲内に規制されてなることを特徴
とする多層回路板。The first, superimposed and arranged in order from top to bottom,
A second, a third, a fourth, a fifth, a sixth and a seventh insulating substrate, and a first signal disposed on a surface of the first insulating substrate opposite to the direction opposite to the second insulating substrate. A wiring layer, a first ground wiring layer provided between the first insulating substrate and the second insulating substrate, and a first ground wiring layer provided between the second insulating substrate and the third insulating substrate. A second signal wiring layer, a third signal wiring layer disposed between the third insulating substrate and the fourth insulating substrate, and a third signal wiring layer disposed between the fourth insulating substrate and the fifth insulating substrate. A power wiring layer provided, a fourth signal wiring layer provided between the fifth insulating substrate and the sixth insulating substrate, and a fourth signal wiring layer provided between the sixth insulating substrate and the seventh insulating substrate. And a fifth signal wiring layer disposed on the surface of the seventh insulating substrate opposite to the direction facing the sixth insulating substrate, Preliminary seventh thickness of the insulating substrate, respectively 2.5mi
1 to 6.5 mil, and the thickness of each of the second, fourth and sixth insulating substrates is 3 m
il to 9 mil, and the thicknesses of the third and fifth insulating substrates are each 3 mil to 9 mil.
23 mil, the first signal wiring layer has a first resistance between the first signal wiring layer and the first ground wiring layer, and the second signal wiring layer has a first ground wiring layer and the power supply wiring. The second signal wiring layer has a third resistance between the first ground wiring layer and the power supply wiring layer, and the fourth signal wiring layer has a third resistance between the first ground wiring layer and the power supply wiring layer. , Second
Having a fourth resistor between the ground wiring layer and the power supply wiring layer,
The fifth signal wiring layer has a fifth resistance between the fifth signal wiring layer and the second ground wiring layer, and the first, second, third, fourth, and fifth resistors each have a resistance value of 49. A multilayer circuit board characterized by being regulated within the range of 5 ohm to 60.5 ohm.
縁基板の少なくともいずれかがポリエステルプリプレグ
によって形成されてなる請求項１に記載の多層回路板。2. The multilayer circuit board according to claim 1, wherein at least one of said first, third, fifth and seventh insulating substrates is formed of polyester prepreg.
の少なくともいずれかが繊維質心材によって形成されて
なる請求項１に記載の多層回路板。3. The multilayer circuit board according to claim 1, wherein at least one of the second, fourth, and sixth insulating substrates is formed of a fibrous core material.
求項３に記載の多層回路板。4. The multilayer circuit board according to claim 3, wherein said fibrous core comprises paper fibers.
る請求項３に記載の多層回路板。5. The multilayer circuit board according to claim 3, wherein said fibrous core comprises glass fibers.
ぞれの厚さが等しい請求項１に記載の多層回路板。6. The multilayer circuit board according to claim 1, wherein each of said first and seventh insulating substrates has an equal thickness.
ぞれの厚さが等しい請求項１に記載の多層回路板。7. The multilayer circuit board according to claim 1, wherein each of said second and sixth insulating substrates has the same thickness.
ぞれの厚さが等しい請求項１に記載の多層回路板。8. The multilayer circuit board according to claim 1, wherein each of said third and fifth insulating substrates has the same thickness.
のそれぞれの厚さが約１．４ｍｉｌで、前記の第２、第
３および第４のシグナル配線層、前記の第１および第２
の接地配線層、ならびに前記電源配線層のそれぞれの厚
さが約０．７ｍｉｌである請求項１に記載の多層回路
板。9. The first and fifth signal wiring layers each having a thickness of about 1.4 mil, wherein the second, third and fourth signal wiring layers, and the first and second signal wiring layers have a thickness of about 1.4 mil.
The multilayer circuit board according to claim 1, wherein each of the ground wiring layer and the power supply wiring layer has a thickness of about 0.7 mil.
れぞれ３ｍｉｌ〜９ｍｉｌの範囲の厚さを有してなる請
求項１に記載の多層回路板。10. The multilayer circuit board according to claim 1, wherein said third and fifth insulating substrates each have a thickness in a range of 3 mil to 9 mil.
れぞれ４．５ｍｉｌの厚さを有し、 前記の第２、第３、第４、第５と第６の絶縁基板がそれ
ぞれ６ｍｉｌの厚さを有し、 前記の第１、第２、第３、第４、第５、第６および第７
の絶縁基板と、前記の第１、第２、第３、第４および第
５のシグナル配線層と、前記の第１および第２の接地配
線層と、前記電源配線層とを、互いにプレス接着して約
１．２ｍｍの厚さの回路板を形成するようにしてなる請
求項１に記載の多層回路板。11. The first and seventh insulating substrates each have a thickness of 4.5 mils, and the second, third, fourth, fifth and sixth insulating substrates each have a thickness of 6 mils. Having a thickness, wherein said first, second, third, fourth, fifth, sixth and seventh
Press bonding the insulating substrate, the first, second, third, fourth, and fifth signal wiring layers, the first and second ground wiring layers, and the power supply wiring layer to each other. 2. The multilayer circuit board according to claim 1, wherein the circuit board has a thickness of about 1.2 mm.
れぞれ９ｍｉｌ〜２３ｍｉｌ範囲の厚さを有してなる請
求項１に記載の多層回路板。12. The multilayer circuit board according to claim 1, wherein said third and fifth insulating substrates each have a thickness in a range of 9 mil to 23 mil.
れぞれ４．５ｍｉｌの厚さを有し、 前記の第２、第４および第６の絶縁基板がそれぞれ６
ｍｉｌの厚さを有し、 前記の第３および第５の絶縁基板がそれぞれ１６ ｍｉ
ｌの厚さを有し、 前記の第１、第２、第３、第４、第５、第６および第７
の絶縁基板と、前記の第１、第２、第３、第４および第
５のシグナル配線層と、前記の第１および第２の接地配
線層と、前記電源配線層とを、互いにプレス接着して約
１．６ｍｍの厚さの回路板を形成するようにしてなる請
求項１２に記載の多層回路板。13. The first and seventh insulating substrates each have a thickness of 4.5 mils, and the second, fourth and sixth insulating substrates each have a thickness of 6 mils.
mil, and the third and fifth insulating substrates each have a thickness of 16 mi.
1, said first, second, third, fourth, fifth, sixth and seventh
Press bonding the insulating substrate, the first, second, third, fourth, and fifth signal wiring layers, the first and second ground wiring layers, and the power supply wiring layer to each other. 13. The multilayer circuit board of claim 12, wherein the circuit board is formed to a thickness of about 1.6 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001100554A JP2002299839A (en) | 2001-03-30 | 2001-03-30 | Multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001100554A JP2002299839A (en) | 2001-03-30 | 2001-03-30 | Multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002299839A true JP2002299839A (en) | 2002-10-11 |
Family
ID=18953988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001100554A Pending JP2002299839A (en) | 2001-03-30 | 2001-03-30 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002299839A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1303851C (en) * | 2004-02-26 | 2007-03-07 | 马建中 | Soft printed circuit board |
| WO2020166996A1 (en) * | 2019-02-15 | 2020-08-20 | 엘지이노텍 주식회사 | Circuit board |
-
2001
- 2001-03-30 JP JP2001100554A patent/JP2002299839A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1303851C (en) * | 2004-02-26 | 2007-03-07 | 马建中 | Soft printed circuit board |
| WO2020166996A1 (en) * | 2019-02-15 | 2020-08-20 | 엘지이노텍 주식회사 | Circuit board |
| US11974388B2 (en) | 2019-02-15 | 2024-04-30 | Lg Innotek Co., Ltd. | Circuit board |
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