JPH10303521A - Transmission line board - Google Patents
Transmission line boardInfo
- Publication number
- JPH10303521A JPH10303521A JP10565197A JP10565197A JPH10303521A JP H10303521 A JPH10303521 A JP H10303521A JP 10565197 A JP10565197 A JP 10565197A JP 10565197 A JP10565197 A JP 10565197A JP H10303521 A JPH10303521 A JP H10303521A
- Authority
- JP
- Japan
- Prior art keywords
- line
- signal
- electric signal
- signal line
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は伝送線路基板に関す
る。[0001] The present invention relates to a transmission line substrate.
【0002】[0002]
【従来の技術】近年、携帯型パーソナルコンピュータ
(以下PC)では、液晶ディスプレイ(以下LCD)の
大画面化が進み、解像度が高くなってきている。また、
デスクトップ型パーソナルコンピュータでも、省スペー
ス,省電力化のためにCRTディスプレイの代わりとし
て液晶ディスプレイが用いられるようになってきてい
る。こうしたLCDの大画面化,高解像度化が進むと、
LCDへのデータ転送速度があがり、従来の信号転送方
式ではデータ転送が困難になってきた。そこで、高速に
信号を送る方式として低振幅の差動伝送方式が提案され
ている。差動伝送方式とは、一つの信号から信号(+
線)と反転信号(−線)の二相の信号を発生し、二本の
信号線を用いて伝送する方式である。この方式では、+
線と−線が電磁気的に結合するため、信号線とそのリタ
ーン電流の経路でできるアンテナループ面積を零に近づ
ける事ができ、従来のシングルエンドの伝送方式と比較
して、ディファレンシャルモードのノイズを減らすこと
ができ、かつ高速に伝送することができる。また、この
伝送には、電磁気的結合を強くするために、一般的に
「ノイズ対策技術,総合技術出版,p200」に示す+
線−線の二本の電線を撚って一対としたツイストペアと
よばれるケーブルが用いられている。2. Description of the Related Art In recent years, in a portable personal computer (hereinafter, referred to as a PC), a liquid crystal display (hereinafter, referred to as an LCD) has a larger screen, and the resolution has been increased. Also,
In desktop personal computers, liquid crystal displays have come to be used instead of CRT displays in order to save space and power. As the LCD screen size and resolution increase,
The data transfer speed to the LCD has increased, and it has become difficult to transfer data using the conventional signal transfer method. Therefore, a low-amplitude differential transmission system has been proposed as a system for transmitting a signal at high speed. The differential transmission method means that a signal (+
This is a method of generating two-phase signals, ie, a line and an inverted signal (−line), and transmitting the signal using two signal lines. In this method, +
Because the line and the-line are electromagnetically coupled, the antenna loop area formed by the signal line and the return current path can be made close to zero, and the differential mode noise can be reduced compared to the conventional single-ended transmission system. The transmission can be reduced and the transmission can be performed at high speed. In addition, in order to strengthen the electromagnetic coupling, this transmission is generally performed by using +
2. Description of the Related Art A cable called a twisted pair in which two electric wires of a wire are twisted into a pair is used.
【0003】[0003]
【発明が解決しようとする課題】しかし、ノートPCで
は筐体形状に制約から、ツイストペアのケーブルを配線
することが難しい。例えば、ツイストペアでLCDの信
号(5組10本)のケーブルを作ると、直径が約5mmと
なるが、通常、LCDと筐体の隙間は側面で2〜3mm、
裏面で0.5mm程度であるため、このケーブルを通すこ
とは不可能である。このため、ノートPCでは、LCD
のケーブルをフレキシブル・プリンテッド基板(以下F
PC)ケーブルのようなフラットなケーブルを用いる必
要がある。However, in a notebook PC, it is difficult to wire a twisted pair cable due to the limitation of the housing shape. For example, when a cable for LCD signals (5 sets of 10 cables) is made with a twisted pair, the diameter becomes about 5 mm. Usually, the gap between the LCD and the housing is 2-3 mm on the side,
Since it is about 0.5 mm on the back surface, it is impossible to pass this cable through. For this reason, notebook PCs use LCD
Cable to a flexible printed board (F
It is necessary to use a flat cable such as a PC) cable.
【0004】一般的に使われているFPCの層構成を図
3に示す。配線層111と配線層の両面を覆うコーティ
ング層113とを有して構成され、配線層111には信
号線が挿入されている。FIG. 3 shows a layer structure of a generally used FPC. It has a wiring layer 111 and a coating layer 113 covering both surfaces of the wiring layer, and a signal line is inserted into the wiring layer 111.
【0005】ここで、配線層111に差動信号の−線1
17と+線118を配置し、層厚116,線幅115,
線間距離114を図3に示す一般的なFPCの値とし、
信号線は銅(導電率5.8×107)、配線層111
(信号線は除く)、および、コーティング層113をポ
リイミド(誘電率3.5)として、電磁界解析から差動
インピーダンス(ペア間のインピーダンス)を算出する
と、166Ωとなる。しかし、差動伝送線路のインピー
ダンスは終端抵抗が決められており、例えば、LVDS
(low voltage differential siganaling)などの差動
伝送方式では100Ωであるので、この構成では、イン
ピーダンスの不整合による反射や波形歪みが生じ、放射
ノイズが増加し、信号品質が低下する。インピーダンス
を下げるには、線間距離114を狭くする、または、線
幅115を広げるといった方法が考えられるが、前者は
ショート危険性が、後者はケーブル面積が増える可能性
がある。また、図4に示すように絶縁層110を挾んで
信号層112を設け、−線117と+線118を配線層
111と配線層112に、対向させて配置した場合、差
動インピーダンスは20Ωと小さくなってしまう。Here, the negative line 1 of the differential signal is
17 and a + line 118, and a layer thickness 116, a line width 115,
The line distance 114 is a general FPC value shown in FIG.
The signal line is made of copper (conductivity 5.8 × 10 7 ), the wiring layer 111
When the differential impedance (impedance between pairs) is calculated from the electromagnetic field analysis using the coating layer 113 (excluding the signal line) and the coating layer 113 as polyimide (dielectric constant 3.5), the value is 166Ω. However, the terminating resistance is determined for the impedance of the differential transmission line.
(Low voltage differential siganaling) or the like, the impedance is 100Ω. Therefore, in this configuration, reflection or waveform distortion occurs due to impedance mismatch, radiation noise increases, and signal quality deteriorates. In order to lower the impedance, a method of narrowing the line distance 114 or increasing the line width 115 can be considered. However, the former has a risk of short-circuit, and the latter has a possibility of increasing the cable area. When the signal layer 112 is provided with the insulating layer 110 interposed therebetween as shown in FIG. 4 and the-line 117 and the + line 118 are arranged opposite to the wiring layer 111 and the wiring layer 112, the differential impedance is 20 Ω. It will be smaller.
【0006】このように、差動伝送回路で要求している
インピーダンスに対して、従来の方法では、差動インピ
ーダンスが大幅に高くなるか、大幅に低くなる。このた
め、インピーダンスの不整合により放射ノイズが増加し
信号品質が低下する可能性があるといった問題があっ
た。As described above, in the conventional method, the differential impedance is significantly higher or lower than the impedance required by the differential transmission circuit. For this reason, there has been a problem that radiation noise may increase due to impedance mismatching and signal quality may deteriorate.
【0007】本発明の目的は、差動伝送回路を伝送する
基板において、差動インピーダンスの整合をとり、信号
の品質の低下を防ぐことにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit board for transmitting a differential transmission circuit, in which differential impedances are matched to prevent signal quality from deteriorating.
【0008】[0008]
【課題を解決するための手段】上記課題を解決するため
に、二つの電気信号を伝送する線路を一対のデータ伝送
路とするデータ伝送回路であって、前記伝送線路のうち
の一つの電気信号線の電圧と他方の伝送線路の電圧の和
が常に一定である差動伝送回路を伝送する基板で、前記
基板は複数層の配線層を有し、前記一対のデータ伝送回
路のうち、一方の電気信号路と他方の電気信号路を前記
基板で互いに異なる配線層に、平行に配置したものであ
る。According to another aspect of the present invention, there is provided a data transmission circuit in which a line for transmitting two electric signals is a pair of data transmission lines, wherein one of the transmission lines has an electric signal. A substrate for transmitting a differential transmission circuit in which the sum of the voltage of the line and the voltage of the other transmission line is always constant, the substrate having a plurality of wiring layers, and one of the pair of data transmission circuits. The electric signal path and the other electric signal path are arranged in parallel on different wiring layers on the substrate.
【0009】さらに、前記伝送路で、二つの電気信号路
間の水平方向距離が100〜350μmで、絶縁層の厚
みを20〜50μmで構成することを特徴としたフレキ
シブル基板である。Further, the flexible substrate is characterized in that the transmission path has a horizontal distance between two electric signal paths of 100 to 350 μm and an insulating layer having a thickness of 20 to 50 μm.
【0010】また、前記差動伝送回路を伝送する基板
で、折り目を有し、一対のデータ伝送回路のうち、一方
の電気信号路と他方の電気信号路を前記基板の折り目の
左右に配置することである。The substrate for transmitting the differential transmission circuit has a fold, and one electric signal path and the other electric signal path of the pair of data transmission circuits are disposed on the left and right of the fold of the substrate. That is.
【0011】さらに、前記差動伝送回路の一方の電気信
号路を有する伝送線路基板と、他方の電気信号路を有す
る伝送線路基板を重ねて配置することである。Further, a transmission line substrate having one electric signal path of the differential transmission circuit and a transmission line substrate having the other electric signal path are arranged so as to overlap with each other.
【0012】さらに、前記伝送路で、二つの電気信号路
間のインピーダンスが終端抵抗に等しいことが望まし
い。加えて前記伝送線路基板はFPCであることであ
る。Further, it is desirable that the impedance between the two electric signal paths in the transmission path is equal to the terminating resistance. In addition, the transmission line substrate is an FPC.
【0013】[0013]
【発明の実施の形態】以下、本発明の一実施例について
図面を参照しながら説明する。本実施例は差動伝送方式
の一つであるLVDSに適用した場合である。図16に
LVDS回路のモデルを示す。160はLVDSのドラ
イバモデル、161は終端抵抗、162は差動伝送路で
ある。そして、終端抵抗161は100Ωである。この
ため、伝送線路162の差動インピーダンスを100Ω
にすることで終端抵抗とインピーダンスの整合がとれ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. This embodiment is a case where the present invention is applied to LVDS which is one of the differential transmission systems. FIG. 16 shows a model of the LVDS circuit. 160 is an LVDS driver model, 161 is a terminating resistor, and 162 is a differential transmission line. The terminating resistance 161 is 100Ω. Therefore, the differential impedance of the transmission line 162 is set to 100Ω.
By doing so, the impedance of the terminating resistor can be matched with that of the impedance.
【0014】図1はFPCケーブルの平面図、図2は図
1に示したA−B部分の断面図である。FPCケーブル
1はベースとなる絶縁層2と絶縁層2の両面に形成され
た配線層3と配線層4とこれらの配線層を覆うコーティ
ング層5で構成される。配線層3と配線層4には、それ
ぞれ、幅が200μmの信号線6と信号線7が複数本挿
入されている。絶縁層2,配線層(信号線は除く)、お
よび、コーティング層5はそれぞれ、本実施例ではポリ
イミドで形成されている。FIG. 1 is a plan view of an FPC cable, and FIG. 2 is a cross-sectional view taken along a line AB shown in FIG. The FPC cable 1 includes an insulating layer 2 serving as a base, wiring layers 3 and 4 formed on both surfaces of the insulating layer 2, and a coating layer 5 covering these wiring layers. A plurality of signal lines 6 and 7 having a width of 200 μm are inserted into the wiring layers 3 and 4 respectively. In this embodiment, the insulating layer 2, the wiring layer (excluding the signal lines), and the coating layer 5 are each formed of polyimide.
【0015】さらに、本実施例では他の回路または装置
との接続のために、FPCケーブル1上にコネクタ8を
設けた。コネクタ8の信号ピン9は配線層3に接続し、
信号線とコネクタ8の接続は配線層3で行う。このため
配線層4内の信号線7はスルーホール10を介してコネ
クタ8と接続している。Further, in this embodiment, a connector 8 is provided on the FPC cable 1 for connection with another circuit or device. The signal pin 9 of the connector 8 is connected to the wiring layer 3,
The connection between the signal line and the connector 8 is made in the wiring layer 3. Therefore, the signal line 7 in the wiring layer 4 is connected to the connector 8 via the through hole 10.
【0016】そして、図2に示すように、信号線6と信
号線7は段違いの平行線として配置する。信号線6と信
号線7を離す距離は、本実施例の場合は、水平方向で2
50μm、厚さ方向で25μmとした。そして、信号線
6に差動信号の−線を、信号線7に差動信号の+線を配
線する。こうすることで、信号線の差動インピーダンス
を100Ω近辺にすることができる。As shown in FIG. 2, the signal lines 6 and 7 are arranged as parallel lines having different levels. In this embodiment, the distance between the signal line 6 and the signal line 7 is 2 in the horizontal direction.
The thickness was 50 μm and 25 μm in the thickness direction. Then, the minus line of the differential signal is wired to the signal line 6 and the plus line of the differential signal is wired to the signal line 7. By doing so, the differential impedance of the signal line can be set to around 100Ω.
【0017】本実施例では、信号線6に差動信号の−線
を、信号線7に差動信号の+線を配線したが、逆でもよ
い。また、信号ごとに、+線と−線を配線する層を変え
てもよい。In the present embodiment, the minus line of the differential signal is wired to the signal line 6 and the plus line of the differential signal is wired to the signal line 7, but the reverse is also possible. Further, the layer for wiring the + line and the-line may be changed for each signal.
【0018】次に、+線と−線の離す距離について詳細
に説明する。図5は、図2の点線で囲んだ部分11の拡
大図である。信号線6と信号線7の水平方向の距離(線
間隔p)20は信号線の幅w21と絶縁層厚d22によ
って異なる。例えば、一般的なFPCである信号線の幅
w=200μm、絶縁層厚d=25μmの場合は、電磁
界シミュレーションにより、線間隔pを250μmとす
ることで、−線と+線間のインピーダンスを100Ω付
近(±5%)にすることができる。Next, the distance between the + line and the-line will be described in detail. FIG. 5 is an enlarged view of a portion 11 surrounded by a dotted line in FIG. The horizontal distance (line interval p) 20 between the signal line 6 and the signal line 7 differs depending on the width w21 of the signal line and the thickness d22 of the insulating layer. For example, in the case of a signal line width w = 200 μm and an insulating layer thickness d = 25 μm, which is a general FPC, the impedance between the − line and the + line is set by setting the line interval p to 250 μm by electromagnetic field simulation. It can be around 100Ω (± 5%).
【0019】線幅w=50,100,150,200,
250,300,350,400μmで、−線と+線間
のインピーダンスが100Ωになる絶縁層厚d22と線
間隔p20の関係を図6に示す。これを満たす線間隔p
20に離して、−線と+線を配置することでペア間のイ
ンピーダンスを100Ω付近に保ことができ、LVDS
の終端抵抗値と整合がとれ、高品質の信号が送ることが
できる。前記絶縁層厚d=25μm,線幅w=200μ
mの場合は、図6のポイント61にあたり、線間隔pを
250μmで、−線と+線間のインピーダンスが100
Ω付近となる。Line widths w = 50, 100, 150, 200,
FIG. 6 shows the relationship between the insulation layer thickness d22 and the line interval p20 at 250, 300, 350, and 400 μm, where the impedance between the − and + lines is 100Ω. Line spacing p that satisfies this
By arranging the-and + wires apart from each other, the impedance between the pairs can be kept near 100Ω, and the LVDS
And a high-quality signal can be sent. The insulation layer thickness d = 25 μm, line width w = 200 μ
In the case of m, it corresponds to the point 61 in FIG. 6, the line interval p is 250 μm, and the impedance between the − line and the + line is 100.
It is around Ω.
【0020】図7に本発明をノート型のパーソナルコン
ピュータに本発明を適用した第二の実施例を示す。この
パーソナルコンピュータは本体部の筐体30と表示部の
筐体31からなり、本体部の筐体内には回路基板32,
キーボード33等で構成される。回路基板32にはCP
U34,表示LSI35、本発明のFPC1を接続する
コネクタ36等からなる。表示LSI35からの信号
は、コネクタを経て、本発明のFPC1を通り、LCD
に伝送される。本発明のFPCを適用することで、終端
抵抗とインピーダンスの整合がとれるので、反射,放射
ノイズを減らすことができる。従来のノート型のパーソ
ナルコンピュータでは、放射ノイズ不要放射の対策のた
めに、筐体のメッキシールドや回路基板上の信号にノイ
ズフィルタの挿入を行っていたが、本発明のFPCを用
いることで、これらのノイズ対策部品を減らすことがで
き、低価格化,高密度実装が可能となる。FIG. 7 shows a second embodiment in which the present invention is applied to a notebook personal computer. This personal computer includes a main body housing 30 and a display housing 31. A circuit board 32,
It is composed of a keyboard 33 and the like. The circuit board 32 has a CP
U34, a display LSI 35, a connector 36 for connecting the FPC 1 of the present invention, and the like. A signal from the display LSI 35 passes through a connector, passes through the FPC 1 of the present invention,
Is transmitted to By applying the FPC of the present invention, the impedance of the terminating resistor can be matched with the impedance, so that reflection and radiation noise can be reduced. In a conventional notebook personal computer, a noise filter was inserted into a plating shield of a housing or a signal on a circuit board in order to prevent unnecessary radiation noise, but by using the FPC of the present invention, It is possible to reduce the number of these noise countermeasure components, and it is possible to reduce the cost and mount the components at a high density.
【0021】次に、接続する回路基板にFPC差し込み
型のコネクタが実装されている場合の第三の実施例につ
いて図14,図15を用いて説明する。FPCの層構成
は第一の実施例と同じである。この場合、FPCの表面
にコネクタを設ける必要はなく、FPC端部140で信
号層を覆っているコーティング層5をなくし、信号層を
表面に出すことで差し込み型のコネクタと接続すること
ができる。図15は図14の点線枠部分141を横から
見た断面図である。FPCの端部はコーティング層5を
設けず、信号層3と信号層4を表面に出す。こうするこ
とで、この部分を回路基板上の差し込み型コネクタに差
し込んだ時に、信号線を回路基板上の回路と接続するこ
とができる。この場合でも、第一の実施例と同様に差動
インピーダンスを終端抵抗と整合をとることができ、高
品質の信号を送ることができる。Next, a third embodiment in which an FPC insertion type connector is mounted on a circuit board to be connected will be described with reference to FIGS. The layer configuration of the FPC is the same as in the first embodiment. In this case, there is no need to provide a connector on the surface of the FPC, and the coating layer 5 covering the signal layer at the FPC end 140 is eliminated, and the signal layer can be exposed to the surface to connect to a plug-in type connector. FIG. 15 is a sectional view of the dotted frame portion 141 of FIG. 14 as viewed from the side. The end portion of the FPC is not provided with the coating layer 5, and the signal layers 3 and 4 are exposed on the surface. By doing so, when this part is inserted into the plug-in connector on the circuit board, the signal line can be connected to the circuit on the circuit board. Also in this case, the differential impedance can be matched with the terminating resistor as in the first embodiment, and a high-quality signal can be transmitted.
【0022】次にFPCケーブルの配線層を複数層にし
た第四の実施例の断面図を図8に示す。本実施例では、
配線層を三層としたが三層以上でもよい。FPCケーブ
ル81は絶縁層2を挾んだ配線層3,配線層4,配線層
82とFPCケーブル81の表面を覆うコーティング層
5とで構成される。配線層3,配線層4,配線層82に
は、それぞれ信号線84,信号線85,信号線83が複
数本挿入されている。そして、二本一組の差動信号のう
ち片方(+線または−線)を信号線84に、もう片方
(−線または+線)を信号線83に配線する。また、信
号線85は差動信号以外の給電線,制御信号等である。
信号線84と信号線83はペア間のインピーダンスが、
終端抵抗と等しくなる距離に離して段違いの平行線とし
て配置する。この結果、インピーダンスの整合がとれ、
高品質の信号を送ることができる。Next, FIG. 8 is a sectional view of a fourth embodiment in which the wiring layers of the FPC cable are formed in a plurality of layers. In this embodiment,
Although three wiring layers are used, three or more wiring layers may be used. The FPC cable 81 is composed of wiring layers 3, 4 and 4, sandwiching the insulating layer 2, and a coating layer 5 covering the surface of the FPC cable 81. In the wiring layer 3, the wiring layer 4, and the wiring layer 82, a plurality of signal lines 84, 85, and 83 are inserted, respectively. Then, one (+ line or − line) of the pair of differential signals is wired to the signal line 84, and the other (− line or + line) is wired to the signal line 83. The signal line 85 is a power supply line other than the differential signal, a control signal, and the like.
The impedance between the pair of the signal line 84 and the signal line 83 is
It is arranged as a parallel line with a step difference at a distance equal to the terminal resistance. As a result, impedance matching is achieved,
High quality signals can be sent.
【0023】次に第五の実施例を示す。図9は差動信号
の−線と+線の間隔のとり方をペア線ごとに変えて構成
した第五の実施例の断面図である。FPCケーブル91
の層構成は第一の実施例の層構成(図2)と同じであ
る。差動信号92は配線層の信号線94と配線層の信号
線95で成り、信号線95は信号線94に対して、図の
右方向に、ペア間のインピーダンスが終端抵抗と等しく
なる距離に離して段違いの平行線として配置する。一
方、差動信号93は配線層の信号線96と配線層の信号
線97で成り、信号線97は信号線96に対して、図の
左方向に、ペア間のインピーダンスが終端抵抗と等しく
なる距離に離して段違いの平行線として配置する。この
ように、差動信号の−線と+線の離す方向は−線と+線
のペアごとに替えてもよい。さらに、−線と+線を配線
する層はペアごとに替えてもよい。Next, a fifth embodiment will be described. FIG. 9 is a sectional view of a fifth embodiment in which the spacing between the negative and positive lines of the differential signal is changed for each pair line. FPC cable 91
Is the same as the layer configuration of the first embodiment (FIG. 2). The differential signal 92 is composed of a signal line 94 in the wiring layer and a signal line 95 in the wiring layer. The signal line 95 is located at a distance from the signal line 94 to the right in the drawing, at a distance where the impedance between the pair is equal to the terminating resistance. Separate and arrange as parallel lines with different levels. On the other hand, the differential signal 93 is composed of the signal line 96 of the wiring layer and the signal line 97 of the wiring layer, and the impedance between the pair is equal to the terminating resistance in the left direction of the drawing with respect to the signal line 96. It is arranged as a parallel line with a step at a distance. As described above, the direction in which the negative and positive lines of the differential signal are separated may be changed for each pair of the negative and positive lines. Further, the layer for wiring the-line and the + line may be changed for each pair.
【0024】次に第六の実施例を示す。図10は差動信
号線の間にガードパタンであるグランド線101を入れ
た第六の実施例の断面図である。第五の実施例では差動
信号のペアでない信号線95と信号線97の電磁気的結
合が強くなり、信号線の品質が下がる可能性があるの
で、異なるペア間にグランド線101を配線する。こう
することで、信号線94と信号線97,信号線98、信
号線95と信号線96,信号線97の電磁気的結合が減
り、より高品質の信号を送ることができる。Next, a sixth embodiment will be described. FIG. 10 is a sectional view of the sixth embodiment in which a ground line 101 serving as a guard pattern is inserted between differential signal lines. In the fifth embodiment, since the electromagnetic coupling between the signal line 95 and the signal line 97 which are not a pair of differential signals is strengthened and the quality of the signal line may be degraded, the ground line 101 is provided between different pairs. By doing so, the electromagnetic coupling between the signal line 94 and the signal line 97 and the signal line 98, and between the signal line 95 and the signal line 96 and the signal line 97 is reduced, so that a higher quality signal can be transmitted.
【0025】次に第七の実施例を図11に示す。本発明
を信号層が一層のFPCに適用した場合である。このF
PC102は、FPCの幅の真ん中付近に折り目103
と、左右に複数本の信号線で構成される。本実施例では
左右に五本づつ(計10本)配線し、左側の信号線を折
り目103に近いところから、L1信号線108,L2
信号線107,L3信号線106,L4信号線105,
L5信号線104、右側の信号線を折り目103に近い
ところから、R1信号線109,R2信号線120,R
3信号線121,R4信号線122,R5信号線123
とする。そして、差動信号のペアは、L1信号線108
とR1信号線109、L2信号線107とR2信号線1
20、L3信号線106とR3信号線121、L4信号
線105とR4信号線122、L5信号線104とR5
信号線123で作る。Next, a seventh embodiment is shown in FIG. This is a case where the present invention is applied to an FPC having a single signal layer. This F
The PC 102 has a fold 103 near the center of the width of the FPC.
And a plurality of signal lines on the left and right. In the present embodiment, five lines (a total of ten lines) are arranged on the left and right, and the left signal line is connected to the L1 signal lines 108, L2
The signal line 107, the L3 signal line 106, the L4 signal line 105,
The L5 signal line 104 and the right signal line are located near the fold 103 from the R1 signal line 109, the R2 signal line 120, and the R
3 signal line 121, R4 signal line 122, R5 signal line 123
And The pair of differential signals is connected to the L1 signal line 108.
, R1 signal line 109, L2 signal line 107 and R2 signal line 1
20, L3 signal line 106 and R3 signal line 121, L4 signal line 105 and R4 signal line 122, L5 signal line 104 and R5
It is made with the signal line 123.
【0026】さらに、ペアになる二本の信号線の折り目
から距離の差は、折り目103で折った時(図12)
に、ペア間のインピーダンスが終端抵抗と等しくなる距
離にする。例えば、信号線108と信号線109は折り
目103で折った時(図12)に、ペア間のインピーダ
ンスが終端抵抗と等しくなる距離124に離すために、
L1信号線108と折り目103間の距離125とR1
信号線109と折り目間の距離126の差をインピーダ
ンスが終端抵抗と等しくなる距離124と等しくする。
こうすることで、一層構成のFPCでインピーダンスの
整合をとることができ、高品質の信号を送ることができ
る。Further, the difference in distance from the fold of the two signal lines forming a pair is determined when the signal line is folded at the fold 103 (FIG. 12).
Then, the distance is set such that the impedance between the pair is equal to the terminating resistance. For example, when the signal line 108 and the signal line 109 are folded at the fold 103 (FIG. 12), the signal line 108 and the signal line 109 are separated by a distance 124 at which the impedance between the pair becomes equal to the terminating resistance.
Distance 125 between L1 signal line 108 and fold 103 and R1
The difference between the distance 126 between the signal line 109 and the fold is made equal to the distance 124 at which the impedance becomes equal to the terminal resistance.
By doing so, impedance matching can be achieved with a single-layer FPC, and a high-quality signal can be transmitted.
【0027】次に第八の実施例を図13に示す。本実施
例は一層のFPC2枚で構成する。FPC131には信
号線134をFPC132には信号線135を複数本配
線する。そして、差動信号は片方の信号(+線または−
線)を信号線134に他方(−線または+線)を信号線
135に配線する。そして、FPC131とFPC13
2は信号線134と信号線135のペア間のインピーダ
ンスが終端抵抗と等しくなる距離133に、横にずらし
て重ねて実装する。こうすることで、インピーダンスの
整合をとることができ、高品質の信号を送ることができ
る。Next, an eighth embodiment is shown in FIG. This embodiment is composed of two FPCs. A plurality of signal lines 134 are connected to the FPC 131 and a plurality of signal lines 135 are connected to the FPC 132. The differential signal is one of the signals (+ line or-
Is connected to the signal line 134, and the other (− or + line) is connected to the signal line 135. Then, the FPC 131 and the FPC 13
No. 2 is mounted by being shifted laterally and overlapping at a distance 133 where the impedance between the pair of the signal line 134 and the signal line 135 is equal to the terminating resistance. By doing so, impedance matching can be achieved, and a high-quality signal can be transmitted.
【0028】次に第九の実施例を図17に示す。本実施
例は本発明をプリント基板に適用した例であり、図17
はその断面の一部を表す図である。本実施例は表面を覆
うコーティング層170と絶縁層172を挾んで信号層
171,信号層173,信号層176,信号層177と
電源層174とグランド層175からなる。本実施例で
は信号層四層の六層基板で構成したが、何層基板でもよ
い。そして、信号層171,信号層173,信号層17
6,信号層177には複数の信号線が配線されている。
ここでは、二本一組の差動信号179のうち片方(+線
または−線)を信号線178に、もう片方(−線または
+線)を信号線180に配線する。また、信号線18
1,信号線182は差動信号以外の信号である。信号線
178と信号線180はペア間のインピーダンスが、終
端抵抗と等しくなる距離に離して段違いの平行線として
配置する。この結果、インピーダンスの整合がとれ、高
品質の信号を送ることができる。Next, a ninth embodiment is shown in FIG. This embodiment is an example in which the present invention is applied to a printed circuit board.
Is a diagram showing a part of the cross section. This embodiment comprises a signal layer 171, a signal layer 173, a signal layer 176, a signal layer 177, a power supply layer 174, and a ground layer 175 with a coating layer 170 covering the surface and an insulating layer 172 sandwiched therebetween. In this embodiment, a six-layer substrate having four signal layers is used, but any number of layers may be used. Then, the signal layer 171, the signal layer 173, and the signal layer 17
6, a plurality of signal lines are wired in the signal layer 177.
Here, one (+ line or − line) of the pair of differential signals 179 is wired to the signal line 178, and the other (− line or + line) is wired to the signal line 180. Also, the signal line 18
1, a signal line 182 is a signal other than the differential signal. The signal line 178 and the signal line 180 are arranged as parallel lines having different levels so that the impedance between the pair is equal to the terminating resistance. As a result, the impedance is matched, and a high-quality signal can be transmitted.
【0029】[0029]
【発明の効果】差動伝送を行う場合、+線と−線を異な
る層に段違いに平行に配置することで、終端抵抗とイン
ピーダンスの整合が容易にとれ、高品質の信号が送れ、
放射ノイズを下げることができる。When differential transmission is performed, by arranging the + line and the-line in different layers in parallel at different levels, matching of the terminating resistance and impedance can be easily achieved, and high-quality signals can be transmitted.
Radiated noise can be reduced.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の実施例の説明図。FIG. 1 is an explanatory diagram of an embodiment of the present invention.
【図2】本発明の実施例のFPCの断面図。FIG. 2 is a sectional view of an FPC according to the embodiment of the present invention.
【図3】FPCの断面図。FIG. 3 is a cross-sectional view of an FPC.
【図4】FPCの断面図。FIG. 4 is a cross-sectional view of an FPC.
【図5】本発明の実施例の説明図。FIG. 5 is an explanatory diagram of an embodiment of the present invention.
【図6】線幅,線間隔,絶縁層厚の関係を表す特性図。FIG. 6 is a characteristic diagram showing a relationship among a line width, a line interval, and an insulating layer thickness.
【図7】本発明を情報処理装置に適用した例を表す斜視
図。FIG. 7 is a perspective view illustrating an example in which the present invention is applied to an information processing apparatus.
【図8】本発明の第四の実施例のFPCの断面図。FIG. 8 is a sectional view of an FPC according to a fourth embodiment of the present invention.
【図9】本発明の第五の実施例のFPCの断面図。FIG. 9 is a sectional view of an FPC according to a fifth embodiment of the present invention.
【図10】本発明の第六の実施例のFPCの断面図。FIG. 10 is a sectional view of an FPC according to a sixth embodiment of the present invention.
【図11】本発明の第七の実施例のFPCの説明図。FIG. 11 is an explanatory diagram of an FPC according to a seventh embodiment of the present invention.
【図12】本発明の第七の実施例の説明図。FIG. 12 is an explanatory view of a seventh embodiment of the present invention.
【図13】本発明の第八の実施例の説明図。FIG. 13 is an explanatory view of an eighth embodiment of the present invention.
【図14】本発明の第三の実施例の説明図。FIG. 14 is an explanatory view of a third embodiment of the present invention.
【図15】コネクタ差し込み型FPCの断面図。FIG. 15 is a sectional view of a connector insertion type FPC.
【図16】LVDSのモデル回路図。FIG. 16 is a model circuit diagram of an LVDS.
【図17】本発明の第九の実施例の説明図。FIG. 17 is an explanatory view of a ninth embodiment of the present invention.
1…FPCケーブル、6…信号線、7…信号線、8…コ
ネクタ、9…コネクタの信号ピン、10…スルーホー
ル。1 FPC cable, 6 signal line, 7 signal line, 8 connector, 9 connector signal pin, 10 through hole.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 横倉 義一郎 神奈川県海老名市下今泉810番地株式会社 日立製作所オフィスシステム事業部内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshiichiro Yokokura 810 Shimoimaizumi, Ebina-shi, Kanagawa Prefecture Hitachi Systems Office Systems Division
Claims (8)
伝送路とするデータ伝送回路であって、前記伝送線路の
うちの一つの電気信号線の電圧と他方の伝送線路の電圧
の和が常に一定である差動伝送回路を伝送する基板にお
いて、前記基板は複数層の配線層を有し、前記一対のデ
ータ伝送回路のうち、一方の電気信号路と他方の電気信
号路を前記基板で互いに異なる配線層に平行に配置する
ことを特徴とした伝送線路基板。1. A data transmission circuit comprising two electric signal transmission lines as a pair of data transmission lines, wherein the sum of the voltage of one electric signal line and the voltage of the other transmission line is one of the transmission lines. In a substrate that transmits a differential transmission circuit that is always constant, the substrate has a plurality of wiring layers, and one electric signal path and the other electric signal path of the pair of data transmission circuits are formed by the substrate. A transmission line substrate characterized by being arranged in parallel on different wiring layers.
水平方向距離が100〜350μmで、絶縁層の厚みを
20〜50μmで構成するフレキシブル基板。2. The flexible substrate according to claim 1, wherein the horizontal distance between the two electric signal paths is 100 to 350 μm, and the thickness of the insulating layer is 20 to 50 μm.
伝送路とするデータ伝送回路であって、前記伝送線路の
うちの一つの電気信号線の電圧と他方の伝送線路の電圧
の和が常に一定である差動伝送回路を伝送する基板にお
いて、前記基板は折り目を有し、前記一対のデータ伝送
回路のうち、一方の電気信号路と他方の電気信号路を前
記基板の折り目の左右に配置することを特徴とした伝送
線路基板。3. A data transmission circuit in which two electric signal transmission lines are used as a pair of data transmission lines, wherein the sum of the voltage of one electric signal line and the voltage of the other transmission line is one of the transmission lines. In a substrate that transmits a differential transmission circuit that is always constant, the substrate has a fold, and among the pair of data transmission circuits, one electric signal path and the other electric signal path are provided on the left and right sides of the fold of the substrate. A transmission line substrate characterized by being arranged.
に、二つの電気信号路間のインピーダンスが終端抵抗に
等しい伝送線路基板。4. The transmission line board according to claim 4, wherein the impedance between the two electric signal paths is equal to the terminating resistance when the electric signal path is folded at the fold.
伝送路とするデータ伝送回路であって、前記伝送線路の
うちの一つの電気信号線の電圧と他方の伝送線路の電圧
の和が常に一定である差動伝送回路の一方の電気信号路
を有する伝送線路基板と、他方の電気信号路を有する伝
送線路基板を重ねて配置することを特徴とした伝送線路
基板。5. A data transmission circuit comprising two electric signal transmission lines as a pair of data transmission lines, wherein the sum of the voltage of one electric signal line and the voltage of the other transmission line is one of the transmission lines. A transmission line substrate comprising: a transmission line substrate having one electric signal path of a differential transmission circuit, which is always constant; and a transmission line substrate having the other electric signal path, which are superposed.
号路間のインピーダンスが終端抵抗に等しい伝送線路基
板。6. The transmission line substrate according to claim 1, wherein the impedance between the two electric signal paths is equal to the terminating resistance.
成した請求項1,2,3,4,5または6に記載の伝送
線路基板。7. The transmission line substrate according to claim 1, wherein said transmission line substrate comprises a flexible printed cable.
記載の前記伝送線路基板を表示信号線に用いた情報処理
装置。8. An information processing apparatus using the transmission line substrate according to claim 1, 2, 3, 4, 5, 6, or 7 for a display signal line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10565197A JPH10303521A (en) | 1997-04-23 | 1997-04-23 | Transmission line board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10565197A JPH10303521A (en) | 1997-04-23 | 1997-04-23 | Transmission line board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10303521A true JPH10303521A (en) | 1998-11-13 |
Family
ID=14413361
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10565197A Pending JPH10303521A (en) | 1997-04-23 | 1997-04-23 | Transmission line board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10303521A (en) |
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KR100496485B1 (en) * | 2001-12-10 | 2005-06-22 | 니뽄 가이시 가부시키가이샤 | Flexible printed wiring board |
JP2006196849A (en) * | 2005-01-17 | 2006-07-27 | Jst Mfg Co Ltd | Double-sided fpc |
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JP2009252816A (en) * | 2008-04-02 | 2009-10-29 | Nitto Denko Corp | Printed circuit board |
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US7714411B2 (en) | 2005-05-30 | 2010-05-11 | Epson Imaging Devices Corporation | Electro-optical device, method of manufacturing the same, and electronic apparatus |
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KR100496485B1 (en) * | 2001-12-10 | 2005-06-22 | 니뽄 가이시 가부시키가이샤 | Flexible printed wiring board |
WO2004080136A1 (en) * | 2003-03-06 | 2004-09-16 | Fujitsu Limited | Connection structure of printed wiring board |
JP2006196849A (en) * | 2005-01-17 | 2006-07-27 | Jst Mfg Co Ltd | Double-sided fpc |
JP4551776B2 (en) * | 2005-01-17 | 2010-09-29 | 日本圧着端子製造株式会社 | Double-sided FPC |
JP2006235517A (en) * | 2005-02-28 | 2006-09-07 | Pioneer Electronic Corp | Display panel driving device and connection cable |
US7714411B2 (en) | 2005-05-30 | 2010-05-11 | Epson Imaging Devices Corporation | Electro-optical device, method of manufacturing the same, and electronic apparatus |
US7978297B2 (en) | 2005-05-30 | 2011-07-12 | Sony Corporation | Electro-optical device having resistor with adjustable resistance value connected to IC and wiring lines |
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JP2009206379A (en) * | 2008-02-29 | 2009-09-10 | Nitto Denko Corp | Wiring circuit board |
JP2009206380A (en) * | 2008-02-29 | 2009-09-10 | Nitto Denko Corp | Wiring circuit board |
JP2009252816A (en) * | 2008-04-02 | 2009-10-29 | Nitto Denko Corp | Printed circuit board |
JP2010003893A (en) * | 2008-06-20 | 2010-01-07 | Nitto Denko Corp | Wiring circuit board, and method of manufacturing the same |
CN101616540B (en) | 2008-06-20 | 2013-03-20 | 日东电工株式会社 | Wired circuit board and method of manufacturing the same |
JP2009060150A (en) * | 2008-12-17 | 2009-03-19 | Panasonic Corp | Differential-balanced signal transmitting board |
JP4659087B2 (en) * | 2008-12-17 | 2011-03-30 | パナソニック株式会社 | Differential balanced signal transmission board |
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