JP2002299517A - Substrate for semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a bur, which occurs at cutting with a dicing blade, from containing a conductive material, related to a substrate for a semiconductor device. SOLUTION: A wiring pattern and a plated lead wire 26 are formed on a semiconductor device substrate 20 wherein a plurality of semiconductor elements are mounted and then resin-sealed for dividing. The plated lead wire 26 extends a plurality of dicing lines, orthogonal each other detouring the intersection region of the dicing lines, to divide the resin-sealed semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for a semiconductor device, and more particularly to a semiconductor device substrate and a semiconductor device for manufacturing individual semiconductor devices by cutting a plurality of semiconductor devices resin-sealed on the substrate. And a method for producing the same.

[0002]

2. Description of the Related Art In recent years, in order to simplify a manufacturing process of a semiconductor device, a plurality of semiconductor chips are resin-sealed on a single substrate and then separated into individual semiconductor chips (singulation).
Technology has been developed. Conventionally, in order to singulate semiconductor chips which are collectively sealed with a resin, a method of cutting with a dicer (dicing saw) has been common.

That is, a plurality of semiconductor chips are aligned and mounted on one substrate, and are sealed with a resin. As a result, the substrate and the sealing resin are integrated, the semiconductor chip is sealed in the sealing resin, and a semiconductor device wired by the substrate is formed. A plurality of semiconductor devices formed in this way by resin sealing are cut into individual pieces by cutting with a dicing blade (dicing saw).

As a substrate on which a semiconductor chip is mounted, a flexible printed circuit (FPC) having a wiring pattern formed on a polyimide film (tape) or the like is often used. The wiring pattern is formed by laminating a copper foil or the like on a polyimide film and patterning it by etching. That is, a plurality of semiconductor chips are mounted on an FPC having a wiring pattern and are collectively sealed with a resin, and then the formed semiconductor device is cut into individual pieces by using a dicing blade. In addition, cutting by a laser cutting device other than cutting by a dicer may be used.

FIG. 1 is a simplified plan view of a substrate used for aligning and mounting a plurality of semiconductor chips. A plurality of aligned rectangles 4 shown in FIG. 1 correspond to semiconductor chips mounted on the FPC board 2, and vertical lines 6 and horizontal lines 8 indicate dicing lines, respectively.

As shown in FIG. 1, when semiconductor chips are arranged in a matrix and are collectively sealed with resin, there are points where the vertical dicing lines 6 and the horizontal dicing lines 8 intersect. The dicing line is located between the semiconductor element mounting regions, and separates the semiconductor device by moving the dicing blade along the dicing line. The dicing line is a line indicating the center of the region that is cut and removed by the dicing blade. In practice, the sealing resin and the FPC board 2 have a width W corresponding to the thickness of the dicing blade as shown in FIG. Is cut and removed by the dicing blade.

Here, attention is paid to a region where the vertical dicing line 6 and the horizontal dicing line 8 intersect. In this intersecting region, first, the dicing blade advances along the dicing line in one direction to cut and remove the FPC board 2 and the sealing resin, and then the dicing blade advances along the dicing line in a direction perpendicular to this. . Therefore, in the intersection area, the dicing blade passes twice. When the dicing blade passes through the intersection area for the second time, since the sealing resin 8 and the substrate 2 have already been cut and removed, as the dicing blade approaches the intersection area, a portion of the cut portion in the direction in which the dicing blade advances is moved. The thickness decreases.

Ideally, the portion (region) to be cut is cut to the end by a dicing blade.
The last part has insufficient strength required for cutting, and is not cut, but is displaced by a dicing blade and remains as a thin burr. FIG. 3 is a plan view showing a state where the semiconductor chip sealed with the sealing resin 10 is cut by a dicing blade. In FIG. 3, first, the horizontal direction (arrow)
And then cut in the vertical direction (arrow), burrs 12-1 are generated as described above.

In addition, since polyimide, which is a material of the FPC board 12, is a relatively soft material, its cutting property is not so good, and the surface of the FPC board 2 remains without being cut as shown in FIG. The burr 12-2 is generated at the time. Here, FIG. 4 is an enlarged side view of the semiconductor device after cutting shown in FIG. The burrs 12-1 and 12-2 described above have a length equivalent to the width of the dicing blade and have a length of about 1.5 times that of the dicing blade, and remain attached to the corners or edges of the cut semiconductor device. Often become.

[0010]

Here, the wiring pattern of the FPC board is often subjected to electrolytic plating such as gold plating or nickel plating. Therefore, a lead wire for electrolytic plating is formed on the FPC board. Generally, plating lead lines are formed by pattern wiring, but by providing plating lead lines along dicing lines, plating lead lines can be removed during dicing (cutting). Note that the solid lines in FIGS. 2 and 5 indicate plating lead lines arranged on the dicing line.

When a plating lead line is provided along the dicing line, when the above-mentioned burr occurs, a part of the plating lead line is included in the burr. That is, since the burr is formed with a length equal to or greater than the width of the dicing blade, a part of the plating lead wire to be removed by the dicing blade remains attached to the burr. The plated lead wire is the same material as the wiring pattern, for example, a copper foil, and is a conductive material. Therefore, burrs containing a conductive material may adhere to the semiconductor device and cause a problem in a process after cutting.

In order to prevent the occurrence of burrs as described above, a method has been proposed in which a through-hole is previously formed in an FPC board. That is, as shown in FIG. 5, a position corresponding to the corner of the region where the semiconductor device of the FPC board is formed is
The through holes 14 are formed in advance to prevent burrs. FIG. 6 is a plan view of the semiconductor device when the FPC board 2 having the through holes 14 is used, as viewed from the board side. The portion corresponding to the through hole 14 is made of FPC made of the sealing resin 10.
It reaches the surface of the substrate 2. FIG. 7 is an enlarged side view of the semiconductor device shown in FIG.

When the through hole 14 is formed in the FPC board 2, FIG.
As indicated by the arrow, the sealing resin 10 may flow out of the through hole 14 between the FPC board 2 and the mold on the FPC board side during the resin sealing and adhere to the mold. In such a case, there is a problem that a dent is formed on the semiconductor device or adheres as a foreign substance in the resin sealing step. Further, in the case of a BGA type semiconductor device, defective bonding of solder balls may be caused. Therefore, suppressing the generation of burrs by providing a through-hole in the FPC board was not the best method.

The present invention has been made in view of the above points, and provides a semiconductor device substrate and a method of manufacturing a semiconductor device which can prevent a conductive material from being included in burrs generated when cutting with a blade or the like. The purpose is to do.

[0015]

Means for Solving the Problems In order to solve the above problems, the present invention is characterized by taking the following means.

According to a first aspect of the present invention, there is provided a substrate for a semiconductor device used for mounting a plurality of semiconductor elements, sealing the resin with a resin, and separating the semiconductor element into a plurality of pieces. A plating lead line extending along a plurality of orthogonal dicing lines for singulating the sealed semiconductor device, wherein the plating lead line is formed so as to bypass an intersection region of the dicing line. It is characterized by having.

According to the first aspect of the present invention, the plating lead line does not extend into the intersection area of the dicing line. Therefore, even if burrs are generated at the time of cutting with a dicing blade or the like, the plating lead is applied to the burrs. No lines are included. Therefore, it is possible to avoid a problem caused by the burr containing a conductive material.

According to a second aspect of the present invention, in the substrate for a semiconductor device according to the first aspect, the crossing region is defined as a square region having a side of a width of a dicing blade used for singulation. It is characterized by the following.

According to the second aspect of the invention, a region having a side having a width corresponding to the width of the dicing blade is defined as an intersection region with respect to the intersection of the orthogonal dicing lines. Since burrs generated by dicing are generated from the area removed by the dicing blade, the burrs do not include the plating lead unless the plating lead extends in the intersection area.

According to a third aspect of the present invention, there is provided the semiconductor device substrate according to the second aspect, wherein the plating lead line extends from the surrounding portion so as to surround the intersection region, and is diced from the surrounding portion. And a portion extending along the line.

According to the third aspect of the present invention, the plating lead line can bypass the intersection area of the dicing line by the surrounding portion. The surrounding portion can have any shape such as a circle or a square.

According to a fourth aspect of the present invention, there is provided the semiconductor device substrate according to any one of the first to third aspects, wherein:
The plating lead line is formed of the same material as the wiring pattern.

According to the fourth aspect of the present invention, it is possible to simultaneously form the plated lead in the step of forming the wiring pattern on the substrate, so that the manufacturing process can be simplified.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are aligned, mounted, resin-sealed, and singulated, and the semiconductor device extends along orthogonal dicing lines. A wiring pattern including plating lead lines formed so as to detour the intersection area of the dicing lines is formed on a substrate, and a semiconductor element is mounted on the substrate and resin-sealed; The device is diced along the orthogonal dicing line.

According to the fifth aspect of the present invention, the plating lead line does not extend in the intersection area of the dicing line. Therefore, even if burrs are generated during cutting by the dicing blade, the plating lead line is applied to the burr. Is not included. Therefore, it is possible to avoid a problem caused by the burr containing a conductive material.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 8 shows an FPC according to an embodiment of the present invention.
It is a top view of a board. FIG. 9 is an enlarged view of a portion A in FIG. FIG. 9A shows an example of a pattern of a plating lead line in an intersection area, and FIG. 9B shows another example of a pattern of a plating lead line.

The FPC board 20 shown in FIG. 8 is a board used for a BGA type semiconductor device, and is formed by bonding a copper foil to a resin tape such as polyimide or the like to form a pattern. The FPC board 20 is provided with regions (mounting regions) 22 for mounting semiconductor chips arranged in a matrix. A region to be removed by dicing (dicing region: indicated by 24 in FIG. 9) is provided between the mounting regions 22. Although the dicing area is not clearly shown in FIG. 8, it is shown in FIG. 9 as a portion surrounded by a dotted line. Although a wiring pattern is provided in each mounting area 22, it is not shown for simplification of the drawing.

A plating lead 26 is provided in the dicing area 24 and extends in the dicing area 24 in the longitudinal direction. Dicing line (dicing area)
There are those that extend in the vertical direction and those that extend in the horizontal direction, and there are points that intersect each other as shown in part A of FIG.
FIG. 9 is an enlarged view of a portion A, in which the vicinity of a region where the dicing regions intersect (intersecting region: indicated by 28 in FIG. 9) is enlarged.

In the conventional substrate, the plated lead extending in the vertical direction and the plated lead extending in the horizontal direction intersect in the intersection region 28. However, in the present embodiment, the plating lead wires 26 are connected to each other bypassing the intersection area 28. That is, the plating lead line 26 extending to the dicing region is split into two lines before the intersection region 28, and extends into the dicing region orthogonal to the intersection region so as not to extend into the intersection region 28. It is connected to the plating lead wire 26.

In the example shown in FIG. 9A, the plating lead line 26 branches into two lines forming an angle of 90 degrees before the intersection area 28, and each of the two lines is perpendicular to the plating lead line. Connected to the wire. Therefore, the plating lead line 26 patterned into a square is formed so as to surround the intersection region 28. In this case, the plating lead line 26 extending in the dicing area extends from each vertex of the square pattern.

In the example shown in FIG. 9B, the plating lead wire 26 extends right and left by 180 degrees before the intersection area 28, and is connected to the orthogonal branch line of the plating lead wire 26. Therefore, the plating lead line 26 patterned into a square having a shape slightly larger than the square intersection region 28 is formed so as to surround the intersection region 28.
In this case, the plating lead 2 extending in the dicing area
Reference numeral 6 extends from the center of each side of the square pattern.

In the above configuration, since the plating lead line 26 does not exist in the intersection area 28,
Even if burrs are generated on the FPC board 20 in 8, the burrs are prevented from including plating lead wires. Therefore,
In the process of manufacturing the semiconductor device using the FPC board 20 according to the present embodiment, there is no possibility that a problem due to burrs containing a conductive material will occur.

The pattern shape of the plating lead wire is as follows.
The shape is not limited to a square as shown in FIG. 9 and may be an arbitrary shape such as a circle as long as it does not enter the intersection area 28. In addition, the pattern does not have to be a symmetrical shape, and may have a part missing. Further, the present invention is not limited to the FPC board, but can be applied to a rigid board such as a glass epoxy board.

FIG. 10 is a view showing a modification of the pattern of the plating lead lines. In the example shown in FIG. 10, a detour portion of the plating lead wire 26 is formed by using a terminal formed in a mounting area of each semiconductor chip. That is, in the mounting area outside the dicing area, a large number of terminals 30 for connecting to the semiconductor chip are provided. Among these terminals, for example, a terminal 30 located in a portion near the intersection area 28 is selected, and one plating lead 2
6 is connected to this terminal 30. Then, another plating lead 26 to be connected to this plating lead is similarly connected to the same terminal 30. Thereby, the plating lead wire 26 is formed.
These are connected to each other via the terminal 30 while bypassing the intersection area. Since the plating lead wire 26 is removed by dicing, the terminal 30 does not affect the function as a normal terminal.

In FIG. 10, the terminal 30 close to the intersection area 28 is selected. However, the terminal may not necessarily be located near the intersection area 28 as long as it can be connected by a wiring pattern. Further, it is not necessary to make a detour via terminals in all directions as shown in FIG. 10, and a form in which detour by pattern and detour via terminals are combined may be used.

In the above-described embodiment, cutting by a dicer has been described as an example, but the present invention can be applied to cutting by a laser cutting device.

According to the present invention as described above, the following various effects can be realized. According to the first aspect of the present invention, the plating lead line does not extend in the intersection area of the dicing line. Therefore, even if burrs occur during cutting by the dicing blade, the burr includes the plating lead line. Never. Therefore, it is possible to avoid a problem caused by the burr containing a conductive material.

According to the second aspect of the present invention, a region having a side having a width corresponding to the width of the dicing blade is defined as an intersection region with respect to the intersection of the orthogonal dicing lines. Since burrs generated by dicing are generated from the area removed by the dicing blade, the burrs do not include the plating lead unless the plating lead extends in the intersection area.

According to the third aspect of the present invention, the plating lead line can bypass the intersection area of the dicing line by the surrounding portion. The surrounding portion can have any shape such as a circle or a square.

According to the fourth aspect of the present invention, in the step of forming a wiring pattern on a substrate, plating lead lines can be formed simultaneously, so that the manufacturing process can be simplified.

According to the fifth aspect of the present invention, the plating lead line does not extend into the intersection area of the dicing line. Therefore, even if burrs are generated during cutting by the dicing blade, the plating lead line is applied to the burrs. Is not included. Therefore, it is possible to avoid a problem caused by the burr containing a conductive material.

[Brief description of the drawings]

FIG. 1 is a simplified plan view of a conventional semiconductor device substrate.

FIG. 2 is an enlarged view showing an intersection of plating lead lines shown in FIG.

FIG. 3 is a simplified plan view of the semiconductor device shown in FIG. 1 after dicing.

FIG. 4 is a side view of the semiconductor device after dicing.

FIG. 5 is an enlarged view showing an intersection of plating lead lines when a through hole is provided in a substrate.

FIG. 6 is a simplified plan view after dicing when a through hole is provided in a substrate.

FIG. 7 is a side view of the semiconductor device when a through hole is provided in the substrate.

FIG. 8 is a plan view of an FPC board according to an embodiment of the present invention.

FIG. 9 is an enlarged view of a portion A shown in FIG.

FIG. 10 is a view showing a modified example of a pattern of a plating lead line.

[Explanation of symbols]

 Reference Signs List 20 FPC board 22 Mounting area 24 Dicing area 26 Plating lead 28 Intersection area

Continued on the front page (72) Inventor Hitoshi Kobayashi No. 1 Nishigaoka, Murata-cho, Shibata-gun, Miyagi Prefecture 1 Fujitsu Miyagi Electronics Co., Ltd.

Claims (5)

[Claims] 1. A semiconductor device substrate used for mounting a plurality of semiconductor elements and encapsulating with a resin to separate the semiconductor device into a plurality of pieces. A plating lead line extending along a plurality of orthogonal dicing lines for singulation, wherein the plating lead line is formed so as to bypass an intersection region of the dicing line. Substrate for semiconductor devices. 2. The semiconductor device substrate according to claim 1, wherein the intersection region is defined as a square region having a side of a width of a dicing blade used for singulation. Equipment substrate. 3. The substrate for a semiconductor device according to claim 2, wherein the plating lead line extends along the dicing line from the surrounding portion extending to surround the intersection region. A substrate for a semiconductor device, comprising: 4. The semiconductor device substrate according to claim 1, wherein the plating lead is formed of the same material as the wiring pattern. Substrate. 5. A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are aligned, mounted, resin-sealed, and then singulated, wherein the semiconductor devices extend along orthogonal dicing lines, and A wiring pattern including a plating lead line formed so as to bypass the intersection region of is formed on a substrate, a semiconductor element is mounted on the substrate and sealed with a resin, and the resin-sealed semiconductor element is orthogonally diced. A method for manufacturing a semiconductor device, comprising: dicing along a line.