JP2002298583A - Power consumption reducing circuit and power consumption reducing method used for the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power consumption reducing circuit which can read out data from a memory cell continuously and at high rate with low power consumption. SOLUTION: In cell arrays CA11-CA1n, CB11-CB1n belonging to the same row of (n) pieces of block A300, block B400 making a pair with two groups, when data of blocks of the cell arrays CA11-CA1n of one side is read out, data of blocks of the cell arrays CB11-CB1n are prepared by half. Operation of sense amplifiers of the cell arrays CA11-CA1n, CB11-CB1n at the time of read-out is divided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption reduction circuit and a power consumption reduction method used therefor, and more particularly to a power consumption reduction circuit in continuous reading of a semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory, as shown in FIGS. 6 and 7, memory cells (M11, M12,
..., M1m) 22-1 to 22-m, (M21, M2
2,..., M2m) 23-1 to 23-m, (M11, M
12,..., M1m) 32-1 to 32-m, (M21,
M22,..., M2m) m composed of 33-1 to 33-m
Sub-arrays 21-1 to 21-m, 31-1 to 31-
m and m sense amplifiers (SAMPs) forming a pair with them.
# 1 to #m) 24-1 to 24-m, 34-1 to 34-m
And a switching circuit 25 and 35 for selecting one of these sense amplifier outputs.

In this semiconductor memory, as shown in FIG. 3, the above-mentioned cell arrays are arranged in k rows and 1 columns, and n data lines YL1 to YLn, YLn + 1 to YL1 to YLn to which outputs of cell arrays belonging to the same column are commonly connected. It has two sets of blocks A300 and B400 composed of YL2n, and has a switching circuit 500 for selecting and outputting one of the outputs of 2n.

In this semiconductor memory, block A3
While the memory cell data is being read from 00, the memory cell data of the block B400 is read up to just before the switching circuit 500, and the memory cell data of the block A300 has been read out and the waiting block B4
00, and the memory cell data of the block A300 is read up to the position just before the switching circuit 500 during the read operation of the block B400 side in the same manner as described above, thereby eliminating the internal delay generated at the time of block switching. There is a data transfer method to perform. This data transfer method is disclosed in Japanese Patent Application Laid-Open No. 08-069409.

[0005]

In the above-described conventional semiconductor memory, for example, a state in which memory cell data is read from block A300 shown in FIG. 3, that is, word line WL1 in block A300 shown in FIG. 3 is activated. The memory cell data M1 of the sub-arrays 21-1 to 21-m.
1 to M1m are amplified by the sense amplifiers 24-1 to 24-m via the respective bit lines BL21-1 to BL21-m,
The switching circuit 25 outputs the sense amplifier output lines DL24-1 to DL24-m in response to the sense amplifier output line switching signal SW1A.
Are always selected, the sense amplifiers 24-1 to 24-2 of the subarrays 21-1 to 21-m are always selected.
Since all of the 4-m operate, wasteful power consumption occurs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a power consumption reduction circuit and a power consumption reduction method that can continuously read data from a memory cell at high speed with low power consumption. To provide.

[0007]

A power consumption reduction circuit according to the present invention is a power consumption reduction circuit for reducing power consumption when reading data continuously in a semiconductor memory comprising a plurality of memory cells, wherein From the sense amplifier for amplifying data from the amplifier.

A power consumption reducing method according to the present invention is a power consumption reducing method for reducing power consumption when reading data continuously in a semiconductor memory including a plurality of memory cells, and amplifies data from the memory cells. The amplification operation in the sense amplifier is divided.

That is, the power consumption reduction circuit of the present invention
In a semiconductor memory [in particular, a dynamic RAM (random access memory) that performs a continuous read operation], when data is continuously read, power consumption is reduced by dividing an operation to be amplified by a sense amplifier.

More specifically, in the power consumption reduction circuit of the present invention, when two sets of 2n cell array blocks belonging to the same row belong to the same row, when data of one cell array block is read, the other cell array block is read. Since the data of the cell array block is prepared halfway and the power consumption in the amplification operation when reading the data of both cell array blocks can be reduced, the data from the memory cells can be continuously and rapidly processed with low power consumption. It becomes possible to read.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 and 2 are circuit diagrams showing a configuration of a cell array according to one embodiment of the present invention. FIG.
Shows the configuration of the cell array CA, and FIG.
Is shown.

In FIG. 1, a cell array CA has m sub-arrays 1-1 to 1-m and sub-arrays 1-1 to 1-m.
m sense amplifiers (SAMP # 1- # SAMP #)
m) The output lines DL2-1 to DL2 of the m sense amplifiers 2-1 to 2-m by a switching signal SW1A activated according to an external address signal (not shown).
-M, and a switching circuit 4 for selecting one of the switching signals S
M decoder circuits (DEC # 1 to DEC # 1) for decoding the sense amplifier activation signal 101 for activating the sense amplifiers 2-1 to 2-m forming a pair with W1A and each of the sub-arrays 1-1 to 1-m #M) 3-1 to 3-m.

The sub-arrays 1-1 to 1-m include memory cells (M11, M12,..., M1m) 11-1 to 11-m, respectively.
m, (M21, M22,..., M2m) 12-1 to 12-12
-M.

In FIG. 2, a cell array CB has m sub-arrays 5-1 to 5-m and sub-arrays 5-1 to 5-m.
m sense amplifiers (SAMP # 1- # SAMP #)
m) The output lines DL6-1 to DL6 of the m sense amplifiers 6-1 to 6-m by the switching signal SW1B activated according to an external address signal (not shown).
-M, and a switching circuit 8 for selecting one of the
M decode circuits (DEC # 1) for decoding a sense amplifier activation signal 201 for activating a sense amplifier paired with W1B and each of the sub-arrays 5-1 to 5-m
-DEC # m) 7-1 to 7-m.

The sub-arrays 5-1 to 5-m respectively include memory cells (M11, M12,..., M1m) 51-1 to 51-m.
m, (M21, M22,..., M2m) 52-1 to 52
-M.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory according to one embodiment of the present invention. 3, a semiconductor memory according to an embodiment of the present invention includes a block A300, a block B400, a switching circuit 500, and a data amplifier 60.
0. Block A300, B400
Are cell arrays CA11 to CA1m,..., CAk1 to CA in which the above-described cell arrays CA and CB are arranged in k rows and 1 columns.
km, CB11 to CB1m, ..., CBk1 to CBkm
And n data lines YL1 to YLn and YLn + 1 to
YL2n.

The cell array output lines YL1 to YL2n of the block A300 and the block B400 are connected to a switching signal SW2.
Is connected by a switching circuit 500 for selecting one of the cell array output lines YL1 to YL2n in accordance with the following formula, and is connected to a data amplifier 600 via an output line YDL of the switching circuit 500.
00 is connected.

FIG. 4 is a timing chart showing an operation of the semiconductor memory according to one embodiment of the present invention, and FIG. 5 is a timing chart showing a comparison operation between the semiconductor memory according to one embodiment of the present invention and a conventional circuit. These FIGS. 1 to 5
The operation of the semiconductor memory according to one embodiment of the present invention will be described with reference to FIG. 4 and 5, the bit lines BL1-1 to BL1-m, BL of the present invention and the conventional example are shown.
5-1 to BL5-m, BL21-1 to BL21-m, B
L31-1 to BL31-m are connected to bit lines BL1 to BL31, respectively.
BLm, and word lines WL1-1, WL1-2, WL5
-1, WL5-2, WL21-1, WL21-2, WL
31-1 and WL31-2 are connected to word lines WL1 and W1, respectively.
L2.

According to the external address signal described above, for example, a desired word line WL1 of each of cell arrays CA11 to CA1n of block A300 and a cell array CB11 to CB1n of block B400 belonging to the same row is selected and connected thereto. Memory cells (M11
To M1m) 11-1 to 11-m and 51-1 to 51-m are read out to the respective bit lines BL1 to BLm.

When amplifying the data read to each of the bit lines BL1 to BLm by the sense amplifiers 2-1 to 2-m and 6-1 to 6-m, in the case of the conventional technique, each of the bit lines BL1 to BLm is amplified.
The sense amplifier activation signal 1 is supplied to all of the sense amplifiers SAMP # 1 to SAMP # m connected to BLm.
01 and 201 are connected in common, and as shown by the solid and broken lines in FIG. 5, when the sense amplifier activating signals 101 and 201 are activated, the sense amplifier SAM
P # 1 to SAMP # m all operate and sense amplifier S
The data of each of the bit lines BL1 to BLm amplified by AMP # 1 to SAMP # m is transferred to a position just before the input terminals of the switching circuits 25 and 35.

On the other hand, in the present embodiment, for example, the switching signals SW1A, SW1 in each of the cell arrays CA11 to CA1n of the block A300 and the cell arrays CB11 to CB1n of the block B400 according to the external address signal.
1B is connected to the sense amplifier output line D in the switching circuits 4 and 8 via the decoder circuits 3-1 to 3-m and 7-1 to 7-m.
Activated to selectively connect L1 to block A30
0 cell array CA11-CA1n and block B4
The data read to DL1 of each of the cell arrays CB11 to CB1n is transferred to the input terminal of the switching circuit 500 via each of the cell array output lines YL1 to YL2n.

Further, the switching signal SW2 is sequentially selected according to the external address signal, and the output line Y of the switching circuit 500 is selected.
Data is transferred to data amplifier 600 via DL. Here, the cell array CA1n in the block A300
And the sense amplifier SAMP # 2 selectively activates the switching signal SW1A in each of the cell arrays CA11 to CA1n in the block A300 at the same time that the output circuit YLn of the cell array CA11 to CA1n in the block A300 has data read out to the YDL in accordance with the switching signal SW2. The signal is switched to a signal for selecting the activation signal 101 and the sense amplifier output line DL2. Block B
The switching signal SW1B in each of the cell arrays CB11 to CB1n in 400 remains activated.

Each cell array CB11 of the block B400
To CB1n output lines YLn + 1 to YL2n
While the data is transferred to the output line YDL of the switching circuit 500 according to W2, the data of the cell arrays CA11 to CA1n in the block A300, that is, the data of the memory cells of the sub-array 21-2, The data is transferred to the input terminal of the switching circuit 500 via the output lines YL1 to YLn of the switching circuit 4.

Each cell array CB11 of the block B400
CB1n through the output lines YLn + 1 to YL2n are sequentially output to the data amplifier 600 in the switching circuit 500, and the switching signal SW2 is activated so as to be sequentially selected again from YL1. Since the memory cell data of the sub-array 21-2 in each cell array has already been read to the output lines YL1 to YLn of each of the cell arrays CA11 to CA1n, the data is continuously output without generating a discontinuous portion in the data output of the switching circuit 500. And can be read.

Therefore, in this embodiment, the cell arrays CA11 to CA1n and CB11 to CB11 to C1n belonging to the 2n same columns of the block A300 and the block B400, which form a pair,
In the case where data is continuously read from the block B1n, when data of one block of the cell arrays CA11 to CA1n is being read, the other cell arrays CB11 to CB are read.
The data of the block B1n can be partially prepared, and the sense amplifiers 2-1 to 2-2 at the time of reading can be prepared.
By dividing the operations of −m, 6-1 to 6-m, power consumption can be reduced by (n−1 subarrays) × (m−1 subarrays). Therefore, data can be read continuously with lower power consumption than the conventional example.

As described above, according to the present invention, the cell arrays CA11 to CA1n and CB11 to CB11 to Cn belonging to the same row of 2n blocks A300 and B400 in pairs.
In the block B1n, one cell array CA11
When data of blocks CA1n to CA1n are being read,
The data of the blocks of the other cell arrays CB11 to CB1n can be prepared halfway, and the power consumption in the amplification operation at the time of reading the data of the blocks of both cell arrays CA11 to CA1n and CB11 to CB1n can be reduced. it can. Therefore, data from the memory cell can be read continuously at high speed with low power consumption.

[0027]

As described above, according to the present invention, a sense amplifier for amplifying data from a memory cell when reducing power consumption when reading data continuously in a semiconductor memory composed of a plurality of memory cells. By dividing the amplifying operation of the memory cell, the data from the memory cell can be read continuously at high speed with low power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a cell array according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a cell array according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory according to one embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the semiconductor memory according to one embodiment of the present invention.

FIG. 5 is a timing chart showing a comparison operation between a semiconductor memory according to one embodiment of the present invention and a conventional circuit.

FIG. 6 is a circuit diagram showing a configuration of a cell array according to a conventional example.

FIG. 7 is a circuit diagram showing a configuration of a cell array according to a conventional example.

[Explanation of symbols]

 1-1 to 1-m, 5-1 to 5-m Subarray 2-1 to 2-m, 6-1 to 6-m Sense amplifier 3-1 to 3-m, 7-1 to 7-m Decoder circuit 4,8,500 Switching circuit 11-1 to 11-m, 12-1 to 12-m, 51-1 to 51-m, 52-1 to 52-m Memory cell 300 Block A 400 Block B 600 Data amplifier 700 Internal bus line SW1A, SW1B, SW2 Switching signal 101, 201 Sense amplifier activation signal

Claims (8)

[Claims] 1. A power consumption reduction circuit for reducing power consumption when reading data continuously in a semiconductor memory including a plurality of memory cells, comprising: an amplifying operation performed by a sense amplifier for amplifying data from the memory cells. A power consumption reduction circuit having means for performing division processing. 2. The semiconductor memory comprises two pairs of cell array blocks, and when one of the two sets of cell array blocks is being read, the other half of the two sets of cell array blocks is transferred halfway. The power consumption reducing circuit according to claim 1, wherein the circuit is prepared. 3. The method according to claim 1, wherein the means for dividing the amplification operation in the sense amplifier performs the amplification operation in the sense amplifier in response to a signal instructing switching of an output line of the sense amplifier. 3. The power consumption reducing circuit according to claim 1, wherein: 4. A means for dividing an amplification operation in the sense amplifier, decodes a signal instructing switching of an output line of the sense amplifier and a signal for activating the sense amplifier, and decodes the decoding result. 4. The power consumption reducing circuit according to claim 3, further comprising a decoding circuit for activating said sense amplifier. 5. A power consumption reducing method for reducing power consumption when reading data continuously in a semiconductor memory including a plurality of memory cells, comprising: amplifying operation by a sense amplifier for amplifying data from the memory cells. A power consumption reduction method characterized by performing a division process. 6. The semiconductor memory includes two pairs of cell array blocks, and when one of the two sets of cell array blocks is being read, the other half of the two sets of cell array blocks is partially transferred. 6. The power consumption reducing method according to claim 5, wherein said method is prepared. 7. When the amplification operation of the sense amplifier is divided, the amplification operation of the sense amplifier is performed in response to a signal instructing switching of an output line of the sense amplifier. The power consumption reduction method according to claim 5 or 6, wherein 8. A signal for instructing switching of an output line of the sense amplifier and a signal for activating the sense amplifier are decoded by a decoding circuit when dividing the amplification operation of the sense amplifier. 8. The method according to claim 7, wherein the sense amplifier is activated based on a result of the decoding.