JP2002287688A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the adjustment of luminance possible during assembling a panel body. SOLUTION: The display device is equipped with a display panel 2, a display panel (organic EL display) driving driver 7 to drive the display panel 2, and a nonvolatile memory (second ROM 8) in which the data for adjusting luminance of the display panel 2 is stored. The organic EL display driving driver 7 adjusts the luminance of the display panel 2 based on the data for adjusting the luminance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device,
More specifically, the present invention relates to a brightness adjustment mechanism in a display device used for a mobile phone or the like.

[0002]

2. Description of the Related Art Here, the above display devices include LCD displays, LED displays, organic EL (electroluminescence) displays, inorganic EL displays, PDPs (plasma displays), FEDs (field emission displays), and the like. There are various flat panel displays.

[0003] As an example, an organic EL display, which is expected to expand its use for mobile phones and the like, will be described below. Since the EL element is self-luminous, it does not require a backlight necessary for a liquid crystal display device, and has many advantages such as no limitation on the viewing angle. Application is expected. In particular, it is known that an organic EL element is capable of high luminance, and is superior to an inorganic EL element in terms of high efficiency, high response characteristics, and multicoloring.

Hereinafter, the configuration of the organic EL display will be described with reference to the drawings.

[0005] In FIG. 14, reference numeral 1 denotes a panel main body. The panel main body 1 includes, for example, a display panel, a controller 3, an anode driver and a cathode driver, and supplies a constant current to an organic EL element to thereby control the organic EL element. A drive driver 4 and the like for causing the elements to emit light are mounted.

[0006] The controller 3 is connected to an MPU (Micro Processing Unit) 5 separately from the panel main body 1, and the MPU 5 is connected to a ROM 6 for storing various program data for the organic EL display.

[0007]

Normally, when it is desired to adjust the brightness of the panel screen in the above display device, the brightness data stored in the ROM 6 must be changed at the time of inspection before shipment after the completion of assembly. To set the desired brightness,
It was then shipped.

However, in recent years, in order to improve the efficiency of manufacturing control, the MPU, that is, during the assembly operation of the panel body, has been performed.
There has been a demand that various kinds of adjustment work including the above-described brightness adjustment and the like should be performed from an initial stage in an assembly work in a state of the panel body alone before being connected to the panel body 5.

[0009]

Therefore, a display device of the present invention comprises a display panel in a panel body, a display panel driving driver for driving the display panel, and data for adjusting the luminance of the display panel. A display panel driving driver that adjusts the brightness of the display panel based on the brightness adjustment data.

The non-volatile memory is constituted by a non-volatile memory in which the brightness adjustment data can be electrically rewritten, so that the brightness of the panel screen can be adjusted.

Further, the nonvolatile memory is a split gate type nonvolatile memory having a floating gate and a control gate.

Still further, the display panel is characterized by comprising an organic EL display.

This makes it possible to adjust the brightness of the panel screen during the assembly work of the display panel.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the display device of the present invention will be described with reference to the drawings. In the present embodiment, an organic EL display, which is being put to practical use for various uses such as a mobile phone, is illustrated as an example of a display device.

First, a description will be given of a semiconductor device in which various MOS transistors constituting a driver for driving an organic EL display mounted on the organic EL display are mounted.

The driver for driving the organic EL display has a logic system (for example, 3) from the left side of FIG.
V) N-channel MOS transistors and P-channel MOS transistors, for level shifters (for example, 30
V) N-channel MOS transistor, high breakdown voltage (for example, 30 V) N-channel MOS transistor, FIG.
A high breakdown voltage (eg, 30 V) N-channel MOS transistor whose on-resistance is reduced from the left side of 0 (b),
It is composed of a high-breakdown-voltage (for example, 30 V) P-channel MOS transistor and a high-breakdown-voltage (for example, 30 V) P-channel MOS transistor whose on-resistance is reduced.

For convenience of explanation, the high breakdown voltage MOS
Transistor and high breakdown voltage MO with low on-resistance
In order to differentiate the S transistor from the S transistor, in the following description, a high withstand voltage MOS transistor having a reduced on-resistance is replaced by an SLED (Slit channel by counter doping with exten).
ded shallow drain) MOS transistor.

In a semiconductor device in which various MOS transistors constituting such an organic EL display driving driver are mounted, as shown in FIG. 10, the high breakdown voltage P-channel MOS transistor and the low on-resistance are reduced. The N-type well 23 in which the illustrated high-withstand-voltage P-channel SLEDMOS transistor is formed is a high step portion, and the P-type well 22 in which other various MOS transistors are formed is in the low step portion. In other words, a fine logic (eg, 3V) N-channel MOS
The configuration is such that the transistor and the P-channel MOS transistor are arranged at the lower part of the step.

Hereinafter, a method of manufacturing the semiconductor device will be described.

First, in FIG. 1, in order to define regions for forming various MOS transistors, for example, P
A P-type well (P-sub) is formed in a P-type semiconductor substrate (P-sub) 21.
W) 22 and an N-type well (NW) 23 are formed by using the LOCOS method. That is, although the illustrated description is omitted, a pad oxide film and a silicon nitride film are formed on the N-type well formation region of the substrate 21 and, for example, boron ions are At an acceleration voltage of 80 KeV, ions are implanted under an implantation condition of 8 × 10 ¹² / cm ² to form an ion-implanted layer. Then, using the silicon nitride film as a mask,
The LOCOS film is formed by performing field oxidation by the S method. At this time, the boron ions implanted below the LOCOS film formation region are diffused into the substrate to form a P-type layer.

Next, the pad oxide film and the silicon nitride
After removing the film, the substrate surface is exposed using the LOCOS film as a mask.
Phosphorus ions are applied to the surface at an acceleration voltage of about 80 KeV,
10 ¹²/ Cm^TwoImplantation under the same implantation conditions
Form a layer. Then, after removing the LOCOS film
Then, each impurity ion implanted into the substrate is thermally diffused.
By forming a P-type well and an N-type well, FIG.
A P-type well 2 formed in the substrate 21 as shown in FIG.
2 is located at the low step, and the N-type well 23 is at the high step.
Be placed.

In FIG. 2, an element isolation film 24 of about 500 nm is formed by the LOCOS method in order to isolate an element for each MOS transistor, and a high-level of about 80 nm is formed on an active region other than the element isolation film 24. A thick gate oxide film 25 for withstand voltage is formed by thermal oxidation.

Subsequently, a first low-concentration N-type and P-type source / drain layer (hereinafter referred to as L
These are referred to as an N layer 26 and an LP layer 27. ) Is formed. That is, first, the substrate surface in a state of covering the region other than the LN layer forming region with a resist film (not shown), for example, phosphorus ions at an acceleration voltage of approximately 120 KeV, an implantation condition of 8 × 10 ¹² / cm ² Thus, the LN layer 26 is formed. Thereafter, for example, boron ions are applied to the surface layer of the substrate at an acceleration voltage of about 120 KeV at a rate of 8.5 × 10 ¹² / cm while the area other than the area where the LP layer is formed is covered with the resist film (PR).
^The LP layer 27 is formed by ion implantation under the implantation conditions of ² .
Note that, in practice, a subsequent annealing step (for example, 1100
After 2 hours in a N ₂ atmosphere at a temperature of ₂ ° C., the ion-implanted ion species are thermally diffused to form the LN layer 26 and the LP layer 27.

In FIG. 3, second resistive films are used as masks between the LN layers 26 and the LP layers 27 where the P-channel type and N-channel type SLED MOS transistor forming regions are formed, respectively. And P-type source / drain layers (hereinafter, SLN layer 28 and SLP
Called layer 29. ) Is formed. That is, first, for example, phosphorus ions are applied to the surface of the substrate in a state of covering the region other than the SLN layer formation region with a resist film (not shown) for about 120 Ke.
At an acceleration voltage of V, ions are implanted under an implantation condition of 1.5 × 10 ¹² / cm ² to form an SLN layer 28 connected to the LN layer 26. Then, for example, boron difluoride ion ( ⁴⁹ BF ₂ ⁺ ) is applied to the surface of the substrate in a state where the region other than the region where the SLP layer is to be formed is covered with the resist film (PR).
At an acceleration voltage of V, ions are implanted under an implantation condition of 2.5 × 10 ¹² / cm ² to form an SLP layer 29 connected to the LP layer 27. The impurity concentration of the LN layer 26 and the SLN layer 28 or the impurity concentration of the LP layer 27 and the SLP layer 29 is as follows.
They are set so that they are almost the same or one of them is higher.

Further, in FIG. 4, the resist film is masked.
High-concentration N-type and P-type source / drain layers
Below, they are referred to as an N + layer 30 and a P + layer 31. ) Is formed. Immediately
First, a resist film (not shown) other than on the N + layer forming region
In the state of covering the area of the substrate, for example, phosphorus ions
At an acceleration voltage of about 80 KeV and 2 × 10¹⁵/ Cm ^Two
The N + layer 30 is formed by ion implantation under the implantation conditions described above. So
After that, the resist film (PR) is used to cover areas other than the P + layer formation area.
In the state where the area is covered, for example, boron difluoride
The ions were accelerated at about 140 KeV and 2 × 10¹⁵
/ Cm^TwoP + layer 31 by ion implantation under the following implantation conditions
I do.

Next, referring to FIG. 5, a resist film having an opening diameter smaller than the mask opening diameter (see FIG. 3) for forming the SLN layer 28 and the SLP layer 29 is used as a mask. The central part of the layer 28 and the LP
By injecting impurities of the opposite conductivity type into the central portion of the SLP layer 29 connected to the layer 27, respectively,
Then, a P-type body layer 32 and an N-type body layer 33 that divide the SLP layer 29 are formed. That is, first, for example, boron difluoride ions are applied to the surface of the substrate in a state in which the resist film (not shown) covers an area other than the P-type layer forming area, for example, about 120 nm.
The P-type body layer 32 is formed by ion implantation at an acceleration voltage of KeV under the conditions of 5 × 10 ¹² / cm ² . afterwards,
With the resist film (PR) covering the area other than the N-type layer forming area, for example, about 1
Ion implantation is performed at an acceleration voltage of 90 KeV under an implantation condition of 5 × 10 ¹² / cm ² to form an N-type body layer 33. still,
The order of the operation steps related to the ion implantation step shown in FIGS. 3 to 5 can be appropriately changed.
Channels are formed in the surface layers of the 2 and N-type body layers 33.

Further, in FIG. 6, a second P-type well (SPW) 34 and a second P-type well (SPW) 34 are formed in the substrate (P-type well 22) in the miniaturized N-channel type and P-channel type MOS transistor formation region for the normal breakdown voltage. N-type well (SNW) 35
To form

That is, the normal breakdown voltage N-channel MOS
A resist (not shown) having an opening on the transistor formation region
In the P-type well 22, for example,
Ion at an accelerating voltage of about 190 KeV and 1.5
× 10¹³/ Cm^TwoAfter the ion implantation under the first implantation condition of
With the acceleration voltage of about 50 KeV,
2.6 × 10¹²/ Cm^TwoImplantation under the second implantation condition
Thus, a second P-type well 34 is formed. In addition,
On P-channel MOS transistor formation region for normal withstand voltage
Using a resist film (PR) having an opening in the mask as a mask,
For example, about 380 K of phosphorus ions are
1.5 × 10 at eV acceleration voltage¹³/ Cm ^TwoInjection conditions
To form a second N-type well 35.
In addition, when there is no high acceleration voltage generator of about 380 KeV
In the case of divalent phosphorus ions, about 190 KeV
1.5 × 10 at pressure¹³/ Cm^TwoImplantation under the same implantation conditions
Double charging method may be used. Then, add phosphorus ions
At an acceleration voltage of about 140 KeV, 4.0 × 10¹²/ C
m^TwoIs implanted under the implantation conditions of

Next, after removing the gate oxide film 25 on the N-channel type and P-channel type MOS transistor forming regions for normal breakdown voltage and on the N-channel type MOS transistor forming region for level shifters, as shown in FIG. To
A gate oxide film having a desired thickness is newly formed on this region.

That is, first, the entire surface is about 14 nm for an N-channel type MOS transistor for a level shifter (about 7 nm at this stage, but the film thickness increases when a later-described gate oxide film for normal withstand voltage is formed). .)
Is formed by thermal oxidation. continue,
After removing the gate oxide film 36 of the level shifter N-channel type MOS transistor formed on the N-type and P-channel type MOS transistor formation regions for normal withstand voltage, a thin gate oxide film for normal withstand voltage is formed in this region. 37 (about 7 nm) is formed by thermal oxidation.

Subsequently, as shown in FIG.
A polysilicon film having a thickness of about 0 nm is formed, the POCl ₃ is thermally diffused into the polysilicon film using a thermal diffusion source to make the polysilicon conductive, and then a tungsten silicide film having a thickness of about 100 nm is formed on the polysilicon film. A gate electrode 38A, 38B, 38C, 38D, 38E, 38F, 3 for each MOS transistor is formed by laminating an SiO ₂ film and patterning using a resist film (not shown).
8G is formed. The SiO ₂ film functions as a hard mask during patterning.

Subsequently, in FIG. 9, low-concentration source / drain layers are formed for the normal breakdown voltage N-channel type and P-channel type MOS transistors.

That is, first, an N-channel type M for normal withstand voltage is used.
Low concentration source / drain layer formation area for OS transistor
Mask the resist film (not shown) that covers the area other than the area
Then, for example, the phosphorous ion is accelerated by about 20 KeV.
By pressure, 6.2 × 10¹³/ Cm ^TwoImplantation under the same implantation conditions
To form a lightly doped N− type source / drain layer 39.
You. Also, a P-channel MOS transistor for normal withstand voltage
Area except on the low concentration source / drain layer formation area
Using the resist film (PR) covering the mask as a mask, for example,
Acceleration voltage of about 20 KeV for boron difluoride ion
And 2 × 10¹³/ Cm^TwoIon implantation under the implantation conditions of
A low concentration P- type source / drain layer 40 is formed.

Further, in FIG. 10, the gate electrodes 38A, 38B, 38C, 38D, 38E, 38
F, T of about 250 nm to cover 38G
An EOS film 41 is formed by an LPCVD method, and the TEOS film 41 is anisotropically etched using a resist film (PR) having an opening on the N-type and P-channel type MOS transistor formation regions for normal breakdown voltage as a mask. .
As a result, as shown in FIG.
A, side wall spacer films 41 on both side walls of 38B
A is formed, and the TEOS film 41 remains in a region covered with the resist film (PR).

The gate electrode 38A, the side wall spacer film 41A, and the gate electrode 38B
Using the sidewall spacer film 41A as a mask, a high-concentration source / drain layer is formed for the normal breakdown voltage N-channel and P-channel MOS transistors.

That is, by using a resist film (not shown) covering a region other than the region for forming the high-concentration source / drain layer for the N-channel MOS transistor for normal withstand voltage as a mask, for example, an arsenic ion is accelerated at about 100 KeV. Then, ion implantation is performed under an implantation condition of 5 × 10 ¹⁵ / cm ² ,
A high concentration N + type source / drain layer 42 is formed. Also, using a resist film (not shown) covering a region other than the region for forming the high-concentration source / drain layer for the normally-breakdown-voltage P-channel MOS transistor as a mask, for example, boron difluoride ion at an acceleration voltage of about 40 KeV , 2 ×
Ion implantation is performed under an implantation condition of 10 ¹⁵ / cm ² to form a high concentration P + type source / drain layer 43.

Although not shown in the drawings, the entire surface is made of a TEOS film, a BPSG film, etc.
After forming an interlayer insulating film of about the same degree, a metal wiring layer is formed to be connected to each of the high-concentration source / drain layers 30, 31, 42, and 43 to form the organic EL display driving driver. N-channel MOS transistor and P-channel MOS transistor for breakdown voltage, N-channel MOS transistor for level shifter, N-channel MOS transistor and P-channel MOS transistor for high breakdown voltage, high breakdown voltage with reduced on-resistance N-channel SLEDMOS transistor and P-channel SLEDMOS transistor are completed (see FIG. 10).

Subsequently, referring to FIG. 11, an anode driver and a cathode are used in an organic EL display driving driver or the like for supplying a constant current to the organic EL element (organic electroluminescence element) and causing the organic EL element to emit light. A description will be given of an efficient pattern layout when a driver and a memory unit for storing display data and the like and a controller and the like are integrated into one chip.

The outline of the pattern layout configuration will be described below with reference to simplified drawings.

In FIG. 11, an anode driver, a cathode driver, a memory section, a controller and the like are integrated into one chip, and a 32-bit anode (segment: SEG) driver area 10 and a 128-bit cathode (common) are arranged from the upper left of FIG. : COM) driver area 11, 32-bit anode driver area 12, 32-bit anode driver area 13, 10-bit icon anode driver area 14, 10-bit icon anode driver areas 15, 32 from bottom left A bit anode driver area 16 is arranged. In each driver area, a desired output bit group is formed by repeatedly arranging an output area corresponding to one output bit for a required output.

A symmetrical position (a left-right symmetric position in the present embodiment) via another logic (LOGIC) portion 17 at the center of the chip may be a vertically symmetrical position in accordance with the arrangement in the chip. ) SRAM as memory part
(Static RAM) 18 and 19 are arranged,
Output wires 20 from the RAMs 18 and 19 are connected to the anode driver regions 10, 12, 13 and 16, respectively.

As described above, according to the present invention, the anode drivers connected to the SRAM are arranged at the four corners in the chip, and the anode drivers 10, 12, 13, and 16 are combined with the SRAMs.
Is divided into two, and corresponds to the group of the anode driver regions 10 and 13 arranged at the left end of the chip and the group of the anode driver regions 12 and 16 arranged at the right end of the chip, respectively. In this case, the wiring space can be easily reduced, so that the wiring space can be reduced, and the chip size can be reduced accordingly.

Hereinafter, the structure of the display device, which is a feature of the present invention, will be described with reference to FIG. In addition, the same reference numerals are given to the same configurations as the conventional configuration (FIG. 14) to avoid redundant description, and the description will be simplified.

In FIG. 12, reference numeral 1 denotes a panel main body, in which a display panel 2, an organic EL display driving driver 7 in which an anode driver, a cathode driver, a memory section, a controller and the like are integrated into one chip, and the like. It is installed.

A controller mounted in the driver 7 for driving the organic EL display is connected to an MPU (Micro Processing Unit) 5 separately from the inside of the panel main body 1. First RO for storing program data etc.
Connected to M6A.

In the panel main body 1, a second ROM 8, which is a feature of the present invention, is connected to the controller. The second ROM 8 stores data of relatively limited use, such as brightness adjustment data, for example, and does not need to be a large-capacity memory.
In this embodiment, a nonvolatile memory such as a 256-bit EEPROM or a flash memory is mounted.

FIG. 13 shows, as an example of the above-mentioned nonvolatile memory, a floating gate (FG) formed on a semiconductor substrate through a gate insulating film and a floating gate (FG) formed through a tunnel insulating film covering the floating gate. FIG. 3 is an equivalent circuit diagram of a split gate nonvolatile memory including a control gate (CG) formed so as to extend from the side to the top.

Referring to FIG. 13, each memory cell MC1, M
Each of C2, MC3, MC4,... Corresponds to one bit, and in the present embodiment, 128 memory cells are provided in parallel. Here, BL is a bit line connected to the drain region, and WL1, WL2, WL3, and WL4 are word lines connected to each control gate of each of the memory cells MC1, MC2, MC3, and MC4.
Are the memory cells MC1, MC2 and the memory cell MC.
3 is a source line commonly connected to the source region of MC4.

The operation of writing / erasing / reading data to / from the memory cell is performed as follows.

That is, in the write operation, the potential of the control gate is set to 2 V, and the potential of the drain region is set to 0.5
V and the high potential of the source region is 12V. This allows
By applying a high potential to the source region, the potential of the floating gate is raised to about 9 V by the coupling ratio between the source region and the floating gate, and the vicinity of the channel region below the region where the floating gate and the control gate are juxtaposed. Is injected into the floating gate through the gate insulating film to write data.

On the other hand, in the erase operation, the potentials of the drain region and the source region are set to 0 V, and the control gate is set to 14 V. As a result, charges (electrons) accumulated in the floating gate are transferred from the acute angle of the upper corner of the floating gate to the FN (Fowler-Nordheim).
The data is erased by being transmitted to the control gate through the tunnel insulating film by tunneling conduction.

In the read operation, the potential of the control gate is set to 4 V, the drain region is set to 2 V,
The source region is set to 0V. At this time, if charges (electrons) are injected into the floating gate, the potential of the floating gate is lowered, so that no channel is formed below the floating gate and no drain current flows. Conversely, if charges (electrons) are not injected into the floating gate, the potential of the floating gate increases, so that a channel is formed below the floating gate and a cell current (read current) flows.

In this embodiment, the memory cells MC1 and MC2 and the memory cells MC3 and MC4 adjacent to each other are arranged to face each other, and the source lines SL1 and SL2 are made common to enable high integration. However, the present invention is not limited to this, and a source line may be formed for each memory cell.

As described above, according to the present invention, the driver 7 for driving the organic EL display is provided in the panel body 1.
By providing the second ROM 8 composed of a non-volatile memory connected to a controller mounted in the inside of the panel main body, during the assembly work of the panel main body 1, that is, in the state of the panel main body alone before being connected to the MPU 5, Various adjustment operations including brightness adjustment and the like can be performed from an early stage in the assembly operation, and the efficiency of manufacturing management can be improved.

In the present embodiment, for example, the controller, the memory, the anode driver, the cathode driver, and the like are integrated into one chip as in the driver 7 for driving the organic EL display to reduce the chip size. There is no need to secure a space for mounting the second ROM 8 in the panel main body 1 and to secure a space for the second ROM 8. Therefore, it does not hinder application to light and thin devices such as mobile phones.

More specifically, the data stored in the second ROM 8 is limited to storing only relatively limited data used for adjusting a panel screen, such as brightness adjustment data. The ROM 8 does not need to have a large capacity, and it is not difficult to secure an arrangement space. In addition, a ROM having the function of the first ROM 6A together with the second ROM 8 may be mounted in the panel body 1. In this case, as described above, the first ROM
6A has a large capacity because it is necessary to store all data relating to the display device including various program data and the like.

In the present invention, the second ROM 8 is
It may be configured as one chip together with the driver 7 for driving the organic EL display.

In this embodiment, an organic EL display has been described as an example of a display device, but the present invention is not limited to this. For example, an LCD display, LED display, inorganic EL display, PD
P (plasma display), FED (field
This is applicable to various flat panel displays such as emission displays.

[0059]

According to the present invention, the provision of the non-volatile memory in the panel main body makes it possible to perform the brightness adjustment work during the assembly work of the panel main body, and the efficiency of manufacturing management can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating the method for manufacturing a semiconductor device of the present invention;

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating the method for manufacturing a semiconductor device of the present invention;

FIG. 11 is a plan view showing a pattern layout of the semiconductor device of the present invention.

FIG. 12 is a plan view showing a display device of the present invention.

FIG. 13 is an equivalent circuit diagram of a nonvolatile memory mounted on a display device of the present invention.

FIG. 14 is a plan view showing a conventional display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Panel main body 2 Display panel 5 MPU 6A 1st ROM 7 Organic EL display drive driver 8 2nd ROM

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/30 G09G 3/30 K H01L 21/8238 H01L 27/10 461 27/092 27/08 321C 27 / 10 461 F-term (reference) 5C080 AA06 BB05 DD25 DD28 EE28 JJ02 JJ06 KK07 KK47 5F048 AB01 AB03 AB07 AB10 AC01 AC03 BA01 BB05 BB08 BB16 BC06 BC07 BE03 BE06 BE09 BG12 DA25 5F083 EP02 EP24 ZA13 BB13 BB07

Claims (4)

[Claims] 1. A display panel in a panel body, a display panel driving driver for driving the display panel,
A non-volatile memory storing brightness adjustment data of the display panel, wherein the display panel driving driver performs brightness adjustment of the display panel based on the brightness adjustment data. apparatus. 2. The non-volatile memory according to claim 1, wherein the non-volatile memory comprises a non-volatile memory in which the luminance adjustment data is electrically rewritable, and the luminance of the display panel screen can be adjusted. The display device according to the above. 3. The non-volatile memory according to claim 1, wherein the non-volatile memory is a split gate type non-volatile memory having a floating gate and a control gate.
Alternatively, the display device according to claim 2. 4. The display device according to claim 1, wherein the display panel comprises an organic EL display.