JP2002286801A - Asic internal state analyzer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that it requires much time to analyze the failure of a printed circuit board or ASIC itself because the conventional ASIC internal state analyzer only converts bit patterns of 0 and 1 showing the state of an internal register at a unit of bit or sexadecimal and indicates the result, and an analyist analyzes the indicated bit pattern string referring to the scan order list of the ASIC every bit. SOLUTION: This ASIC internal state analyzer that analyzes the failure of a printed circuit board including the ASIC by analyzing the internal state of the ASIC, is provided with a means to indicate the internal state of the ASIC according to a scan order list, or at a united unit of a register or the like, thus efficiently analyzing the internal state of the ASIC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ASIC internal state analyzer for analyzing a failure of a printed circuit board including an ASIC by analyzing the internal state of the ASIC. By displaying the data in a unit such as, for example, the analysis of the internal state of the ASIC is made more efficient.

[0002]

2. Description of the Related Art As the scale and speed of LSIs increase, the speed and density of printed circuit boards have rapidly increased. However, with the progress thereof, design debugging and failure analysis of a printed circuit board have become increasingly difficult.

[0003] The reasons can be roughly classified as follows. (1) Analysis devices such as logic analyzers are becoming obsolete.・ The sampling frequency is slow. -Insufficient number of channels. -The impedance of the printed circuit board cannot be matched. (2) The bus protocol is becoming more complicated. (3) It is becoming difficult to mount a debug connector on a printed circuit board.

[0004] For these reasons, attention has been paid to a method of analyzing the internal state of an ASIC and finding the cause of the failure based on the analysis result as a method for supplementing the failure analysis of the printed circuit board.

FIG. 11 is a block diagram showing the configuration of a conventional ASIC internal state analyzer. In the figure, 1110 is ASI
A printed circuit board including C, a computer 1120,
Reference numeral 1130 denotes an input / output unit including a display unit such as a display and input units such as a keyboard and a mouse. Reference numeral 1140 denotes a storage unit that stores a scan order list 1141 and an internal register data file 1144.

[0006] The scan chain is designed to improve the ASIC failure detection rate by using a scan insertion program, which is one of the programs used when designing an ASIC.
The scan input and the scan output of each flop in the IC are sequentially (sequentially) connected. The scan order list 1141 is output when the scan chain is connected, and is output when the scan chain is connected to the ASIC. This file stores the order of flip-flops.

The internal register data file 114
4 is an analysis unit 112 executed by the computer 1120
Reference numeral 1 denotes a file in which data (state) of an internal register read by scanning a flip-flop inside the ASIC for a predetermined ASIC mounted on the printed circuit board 1110 is stored.

FIG. 12 shows an internal configuration diagram of a conventional ASIC. In the internal logic of the ASIC, flip-flops (FFs) mainly forming registers and the like are arranged, and a scan chain connecting scan inputs and scan outputs in each FF in order is provided. The scan chain is connected to a TAP (Test Access Port) controller, and the state of each FF can be read out through the TAP controller when necessary.

FIG. 13 shows an example of a display screen of internal register data in a conventional analysis unit. In this example, the internal register data of the ASIC read under control of the TAP controller is set to 0,
1 bit pattern string, ASI corresponding to the lower part
The C scan order list is read from the storage unit and displayed.

[0010]

As described above, the conventional A
The SIC internal state analyzer only converts the bit pattern of 0 and 1 indicating the state of the internal register extracted from the ASIC into a bit unit or a hexadecimal number and displays the converted bit pattern. , ASIC
The scan order list of the ASIC is analyzed while being compared bit by bit, so that it takes a lot of time to analyze the internal state of the ASIC, and the printed circuit board or the AS
There is a problem that it takes time to analyze the failure of the IC itself.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and a failure analysis of a printed circuit board including an ASIC is performed by analyzing an internal state of the ASIC. In the state analyzer, A
By providing a means for displaying the internal state of the SIC in a unit based on the scan order list or in a unit such as a register, the internal state of the ASIC is analyzed efficiently.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) In an ASIC internal state analyzer for analyzing a failure of a printed circuit board including an ASIC by analyzing an internal state of the ASIC, an ASIC to be analyzed is internally scanned through a scan chain. A reads the data of the register and sets A to be analyzed.
An analysis means is provided for acquiring the scan order list of the SIC from the storage unit and displaying the read data of the internal register of the ASIC in an easy-to-understand display format in association with the acquired scan order list. Accordingly, the internal state of the ASIC can be analyzed quickly and easily, and the failure analysis of the printed circuit board or the ASIC itself can be performed in a short time.

(2) In the ASIC internal state analyzer according to (1), A is used as a data register in the ASIC.
Means for providing an identification register for storing the identification code and the version number of the SIC, acquiring the identification code and the version number of the ASIC from the identification register, and acquiring the scan order list corresponding to the acquired identification code and the version number from the storage unit. Provide. This makes it possible to automatically obtain the scan order list of the ASIC to be analyzed.

(3) The ASIC according to (1) or (2)
In the internal state analyzer, there is provided means for displaying the internal register data extracted from the ASIC in association with the scan order list. Accordingly, the internal state of the ASIC can be analyzed quickly and easily, and the failure analysis of the printed circuit board or the ASIC itself can be performed in a short time.

(4) The ASIC according to (1) or (2)
In the internal state analyzer, there is provided means for displaying the internal register data extracted from the ASIC in register units based on the scan order list. As a result, AS
The internal state of the IC can be analyzed quickly and easily, and failure analysis of the printed circuit board or the ASIC itself can be performed in a short time.

(5) The ASIC according to (3) or (4)
In the internal state analysis device, an alias table in which an instance of a flip-flop or a predetermined register in the scan order list is defined by an easy-to-remember name is provided.
When the internal register data extracted from C is displayed in association with the scan order list, or when it is displayed on a register basis based on the scan order list, a means is provided for adding or replacing an alias with the alias. Accordingly, the internal state of the ASIC can be analyzed quickly and easily, and the failure analysis of the printed circuit board or the ASIC itself can be performed in a short time.

(6) In the ASIC internal state analyzer according to (3), (4) or (5), registers extracted and displayed from the scan order list, group configurations in which the displayed registers are grouped, and A display condition file for defining a display format and the like is provided, and means for displaying internal register data extracted from the ASIC in a display format defined in the display condition file is provided. This allows
The internal state of the ASIC can be analyzed quickly and easily, and failure analysis of the printed circuit board or the ASIC itself can be performed in a short time.

[0018]

FIG. 1 is a block diagram showing the configuration of an ASIC internal state analyzer according to the present invention. In the drawing, reference numeral 10 denotes a printed circuit board including an ASIC provided with an identification register 11;
0 is a computer, 30 is an input / output unit having a display unit such as a display and an input unit such as a keyboard and a mouse, 40 is a scan order list 41, an alias table 4
2. A storage unit for storing the display condition file 43 and the internal register data file 44.

The scan chain is designed so that a scan insertion program, which is one of the programs used when designing an ASIC, increases the failure detection rate of the ASIC.
The scan input and scan output of each flop in the IC are sequentially (sequentially) connected. The scan order list 41 is output when the scan chain is connected, and is output when the scan chain is connected to the ASIC. This file stores the order of flip-flops.

The internal register data file 44
Is a file in which the data (state) of the internal register read by the analysis unit 21 executed by the computer 20 by scanning a predetermined ASIC of the printed circuit board 10 is stored.

The alias table 42 is a table in which the same register or a predetermined register in the scan order list is defined by an alias that is easy to remember.
When displaying the internal register data of the SIC, the alias defined in the alias table 42 is added instead of the internal register name or beside the internal register display,
Used to display the status of internal registers in an easy-to-understand manner.

The display condition file 43 is a file for designating registers to be extracted and displayed from the scan order list, defining a group configuration of the registers to be displayed, their display format, and the like. Displays the internal register data of the ASIC, the registers defined in the display condition file 43,
The display according to the display format is used to customize and display the state of the internal register in an easily understandable manner.

FIG. 2 shows an internal configuration diagram of the ASIC of the present invention. In the internal logic of the ASIC, flip-flops (FFs) mainly forming registers and the like are arranged, and a scan chain connecting scan inputs and scan outputs in each FF in order is provided. The scan chain is connected to a TAP (Test Access Port) controller, and the state of each FF can be read out through the TAP controller when necessary.

As an ASIC data register,
Identification register 1 for storing ASIC identification code and version number
1 is provided. The data in the identification register 11 can be read by controlling the TAP controller. In this example, the identification code of the identification register 11 is a numeral or an alphabetic character. However, an alphabetic character and a numeral may be combined. In this example, the identification code and the version number are provided in one data register, but they may be provided separately in two data registers.

FIG. 3 shows an embodiment of the scan order list. The normal scan insertion program is ASI
Since the scan chain is set up regardless of the logical connection in C, the scan order list to be created has the configuration bits of one register scattered in this way.

FIG. 4 shows an embodiment of the alias table. In this example, an internal register name is defined on the left side, and an alias of the internal register is defined on the right side. In addition,%
Means an arbitrary character string, for example, "y_
“reg_%” is “y” in the scan order list in FIG.
_Reg — 7-0 ”.

FIG. 5 shows an embodiment of the display condition file. This example is a display condition file defined in a C language style. The definition of the configuration of a group (internal register) displayed by “Display_group”, “Displ.
ay_style "defines the display format. The display data is defined by “Display”.

FIG. 6 shows a processing flowchart of an embodiment of the analyzing means of the present invention. Hereinafter, the operation will be described according to this flow.

Step S601: A scan is executed and A
The internal register data of the SIC is read, expanded in the memory, and stored in the storage unit.

Step S602: The identification register is read, and the identification code and the version number of the ASIC are obtained.

Step S603: The scan order list and the alias table corresponding to the identification code and the version number are read from the storage unit. Note that the file name of the scan order list stored in the storage unit is a name obtained by adding the version number to the identification code of the ASIC. For example, in the example of FIG.
C_AAA01 ". The file name of the alias table stored in the storage unit is a name obtained by adding the version number to the identification code of the ASIC before “_alias”. For example, in the example of FIG. 4, "ASIC_AAA01_alia"
s ".

Step S604: It is determined whether the setting of the display menu is the order list display. If the order list is displayed, the process proceeds to step S605; otherwise, the process proceeds to step S606.

Step S605: Display data for displaying the internal register data corresponding to the scan order list is generated, and the data is sorted, rearranged and displayed on the display unit. Then, the process proceeds to step S612.

Step S606: It is determined whether the setting of the display menu is the register configuration display. If the display is the register configuration display, the process proceeds to step S607. If the display is not the register configuration display, the process proceeds to step S609.

Step S607: Display data for displaying the internal register data corresponding to the scan order list is generated, and the data is sorted and rearranged.

Step S608: The rearranged data is edited into a register configuration and displayed on the display unit. At this time, if the alias designation is on, an alias is added beside the internal register name and displayed. Then, step S612
Proceed to.

Step S609: The designated display condition file is read from the storage unit.

Step S610: Data of the group configuration defined in the display condition file is obtained from the scan order list and the internal register data, and a group value is generated.

Step S611: The display data defined in the display format defined in the display condition file is displayed on the display unit.

Step S612: It is determined whether there is a change in the setting of the display menu. If the setting has been changed, the process returns to step S604. If the setting has not been changed, step S6.
Proceed to 13.

Step S613: It is determined whether there is an end instruction. If there is an end instruction, the process ends. If there is no end instruction, the process returns to step S612.

FIG. 7 shows a display example (1) of the analyzing means of the present invention. This display example corresponds to step S605 in FIG.
After the data for displaying the internal register corresponding to the scan order list is generated, the data is further sorted, rearranged and displayed. By displaying in this manner, the bit pattern of 0 and 1 indicating the state of the internal register extracted from the ASIC is converted into a bit unit or a hexadecimal number and displayed, so that there is no need to consider the correspondence of the scan order list. , ASIC can be quickly and easily analyzed.

FIG. 8 shows a display example (2) of the analyzing means of the present invention. This display example corresponds to step S60 in FIG.
7. Displayed in the process of step S608 (alias instruction: OFF). After generating data for displaying the internal register corresponding to the scan order list, the data is sorted, and the rearranged data is further stored in the register configuration. It is edited and displayed. By displaying in this manner, the data of the register configuration in which the internal registers are put together can be easily referred to, and the internal state of the ASIC can be analyzed more quickly and easily.

FIG. 9 shows a display example (3) of the analyzing means of the present invention. This display example corresponds to step S60 in FIG.
7. This is displayed in the processing of step S608 (alias instruction: ON). When the internal register name defined in the alias table as shown in FIG. 4 is displayed, an alias is added beside the internal register name. This is an example of displaying. By displaying in this manner, the internal register name can be referred to by a name that can be easily remembered by the analyst, and the internal state of the ASIC can be analyzed more quickly and easily.

FIG. 10 shows a display example (4) of the analyzing means of the present invention. This display example corresponds to step S609 in FIG.
5 is displayed in the processing of step S611, and displays the display data in the register, group configuration, and display format defined in the display condition file of FIG. By displaying in this way, the analyst can display and refer to the necessary internal registers in a group configuration in which the registers are conveniently arranged, so that the internal state of the ASIC can be analyzed more quickly and easily. it can.

[0046]

The present invention is embodied in the form described above, and has the following effects.

The internal state (internal register) of the ASIC is
It can be displayed based on the scan order list and in a unit such as a register, and the failure analysis of the printed circuit board or the ASIC itself can be greatly reduced.

Further, by providing an identification register in the ASIC, a scan order list corresponding to the ASIC can be automatically selected.

[Brief description of the drawings]

FIG. 1 is a structural block diagram of an ASIC internal state analyzer of the present invention.

FIG. 2 is an example of an internal configuration of an ASIC of the present invention.

FIG. 3 is a diagram illustrating an example of a scan order list.

FIG. 4 is a diagram illustrating an example of an alias table.

FIG. 5 is a diagram illustrating an example of a display condition file.

FIG. 6 is a processing flowchart of an embodiment of the analyzing means of the present invention.

FIG. 7 is a diagram (1) showing a display example of the analysis means of the present invention.

FIG. 8 is a display example (2) of the analysis means of the present invention.

FIG. 9 is a display example (3) of the analysis means of the present invention.

FIG. 10 is a display example diagram (4) of the analysis means of the present invention.

FIG. 11 is a structural block diagram of a conventional ASIC internal state analyzer.

FIG. 12 is an internal configuration diagram of a conventional ASIC.

FIG. 13 is a diagram illustrating an example of a display screen of internal register data in a conventional analysis unit.

[Explanation of symbols]

 Reference Signs List 10 printed circuit board 11 identification register 20 computer 21 analysis means 30 input / output unit 40 storage unit 41 scan order list 42 alias table 43 display condition file 44 internal register data file

Claims (6)

[Claims] An ASI for analyzing a failure of a printed circuit board including an ASIC by analyzing an internal state of the ASIC.
C In the internal state analyzer, the data of the internal register is read out from the ASIC to be analyzed through the scan chain, the scan order list of the ASIC to be analyzed is obtained from the storage unit, and the read internal register of the ASIC is read out. An ASIC internal state analysis apparatus, comprising: an analysis unit (21) for displaying data in an easy-to-understand display format in correspondence with the acquired scan order list. 2. The ASIC internal state analyzer according to claim 1, wherein an identification register (11) for storing an identification code and a version number of the ASIC is provided as a data register in the ASIC. An ASIC internal state analysis apparatus, comprising: means for acquiring an identification code and a version number, and acquiring a scan order list corresponding to the acquired identification code and version number from a storage unit. 3. The ASIC internal state analysis device according to claim 1, further comprising means for displaying internal register data extracted from the ASIC in correspondence with a scan order list. 4. The ASIC internal state analyzer according to claim 1, further comprising means for displaying internal register data extracted from the ASIC in register units based on a scan order list. apparatus. 5. The ASIC internal state analysis device according to claim 3, wherein an alias table (42) in which an instance of a flip-flop or a predetermined register in the scan order list is defined by an easy-to-remember name is provided and extracted from the ASIC. When displaying the internal register data in association with the scan order list, or when displaying in register units based on the scan order list, means for adding or replacing aliases and displaying the aliases is provided. Analysis device. 6. The ASIC internal state analyzer according to claim 3, wherein a register to be extracted from the scan order list and displayed, a group configuration of registers to be displayed and a display format thereof are defined. Display condition file (4
3) An ASIC internal state analysis apparatus, further comprising: means for displaying internal register data extracted from the ASIC in a display format defined in a display condition file (43).